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MLB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3E0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MLBC0

HCMR[0]

HCER[0]

HCBR[0]

MS1

MDAT[0]

HCMR[1]

MDWE[0]

HCER[1]

HCBR[1]

MSS

MSD

MDAT[1]

MDWE[1]

MIEN

MDAT[2]

MDWE[2]

MLBC1

ACTL

ACSR0

ACSR1

MDAT[3]

ACMR0

ACMR1

MDWE[3]

ACSR[0]

ACMR[0]

HCTL

HCMR0

HCMR1

HCER0

HCER1

HCBR0

HCBR1

ACSR[1]

ACMR[1]

MS0

MDAT0

MDAT1

MDAT2

MDAT3

MDWE0

MDWE1

MDWE2

MDWE3

MCTL

MADR


MLBC0

MediaLB Control 0 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MLBC0 MLBC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MLBEN MLBCLK ZERO MLBLK ASYRETRY CTLRETRY FCNT

MLBEN : MediaLB Enable
bits : 0 - 0 (1 bit)

MLBCLK : MLBCLK (MediaLB clock) Speed Select
bits : 2 - 4 (3 bit)

Enumeration: MLBCLKSelect

0x0 : _256_FS

256xFs (for MLBPEN = 0)

0x1 : _512_FS

512xFs (for MLBPEN = 0)

0x2 : _1024_FS

1024xFs (for MLBPEN = 0)

End of enumeration elements list.

ZERO : Must be Written to 0
bits : 5 - 5 (1 bit)

MLBLK : MediaLB Lock Status (read-only)
bits : 7 - 7 (1 bit)

ASYRETRY : Asynchronous Tx Packet Retry
bits : 12 - 12 (1 bit)

CTLRETRY : Control Tx Packet Retry
bits : 14 - 14 (1 bit)

FCNT : The number of frames per sub-buffer for synchronous channels
bits : 15 - 17 (3 bit)

Enumeration: FCNTSelect

0x0 : _1_FRAME

1 frame per sub-buffer (Operation is the same as Standard mode.)

0x1 : _2_FRAMES

2 frames per sub-buffer

0x2 : _4_FRAMES

4 frames per sub-buffer

0x3 : _8_FRAMES

8 frames per sub-buffer

0x4 : _16_FRAMES

16 frames per sub-buffer

0x5 : _32_FRAMES

32 frames per sub-buffer

0x6 : _64_FRAMES

64 frames per sub-buffer

End of enumeration elements list.


HCMR[0]

HBI Channel Mask 0 Register 0
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCMR[0] HCMR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM

CHM : Bitwise Channel Mask Bit [31:0]
bits : 0 - 31 (32 bit)


HCER[0]

HBI Channel Error 0 Register 0
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCER[0] HCER[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CERR

CERR : Bitwise Channel Error Bit [31:0]
bits : 0 - 31 (32 bit)


HCBR[0]

HBI Channel Busy 0 Register 0
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCBR[0] HCBR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHB

CHB : Bitwise Channel Busy Bit [31:0]
bits : 0 - 31 (32 bit)


MS1

MediaLB Channel Status1 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MS1 MS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCS

MCS : MediaLB Channel Status [63:32] (cleared by writing a 0)
bits : 0 - 31 (32 bit)


MDAT[0]

MIF Data 0 Register 0
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT[0] MDAT[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)


HCMR[1]

HBI Channel Mask 0 Register 0
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCMR[1] HCMR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM

CHM : Bitwise Channel Mask Bit [31:0]
bits : 0 - 31 (32 bit)


MDWE[0]

MIF Data Write Enable 0 Register 0
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE[0] MDWE[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)


HCER[1]

HBI Channel Error 0 Register 0
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCER[1] HCER[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CERR

CERR : Bitwise Channel Error Bit [31:0]
bits : 0 - 31 (32 bit)


HCBR[1]

HBI Channel Busy 0 Register 0
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCBR[1] HCBR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHB

CHB : Bitwise Channel Busy Bit [31:0]
bits : 0 - 31 (32 bit)


MSS

MediaLB System Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSS MSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTSYSCMD LKSYSCMD ULKSYSCMD CSSYSCMD SWSYSCMD SERVREQ

RSTSYSCMD : Reset System Command Detected in the System Quadlet (cleared by writing a 0)
bits : 0 - 0 (1 bit)

LKSYSCMD : Network Lock System Command Detected in the System Quadlet (cleared by writing a 0)
bits : 1 - 1 (1 bit)

ULKSYSCMD : Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0)
bits : 2 - 2 (1 bit)

CSSYSCMD : Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0)
bits : 3 - 3 (1 bit)

SWSYSCMD : Software System Command Detected in the System Quadlet (cleared by writing a 0)
bits : 4 - 4 (1 bit)

SERVREQ : Service Request Enabled
bits : 5 - 5 (1 bit)


MSD

MediaLB System Data Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSD MSD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SD0 SD1 SD2 SD3

SD0 : System Data (Byte 0)
bits : 0 - 7 (8 bit)

SD1 : System Data (Byte 1)
bits : 8 - 15 (8 bit)

SD2 : System Data (Byte 2)
bits : 16 - 23 (8 bit)

SD3 : System Data (Byte 3)
bits : 24 - 31 (8 bit)


MDAT[1]

MIF Data 0 Register 0
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT[1] MDAT[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)


MDWE[1]

MIF Data Write Enable 0 Register 0
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE[1] MDWE[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)


MIEN

MediaLB Interrupt Enable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIEN MIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISOC_PE ISOC_BUFO SYNC_PE ARX_DONE ARX_PE ARX_BREAK ATX_DONE ATX_PE ATX_BREAK CRX_DONE CRX_PE CRX_BREAK CTX_DONE CTX_PE CTX_BREAK

ISOC_PE : Isochronous Rx Protocol Error Enable
bits : 0 - 0 (1 bit)

ISOC_BUFO : Isochronous Rx Buffer Overflow Enable
bits : 1 - 1 (1 bit)

SYNC_PE : Synchronous Protocol Error Enable
bits : 16 - 16 (1 bit)

ARX_DONE : Asynchronous Rx Done Enable
bits : 17 - 17 (1 bit)

ARX_PE : Asynchronous Rx Protocol Error Enable
bits : 18 - 18 (1 bit)

ARX_BREAK : Asynchronous Rx Break Enable
bits : 19 - 19 (1 bit)

ATX_DONE : Asynchronous Tx Packet Done Enable
bits : 20 - 20 (1 bit)

ATX_PE : Asynchronous Tx Protocol Error Enable
bits : 21 - 21 (1 bit)

ATX_BREAK : Asynchronous Tx Break Enable
bits : 22 - 22 (1 bit)

CRX_DONE : Control Rx Packet Done Enable
bits : 24 - 24 (1 bit)

CRX_PE : Control Rx Protocol Error Enable
bits : 25 - 25 (1 bit)

CRX_BREAK : Control Rx Break Enable
bits : 26 - 26 (1 bit)

CTX_DONE : Control Tx Packet Done Enable
bits : 27 - 27 (1 bit)

CTX_PE : Control Tx Protocol Error Enable
bits : 28 - 28 (1 bit)

CTX_BREAK : Control Tx Break Enable
bits : 29 - 29 (1 bit)


MDAT[2]

MIF Data 0 Register 0
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT[2] MDAT[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)


MDWE[2]

MIF Data Write Enable 0 Register 0
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE[2] MDWE[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)


MLBC1

MediaLB Control 1 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MLBC1 MLBC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK CLKM NDA

LOCK : MediaLB Lock Error Status (cleared by writing a 0)
bits : 6 - 6 (1 bit)

CLKM : MediaLB Clock Missing Status (cleared by writing a 0)
bits : 7 - 7 (1 bit)

NDA : Node Device Address
bits : 8 - 15 (8 bit)


ACTL

AHB Control Register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTL ACTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCE SMX DMA_MODE MPB

SCE : Software Clear Enable
bits : 0 - 0 (1 bit)

SMX : AHB Interrupt Mux Enable
bits : 1 - 1 (1 bit)

DMA_MODE : DMA Mode
bits : 2 - 2 (1 bit)

MPB : DMA Packet Buffering Mode
bits : 4 - 4 (1 bit)

Enumeration: MPBSelect

0 : SINGLE_PACKET

Single-packet mode

1 : MULTIPLE_PACKET

Multiple-packet mode

End of enumeration elements list.


ACSR0

AHB Channel Status 0 Register 0
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACSR0 ACSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHS

CHS : Interrupt Status for Logical Channels [31:0] (cleared by writing a 1)
bits : 0 - 31 (32 bit)


ACSR1

AHB Channel Status 0 Register 0
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACSR1 ACSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHS

CHS : Interrupt Status for Logical Channels [31:0] (cleared by writing a 1)
bits : 0 - 31 (32 bit)


MDAT[3]

MIF Data 0 Register 0
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT[3] MDAT[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)


ACMR0

AHB Channel Mask 0 Register 0
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMR0 ACMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM

CHM : Bitwise Channel Mask Bits 31 to 0
bits : 0 - 31 (32 bit)


ACMR1

AHB Channel Mask 0 Register 0
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMR1 ACMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM

CHM : Bitwise Channel Mask Bits 31 to 0
bits : 0 - 31 (32 bit)


MDWE[3]

MIF Data Write Enable 0 Register 0
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE[3] MDWE[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)


ACSR[0]

AHB Channel Status 0 Register 0
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACSR[0] ACSR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHS

CHS : Interrupt Status for Logical Channels [31:0] (cleared by writing a 1)
bits : 0 - 31 (32 bit)


ACMR[0]

AHB Channel Mask 0 Register 0
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMR[0] ACMR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM

CHM : Bitwise Channel Mask Bits 31 to 0
bits : 0 - 31 (32 bit)


HCTL

HBI Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTL HCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST0 RST1 EN

RST0 : Address Generation Unit 0 Software Reset
bits : 0 - 0 (1 bit)

RST1 : Address Generation Unit 1 Software Reset
bits : 1 - 1 (1 bit)

EN : HBI Enable
bits : 15 - 15 (1 bit)


HCMR0

HBI Channel Mask 0 Register 0
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCMR0 HCMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM

CHM : Bitwise Channel Mask Bit [31:0]
bits : 0 - 31 (32 bit)


HCMR1

HBI Channel Mask 0 Register 0
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCMR1 HCMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM

CHM : Bitwise Channel Mask Bit [31:0]
bits : 0 - 31 (32 bit)


HCER0

HBI Channel Error 0 Register 0
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCER0 HCER0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CERR

CERR : Bitwise Channel Error Bit [31:0]
bits : 0 - 31 (32 bit)


HCER1

HBI Channel Error 0 Register 0
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCER1 HCER1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CERR

CERR : Bitwise Channel Error Bit [31:0]
bits : 0 - 31 (32 bit)


HCBR0

HBI Channel Busy 0 Register 0
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCBR0 HCBR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHB

CHB : Bitwise Channel Busy Bit [31:0]
bits : 0 - 31 (32 bit)


HCBR1

HBI Channel Busy 0 Register 0
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCBR1 HCBR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHB

CHB : Bitwise Channel Busy Bit [31:0]
bits : 0 - 31 (32 bit)


ACSR[1]

AHB Channel Status 0 Register 0
address_offset : 0xB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACSR[1] ACSR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHS

CHS : Interrupt Status for Logical Channels [31:0] (cleared by writing a 1)
bits : 0 - 31 (32 bit)


ACMR[1]

AHB Channel Mask 0 Register 0
address_offset : 0xB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMR[1] ACMR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM

CHM : Bitwise Channel Mask Bits 31 to 0
bits : 0 - 31 (32 bit)


MS0

MediaLB Channel Status 0 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MS0 MS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCS

MCS : MediaLB Channel Status [31:0] (cleared by writing a 0)
bits : 0 - 31 (32 bit)


MDAT0

MIF Data 0 Register 0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT0 MDAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)


MDAT1

MIF Data 0 Register 0
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT1 MDAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)


MDAT2

MIF Data 0 Register 0
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT2 MDAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)


MDAT3

MIF Data 0 Register 0
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT3 MDAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)


MDWE0

MIF Data Write Enable 0 Register 0
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE0 MDWE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)


MDWE1

MIF Data Write Enable 0 Register 0
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE1 MDWE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)


MDWE2

MIF Data Write Enable 0 Register 0
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE2 MDWE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)


MDWE3

MIF Data Write Enable 0 Register 0
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE3 MDWE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)


MCTL

MIF Control Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL MCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XCMP

XCMP : Transfer Complete (Write 0 to Clear)
bits : 0 - 0 (1 bit)


MADR

MIF Address Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MADR MADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR TB WNR

ADDR : CTR or DBR Address
bits : 0 - 13 (14 bit)

TB : Target Location Bit
bits : 30 - 30 (1 bit)

Enumeration: TBSelect

0 : CTR

Selects CTR

1 : DBR

Selects DBR

End of enumeration elements list.

WNR : Write-Not-Read Selection
bits : 31 - 31 (1 bit)



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