\n
address_offset : 0x0 Bytes (0x0)
size : 0x1A0 byte (0x0)
mem_usage : registers
protection : not protected
HINF_CFG_DATA0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USER_ID_FN1 :
bits : 0 - 15 (16 bit)
DEVICE_ID_FN1 :
bits : 16 - 31 (16 bit)
HINF_CFG_DATA7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN_STATE :
bits : 0 - 7 (8 bit)
CHIP_STATE :
bits : 8 - 15 (8 bit)
SDIO_RST :
bits : 16 - 16 (1 bit)
SDIO_IOREADY0 :
bits : 17 - 17 (1 bit)
HINF_CIS_CONF0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIS_CONF_W0 :
bits : 0 - 31 (32 bit)
HINF_CIS_CONF1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIS_CONF_W1 :
bits : 0 - 31 (32 bit)
HINF_CIS_CONF2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIS_CONF_W2 :
bits : 0 - 31 (32 bit)
HINF_CIS_CONF3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIS_CONF_W3 :
bits : 0 - 31 (32 bit)
HINF_CIS_CONF4
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIS_CONF_W4 :
bits : 0 - 31 (32 bit)
HINF_CIS_CONF5
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIS_CONF_W5 :
bits : 0 - 31 (32 bit)
HINF_CIS_CONF6
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIS_CONF_W6 :
bits : 0 - 31 (32 bit)
HINF_CIS_CONF7
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIS_CONF_W7 :
bits : 0 - 31 (32 bit)
HINF_CFG_DATA1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDIO_ENABLE :
bits : 0 - 0 (1 bit)
SDIO_IOREADY1 :
bits : 1 - 1 (1 bit)
HIGHSPEED_ENABLE :
bits : 2 - 2 (1 bit)
HIGHSPEED_MODE :
bits : 3 - 3 (1 bit)
SDIO_CD_ENABLE :
bits : 4 - 4 (1 bit)
SDIO_IOREADY2 :
bits : 5 - 5 (1 bit)
SDIO_INT_MASK :
bits : 6 - 6 (1 bit)
IOENABLE2 :
bits : 7 - 7 (1 bit)
CD_DISABLE :
bits : 8 - 8 (1 bit)
FUNC1_EPS :
bits : 9 - 9 (1 bit)
EMP :
bits : 10 - 10 (1 bit)
IOENABLE1 :
bits : 11 - 11 (1 bit)
SDIO20_CONF0 :
bits : 12 - 15 (4 bit)
SDIO_VER :
bits : 16 - 27 (12 bit)
FUNC2_EPS :
bits : 28 - 28 (1 bit)
SDIO20_CONF1 :
bits : 29 - 31 (3 bit)
HINF_CFG_DATA16
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USER_ID_FN2 :
bits : 0 - 15 (16 bit)
DEVICE_ID_FN2 :
bits : 16 - 31 (16 bit)
HINF_DATE
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDIO_DATE :
bits : 0 - 31 (32 bit)
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