\n
address_offset : 0x0 Bytes (0x0)
size : 0x6A0 byte (0x0)
mem_usage : RTC CNTL registers
protection : not protected
address_offset : 0x200C6000 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : Internal I2C registers
protection : not protected
RTC_CNTL_OPTIONS0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_STALL_APPCPU_C0 :
bits : 0 - 1 (2 bit)
SW_STALL_PROCPU_C0 :
bits : 2 - 3 (2 bit)
SW_APPCPU_RST :
bits : 4 - 4 (1 bit)
SW_PROCPU_RST :
bits : 5 - 5 (1 bit)
BB_I2C_FORCE_PD :
bits : 6 - 6 (1 bit)
BB_I2C_FORCE_PU :
bits : 7 - 7 (1 bit)
BBPLL_I2C_FORCE_PD :
bits : 8 - 8 (1 bit)
BBPLL_I2C_FORCE_PU :
bits : 9 - 9 (1 bit)
BBPLL_FORCE_PD :
bits : 10 - 10 (1 bit)
BBPLL_FORCE_PU :
bits : 11 - 11 (1 bit)
XTL_FORCE_PD :
bits : 12 - 12 (1 bit)
XTL_FORCE_PU :
bits : 13 - 13 (1 bit)
BIAS_SLEEP_FOLW_8M :
bits : 14 - 14 (1 bit)
BIAS_FORCE_SLEEP :
bits : 15 - 15 (1 bit)
BIAS_FORCE_NOSLEEP :
bits : 16 - 16 (1 bit)
BIAS_I2C_FOLW_8M :
bits : 17 - 17 (1 bit)
BIAS_I2C_FORCE_PD :
bits : 18 - 18 (1 bit)
BIAS_I2C_FORCE_PU :
bits : 19 - 19 (1 bit)
BIAS_CORE_FOLW_8M :
bits : 20 - 20 (1 bit)
BIAS_CORE_FORCE_PD :
bits : 21 - 21 (1 bit)
BIAS_CORE_FORCE_PU :
bits : 22 - 22 (1 bit)
XTL_FORCE_ISO :
bits : 23 - 23 (1 bit)
PLL_FORCE_ISO :
bits : 24 - 24 (1 bit)
ANALOG_FORCE_ISO :
bits : 25 - 25 (1 bit)
XTL_FORCE_NOISO :
bits : 26 - 26 (1 bit)
PLL_FORCE_NOISO :
bits : 27 - 27 (1 bit)
ANALOG_FORCE_NOISO :
bits : 28 - 28 (1 bit)
DG_WRAP_FORCE_RST :
bits : 29 - 29 (1 bit)
DG_WRAP_FORCE_NORST :
bits : 30 - 30 (1 bit)
SW_SYS_RST :
bits : 31 - 31 (1 bit)
RTC_CNTL_TIME0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIME_LO :
bits : 0 - 31 (32 bit)
RTC_CNTL_DATE
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTL_DATE :
bits : 0 - 27 (28 bit)
RTC_CNTL_TIME1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIME_HI :
bits : 0 - 15 (16 bit)
RTC_CNTL_STATE0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUCH_WAKEUP_FORCE_EN :
bits : 20 - 20 (1 bit)
ULP_CP_WAKEUP_FORCE_EN :
bits : 21 - 21 (1 bit)
APB2RTC_BRIDGE_SEL :
bits : 22 - 22 (1 bit)
TOUCH_SLP_TIMER_EN :
bits : 23 - 23 (1 bit)
ULP_CP_SLP_TIMER_EN :
bits : 24 - 24 (1 bit)
SDIO_ACTIVE_IND :
bits : 28 - 28 (1 bit)
SLP_WAKEUP :
bits : 29 - 29 (1 bit)
SLP_REJECT :
bits : 30 - 30 (1 bit)
SLEEP_EN :
bits : 31 - 31 (1 bit)
RTC_CNTL_TIMER1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_STALL_EN :
bits : 0 - 0 (1 bit)
CPU_STALL_WAIT :
bits : 1 - 5 (5 bit)
CK8M_WAIT :
bits : 6 - 13 (8 bit)
XTL_BUF_WAIT :
bits : 14 - 23 (10 bit)
PLL_BUF_WAIT :
bits : 24 - 31 (8 bit)
RTC_CNTL_TIMER2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULPCP_TOUCH_START_WAIT :
bits : 15 - 23 (9 bit)
MIN_TIME_CK8M_OFF :
bits : 24 - 31 (8 bit)
APLL I2C Register
address_offset : 0x200C600C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK : Block
bits : 0 - 7 (8 bit)
ADDR : Address
bits : 8 - 15 (8 bit)
DATA : Data
bits : 16 - 23 (8 bit)
WRITE : Write
bits : 24 - 24 (1 bit)
BUSY : Ready
bits : 25 - 25 (1 bit)
PLL I2C Register
address_offset : 0x200C6010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK : Block
bits : 0 - 7 (8 bit)
ADDR : Address
bits : 8 - 15 (8 bit)
DATA : Data
bits : 16 - 23 (8 bit)
WRITE : Write
bits : 24 - 24 (1 bit)
BUSY : Ready
bits : 25 - 25 (1 bit)
RTC_CNTL_TIMER3
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIFI_WAIT_TIMER :
bits : 0 - 8 (9 bit)
WIFI_POWERUP_TIMER :
bits : 9 - 15 (7 bit)
ROM_RAM_WAIT_TIMER :
bits : 16 - 24 (9 bit)
ROM_RAM_POWERUP_TIMER :
bits : 25 - 31 (7 bit)
RTC_CNTL_TIMER4
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TIMER :
bits : 0 - 8 (9 bit)
POWERUP_TIMER :
bits : 9 - 15 (7 bit)
DG_WRAP_WAIT_TIMER :
bits : 16 - 24 (9 bit)
DG_WRAP_POWERUP_TIMER :
bits : 25 - 31 (7 bit)
RTC_CNTL_TIMER5
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULP_CP_SUBTIMER_PREDIV :
bits : 0 - 7 (8 bit)
MIN_SLP_VAL :
bits : 8 - 15 (8 bit)
RTCMEM_WAIT_TIMER :
bits : 16 - 24 (9 bit)
RTCMEM_POWERUP_TIMER :
bits : 25 - 31 (7 bit)
RTC_CNTL_ANA_CONF
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLA_FORCE_PD :
bits : 23 - 23 (1 bit)
PLLA_FORCE_PU :
bits : 24 - 24 (1 bit)
BBPLL_CAL_SLP_START :
bits : 25 - 25 (1 bit)
PVTMON_PU :
bits : 26 - 26 (1 bit)
TXRF_I2C_PU :
bits : 27 - 27 (1 bit)
RFRX_PBUS_PU :
bits : 28 - 28 (1 bit)
CKGEN_I2C_PU :
bits : 30 - 30 (1 bit)
PLL_I2C_PU :
bits : 31 - 31 (1 bit)
RTC_CNTL_RESET_STATE
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET_CAUSE_PROCPU :
bits : 0 - 5 (6 bit)
RESET_CAUSE_APPCPU :
bits : 6 - 11 (6 bit)
APPCPU_STAT_VECTOR_SEL :
bits : 12 - 12 (1 bit)
PROCPU_STAT_VECTOR_SEL :
bits : 13 - 13 (1 bit)
RTC_CNTL_WAKEUP_STATE
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEUP_CAUSE :
bits : 0 - 10 (11 bit)
WAKEUP_ENA :
bits : 11 - 21 (11 bit)
GPIO_WAKEUP_FILTER :
bits : 22 - 22 (1 bit)
RTC_CNTL_INT_ENA
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLP_WAKEUP_INT_ENA :
bits : 0 - 0 (1 bit)
SLP_REJECT_INT_ENA :
bits : 1 - 1 (1 bit)
SDIO_IDLE_INT_ENA :
bits : 2 - 2 (1 bit)
WDT_INT_ENA :
bits : 3 - 3 (1 bit)
TIME_VALID_INT_ENA :
bits : 4 - 4 (1 bit)
ULP_CP_INT_ENA :
bits : 5 - 5 (1 bit)
TOUCH_INT_ENA :
bits : 6 - 6 (1 bit)
BROWN_OUT_INT_ENA :
bits : 7 - 7 (1 bit)
MAIN_TIMER_INT_ENA :
bits : 8 - 8 (1 bit)
RTC_CNTL_SLP_TIMER0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLP_VAL_LO :
bits : 0 - 31 (32 bit)
RTC_CNTL_INT_RAW
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLP_WAKEUP_INT_RAW :
bits : 0 - 0 (1 bit)
SLP_REJECT_INT_RAW :
bits : 1 - 1 (1 bit)
SDIO_IDLE_INT_RAW :
bits : 2 - 2 (1 bit)
WDT_INT_RAW :
bits : 3 - 3 (1 bit)
TIME_VALID_INT_RAW :
bits : 4 - 4 (1 bit)
ULP_CP_INT_RAW :
bits : 5 - 5 (1 bit)
TOUCH_INT_RAW :
bits : 6 - 6 (1 bit)
BROWN_OUT_INT_RAW :
bits : 7 - 7 (1 bit)
MAIN_TIMER_INT_RAW :
bits : 8 - 8 (1 bit)
RTC_CNTL_INT_ST
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLP_WAKEUP_INT_ST :
bits : 0 - 0 (1 bit)
SLP_REJECT_INT_ST :
bits : 1 - 1 (1 bit)
SDIO_IDLE_INT_ST :
bits : 2 - 2 (1 bit)
WDT_INT_ST :
bits : 3 - 3 (1 bit)
TIME_VALID_INT_ST :
bits : 4 - 4 (1 bit)
SAR_INT_ST :
bits : 5 - 5 (1 bit)
TOUCH_INT_ST :
bits : 6 - 6 (1 bit)
BROWN_OUT_INT_ST :
bits : 7 - 7 (1 bit)
MAIN_TIMER_INT_ST :
bits : 8 - 8 (1 bit)
RTC_CNTL_INT_CLR
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLP_WAKEUP_INT_CLR :
bits : 0 - 0 (1 bit)
SLP_REJECT_INT_CLR :
bits : 1 - 1 (1 bit)
SDIO_IDLE_INT_CLR :
bits : 2 - 2 (1 bit)
WDT_INT_CLR :
bits : 3 - 3 (1 bit)
TIME_VALID_INT_CLR :
bits : 4 - 4 (1 bit)
SAR_INT_CLR :
bits : 5 - 5 (1 bit)
TOUCH_INT_CLR :
bits : 6 - 6 (1 bit)
BROWN_OUT_INT_CLR :
bits : 7 - 7 (1 bit)
MAIN_TIMER_INT_CLR :
bits : 8 - 8 (1 bit)
RTC_CNTL_STORE0
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCRATCH0 :
bits : 0 - 31 (32 bit)
RTC_CNTL_STORE1
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCRATCH1 :
bits : 0 - 31 (32 bit)
RTC_CNTL_STORE2
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCRATCH2 :
bits : 0 - 31 (32 bit)
RTC_CNTL_STORE3
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCRATCH3 :
bits : 0 - 31 (32 bit)
RTC_CNTL_EXT_XTL_CONF
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL_EXT_CTR_LV :
bits : 30 - 30 (1 bit)
XTL_EXT_CTR_EN :
bits : 31 - 31 (1 bit)
RTC_CNTL_EXT_WAKEUP_CONF
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXT_WAKEUP0_LV :
bits : 30 - 30 (1 bit)
EXT_WAKEUP1_LV :
bits : 31 - 31 (1 bit)
RTC_CNTL_SLP_REJECT_CONF
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_REJECT_EN :
bits : 24 - 24 (1 bit)
SDIO_REJECT_EN :
bits : 25 - 25 (1 bit)
LIGHT_SLP_REJECT_EN :
bits : 26 - 26 (1 bit)
DEEP_SLP_REJECT_EN :
bits : 27 - 27 (1 bit)
REJECT_CAUSE :
bits : 28 - 31 (4 bit)
RTC_CNTL_CPU_PERIOD_CONF
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPUSEL_CONF :
bits : 29 - 29 (1 bit)
CPUPERIOD_SEL :
bits : 30 - 31 (2 bit)
RTC_CNTL_SDIO_ACT_CONF
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDIO_ACT_DNUM :
bits : 22 - 31 (10 bit)
RTC_CNTL_CLK_CONF
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CK8M_DIV :
bits : 4 - 5 (2 bit)
Enumeration: CK8M_DIV ( read-write )
0 : div128
div128
1 : div256
div256
2 : div512
div512
3 : div1024
div1024
End of enumeration elements list.
ENB_CK8M :
bits : 6 - 6 (1 bit)
ENB_CK8M_DIV :
bits : 7 - 7 (1 bit)
DIG_XTAL32K_EN :
bits : 8 - 8 (1 bit)
Enumeration: DIG_XTAL32K_EN ( read-write )
0 : Disable
Disable CK_XTAL_32K
1 : Enable
Enable CK_XTAL_32K for digital core(no relation to RTC core)
End of enumeration elements list.
DIG_CLK8M_D256_EN :
bits : 9 - 9 (1 bit)
Enumeration: DIG_CLK8M_D256_EN ( read-write )
0 : Disable
Disable CK8M_D256_OUT
1 : Enable
Enable CK8M_D256_OUT for digital core (no relation to RTC core)
End of enumeration elements list.
DIG_CLK8M_EN :
bits : 10 - 10 (1 bit)
Enumeration: DIG_CLK8M_EN ( read-write )
0 : Disable
Disable CK8M
1 : Enable
Enable CK8M for digital core (no relation to RTC core)
End of enumeration elements list.
CK8M_DFREQ_FORCE :
bits : 11 - 11 (1 bit)
CK8M_DIV_SEL :
bits : 12 - 14 (3 bit)
XTAL_FORCE_NOGATING :
bits : 15 - 15 (1 bit)
CK8M_FORCE_NOGATING :
bits : 16 - 16 (1 bit)
CK8M_DFREQ :
bits : 17 - 24 (8 bit)
CK8M_FORCE_PD :
bits : 25 - 25 (1 bit)
Enumeration: CK8M_FORCE_PD ( read-write )
0 : Clear
Don't force power down
1 : Force
Force power down
End of enumeration elements list.
CK8M_FORCE_PU :
bits : 26 - 26 (1 bit)
Enumeration: CK8M_FORCE_PU ( read-write )
0 : Clear
Don't force power up
1 : Force
Force power up
End of enumeration elements list.
SOC_CLK_SEL :
bits : 27 - 28 (2 bit)
Enumeration: SOC_CLK_SEL ( read-write )
0 : XTAL
Select XTAL clock
1 : PLL
Select PLL clock
2 : CK8M
Select CK8M clock
3 : APLL
Select APLL clock
End of enumeration elements list.
FAST_CLK_RTC_SEL :
bits : 29 - 29 (1 bit)
Enumeration: FAST_CLK_RTC_SEL ( read-write )
0 : XTAL
Select XTAL
1 : CK8M
Select CK8M
End of enumeration elements list.
ANA_CLK_RTC_SEL :
bits : 30 - 31 (2 bit)
Enumeration: ANA_CLK_RTC_SEL ( read-write )
0 : SLOW_CK
Select slow clock
1 : CK_XTAL_32K
Select XTAL_32K
2 : CK8M_D256_OUT
Internal 8 MHz RC oscillator, divided by 256
End of enumeration elements list.
RTC_CNTL_SDIO_CONF
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDIO_PD_EN :
bits : 21 - 21 (1 bit)
SDIO_FORCE :
bits : 22 - 22 (1 bit)
SDIO_TIEH :
bits : 23 - 23 (1 bit)
REG1P8_READY :
bits : 24 - 24 (1 bit)
DREFL_SDIO :
bits : 25 - 26 (2 bit)
DREFM_SDIO :
bits : 27 - 28 (2 bit)
DREFH_SDIO :
bits : 29 - 30 (2 bit)
XPD_SDIO_REG :
bits : 31 - 31 (1 bit)
RTC_CNTL_BIAS_CONF
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCK_DCAP_FORCE :
bits : 7 - 7 (1 bit)
DIG_DBIAS_SLP :
bits : 8 - 10 (3 bit)
DIG_DBIAS_WAK :
bits : 11 - 13 (3 bit)
SCK_DCAP :
bits : 14 - 21 (8 bit)
DBIAS_SLP :
bits : 22 - 24 (3 bit)
DBG_ATTEN :
bits : 24 - 25 (2 bit)
DBIAS_WAK :
bits : 25 - 27 (3 bit)
ENB_SCK_XTAL :
bits : 26 - 26 (1 bit)
INC_HEARTBEAT_REFRESH :
bits : 27 - 27 (1 bit)
DEC_HEARTBEAT_PERIOD :
bits : 28 - 28 (1 bit)
DBOOST_FORCE_PD :
bits : 28 - 28 (1 bit)
INC_HEARTBEAT_PERIOD :
bits : 29 - 29 (1 bit)
DBOOST_FORCE_PU :
bits : 29 - 29 (1 bit)
DEC_HEARTBEAT_WIDTH :
bits : 30 - 30 (1 bit)
FORCE_PD :
bits : 30 - 30 (1 bit)
RST_BIAS_I2C :
bits : 31 - 31 (1 bit)
FORCE_PU :
bits : 31 - 31 (1 bit)
RTC Control Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCK_DCAP_FORCE : 150kHz tuning force
bits : 7 - 7 (1 bit)
DIG_DBIAS_SLP : DBIAS during wakeup
bits : 8 - 10 (3 bit)
Enumeration:
End of enumeration elements list.
DIG_DBIAS_WAK : DBIAS during wakeup
bits : 11 - 13 (3 bit)
Enumeration:
End of enumeration elements list.
SCK_DCAP : 150kHz oscillator tuning
bits : 14 - 21 (8 bit)
DBIAS_SLP : RTC DBIAS during sleep
bits : 22 - 24 (3 bit)
Enumeration:
End of enumeration elements list.
DBIAS_WAK : RTC DBIAS during wakeup
bits : 25 - 27 (3 bit)
Enumeration: DBIAS_WAK ( read-write )
0 : BIAS_0V90
Core voltage 0.90V
1 : BIAS_0V95
Core voltage 0.95V
2 : BIAS_1V00
Core voltage 1.00V
3 : BIAS_1V05
Core voltage 1.05V
4 : BIAS_1V10
Core voltage 1.10V
5 : BIAS_1V15
Core voltage 1.15V
6 : BIAS_1V20
Core voltage 1.20V
7 : BIAS_1V25
Core voltage 1.25V
End of enumeration elements list.
FORCE_DBOOST_PD : Force DBOOST power down
bits : 28 - 28 (1 bit)
FORCE_DBOOST_PU : Force DBOOST power up
bits : 29 - 29 (1 bit)
FORCE_PD : Force RTC power down (decrease voltage to 0.8V or lower)
bits : 30 - 30 (1 bit)
FORCE_PU : Force RTC power up
bits : 31 - 31 (1 bit)
RTC_CNTL_SLP_TIMER1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLP_VAL_HI :
bits : 0 - 15 (16 bit)
MAIN_TIMER_ALARM_EN :
bits : 16 - 16 (1 bit)
RTC_CNTL_PWC
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FASTMEM_FORCE_NOISO :
bits : 0 - 0 (1 bit)
FASTMEM_FORCE_ISO :
bits : 1 - 1 (1 bit)
SLOWMEM_FORCE_NOISO :
bits : 2 - 2 (1 bit)
SLOWMEM_FORCE_ISO :
bits : 3 - 3 (1 bit)
FORCE_ISO :
bits : 4 - 4 (1 bit)
FORCE_NOISO :
bits : 5 - 5 (1 bit)
FASTMEM_FOLW_CPU :
bits : 6 - 6 (1 bit)
FASTMEM_FORCE_LPD :
bits : 7 - 7 (1 bit)
FASTMEM_FORCE_LPU :
bits : 8 - 8 (1 bit)
SLOWMEM_FOLW_CPU :
bits : 9 - 9 (1 bit)
SLOWMEM_FORCE_LPD :
bits : 10 - 10 (1 bit)
SLOWMEM_FORCE_LPU :
bits : 11 - 11 (1 bit)
FASTMEM_FORCE_PD :
bits : 12 - 12 (1 bit)
FASTMEM_FORCE_PU :
bits : 13 - 13 (1 bit)
FASTMEM_PD_EN :
bits : 14 - 14 (1 bit)
SLOWMEM_FORCE_PD :
bits : 15 - 15 (1 bit)
SLOWMEM_FORCE_PU :
bits : 16 - 16 (1 bit)
SLOWMEM_PD_EN :
bits : 17 - 17 (1 bit)
FORCE_PD :
bits : 18 - 18 (1 bit)
FORCE_PU :
bits : 19 - 19 (1 bit)
PD_EN :
bits : 20 - 20 (1 bit)
RTC_CNTL_DIG_PWC
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSLP_MEM_FORCE_PD :
bits : 3 - 3 (1 bit)
LSLP_MEM_FORCE_PU :
bits : 4 - 4 (1 bit)
ROM0_FORCE_PD :
bits : 5 - 5 (1 bit)
ROM0_FORCE_PU :
bits : 6 - 6 (1 bit)
INTER_RAM0_FORCE_PD :
bits : 7 - 7 (1 bit)
INTER_RAM0_FORCE_PU :
bits : 8 - 8 (1 bit)
INTER_RAM1_FORCE_PD :
bits : 9 - 9 (1 bit)
INTER_RAM1_FORCE_PU :
bits : 10 - 10 (1 bit)
INTER_RAM2_FORCE_PD :
bits : 11 - 11 (1 bit)
INTER_RAM2_FORCE_PU :
bits : 12 - 12 (1 bit)
INTER_RAM3_FORCE_PD :
bits : 13 - 13 (1 bit)
INTER_RAM3_FORCE_PU :
bits : 14 - 14 (1 bit)
INTER_RAM4_FORCE_PD :
bits : 15 - 15 (1 bit)
INTER_RAM4_FORCE_PU :
bits : 16 - 16 (1 bit)
WIFI_FORCE_PD :
bits : 17 - 17 (1 bit)
WIFI_FORCE_PU :
bits : 18 - 18 (1 bit)
DG_WRAP_FORCE_PD :
bits : 19 - 19 (1 bit)
DG_WRAP_FORCE_PU :
bits : 20 - 20 (1 bit)
ROM0_PD_EN :
bits : 24 - 24 (1 bit)
INTER_RAM0_PD_EN :
bits : 25 - 25 (1 bit)
INTER_RAM1_PD_EN :
bits : 26 - 26 (1 bit)
INTER_RAM2_PD_EN :
bits : 27 - 27 (1 bit)
INTER_RAM3_PD_EN :
bits : 28 - 28 (1 bit)
INTER_RAM4_PD_EN :
bits : 29 - 29 (1 bit)
WIFI_PD_EN :
bits : 30 - 30 (1 bit)
DG_WRAP_PD_EN :
bits : 31 - 31 (1 bit)
RTC_CNTL_DIG_ISO
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIG_ISO_FORCE_OFF :
bits : 7 - 7 (1 bit)
DIG_ISO_FORCE_ON :
bits : 8 - 8 (1 bit)
DG_PAD_AUTOHOLD :
bits : 9 - 9 (1 bit)
CLR_DG_PAD_AUTOHOLD :
bits : 10 - 10 (1 bit)
DG_PAD_AUTOHOLD_EN :
bits : 11 - 11 (1 bit)
DG_PAD_FORCE_NOISO :
bits : 12 - 12 (1 bit)
DG_PAD_FORCE_ISO :
bits : 13 - 13 (1 bit)
DG_PAD_FORCE_UNHOLD :
bits : 14 - 14 (1 bit)
DG_PAD_FORCE_HOLD :
bits : 15 - 15 (1 bit)
ROM0_FORCE_ISO :
bits : 16 - 16 (1 bit)
ROM0_FORCE_NOISO :
bits : 17 - 17 (1 bit)
INTER_RAM0_FORCE_ISO :
bits : 18 - 18 (1 bit)
INTER_RAM0_FORCE_NOISO :
bits : 19 - 19 (1 bit)
INTER_RAM1_FORCE_ISO :
bits : 20 - 20 (1 bit)
INTER_RAM1_FORCE_NOISO :
bits : 21 - 21 (1 bit)
INTER_RAM2_FORCE_ISO :
bits : 22 - 22 (1 bit)
INTER_RAM2_FORCE_NOISO :
bits : 23 - 23 (1 bit)
INTER_RAM3_FORCE_ISO :
bits : 24 - 24 (1 bit)
INTER_RAM3_FORCE_NOISO :
bits : 25 - 25 (1 bit)
INTER_RAM4_FORCE_ISO :
bits : 26 - 26 (1 bit)
INTER_RAM4_FORCE_NOISO :
bits : 27 - 27 (1 bit)
WIFI_FORCE_ISO :
bits : 28 - 28 (1 bit)
WIFI_FORCE_NOISO :
bits : 29 - 29 (1 bit)
DG_WRAP_FORCE_ISO :
bits : 30 - 30 (1 bit)
DG_WRAP_FORCE_NOISO :
bits : 31 - 31 (1 bit)
RTC_CNTL_WDTCONFIG0
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_PAUSE_IN_SLP :
bits : 7 - 7 (1 bit)
WDT_APPCPU_RESET_EN :
bits : 8 - 8 (1 bit)
WDT_PROCPU_RESET_EN :
bits : 9 - 9 (1 bit)
WDT_FLASHBOOT_MOD_EN :
bits : 10 - 10 (1 bit)
WDT_SYS_RESET_LENGTH :
bits : 11 - 13 (3 bit)
Enumeration:
End of enumeration elements list.
WDT_CPU_RESET_LENGTH :
bits : 14 - 16 (3 bit)
Enumeration: WDT_CPU_RESET_LENGTH ( read-write )
0 : T100ns
100ns
1 : T200ns
200ns
2 : T300ns
300ns
3 : T400ns
400ns
4 : T500ns
500ns
5 : T800ns
800ns
6 : T1600ns
1600ns
7 : T3200ns
3200ns
End of enumeration elements list.
WDT_LEVEL_INT_EN :
bits : 17 - 17 (1 bit)
WDT_EDGE_INT_EN :
bits : 18 - 18 (1 bit)
WDT_STG3 :
bits : 19 - 21 (3 bit)
Enumeration:
End of enumeration elements list.
WDT_STG2 :
bits : 22 - 24 (3 bit)
Enumeration:
End of enumeration elements list.
WDT_STG1 :
bits : 25 - 27 (3 bit)
Enumeration:
End of enumeration elements list.
WDT_STG0 :
bits : 28 - 30 (3 bit)
Enumeration: WDT_STG0 ( read-write )
0 : Disable
Disabled
1 : Interrupt
Trigger an interrupt
2 : ResetCPU
Reset CPU core
3 : ResetSystem
Reset System, but not RTC
4 : ResetRTC
Reset System & RTC
End of enumeration elements list.
WDT_EN :
bits : 31 - 31 (1 bit)
RTC_CNTL_WDTCONFIG1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_STG0_HOLD :
bits : 0 - 31 (32 bit)
RTC_CNTL_WDTCONFIG2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_STG1_HOLD :
bits : 0 - 31 (32 bit)
RTC_CNTL_WDTCONFIG3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_STG2_HOLD :
bits : 0 - 31 (32 bit)
RTC_CNTL_WDTCONFIG4
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_STG3_HOLD :
bits : 0 - 31 (32 bit)
RTC_CNTL_WDTFEED
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_FEED :
bits : 31 - 31 (1 bit)
RTC_CNTL_WDTWPROTECT
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_WKEY :
bits : 0 - 31 (32 bit)
RTC_CNTL_TEST_MUX
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENT_RTC :
bits : 29 - 29 (1 bit)
DTEST_RTC :
bits : 30 - 31 (2 bit)
RTC_CNTL_SW_CPU_STALL
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_STALL_APPCPU_C1 :
bits : 20 - 25 (6 bit)
SW_STALL_PROCPU_C1 :
bits : 26 - 31 (6 bit)
RTC_CNTL_STORE4
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCRATCH4 :
bits : 0 - 31 (32 bit)
RTC_CNTL_STORE5
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCRATCH5 :
bits : 0 - 31 (32 bit)
RTC_CNTL_STORE6
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCRATCH6 :
bits : 0 - 31 (32 bit)
RTC_CNTL_STORE7
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCRATCH7 :
bits : 0 - 31 (32 bit)
RTC_CNTL_TIME_UPDATE
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIME_VALID :
bits : 30 - 30 (1 bit)
TIME_UPDATE :
bits : 31 - 31 (1 bit)
RTC_CNTL_DIAG1
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOW_POWER_DIAG1 :
bits : 0 - 31 (32 bit)
RTC_CNTL_HOLD_FORCE
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1_HOLD_FORCE :
bits : 0 - 0 (1 bit)
ADC2_HOLD_FORCE :
bits : 1 - 1 (1 bit)
PDAC1_HOLD_FORCE :
bits : 2 - 2 (1 bit)
PDAC2_HOLD_FORCE :
bits : 3 - 3 (1 bit)
SENSE1_HOLD_FORCE :
bits : 4 - 4 (1 bit)
SENSE2_HOLD_FORCE :
bits : 5 - 5 (1 bit)
SENSE3_HOLD_FORCE :
bits : 6 - 6 (1 bit)
SENSE4_HOLD_FORCE :
bits : 7 - 7 (1 bit)
TOUCH_PAD0_HOLD_FORCE :
bits : 8 - 8 (1 bit)
TOUCH_PAD1_HOLD_FORCE :
bits : 9 - 9 (1 bit)
TOUCH_PAD2_HOLD_FORCE :
bits : 10 - 10 (1 bit)
TOUCH_PAD3_HOLD_FORCE :
bits : 11 - 11 (1 bit)
TOUCH_PAD4_HOLD_FORCE :
bits : 12 - 12 (1 bit)
TOUCH_PAD5_HOLD_FORCE :
bits : 13 - 13 (1 bit)
TOUCH_PAD6_HOLD_FORCE :
bits : 14 - 14 (1 bit)
TOUCH_PAD7_HOLD_FORCE :
bits : 15 - 15 (1 bit)
X32P_HOLD_FORCE :
bits : 16 - 16 (1 bit)
X32N_HOLD_FORCE :
bits : 17 - 17 (1 bit)
RTC_CNTL_EXT_WAKEUP1
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXT_WAKEUP1_SEL :
bits : 0 - 17 (18 bit)
EXT_WAKEUP1_STATUS_CLR :
bits : 18 - 18 (1 bit)
RTC_CNTL_EXT_WAKEUP1_STATUS
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXT_WAKEUP1_STATUS :
bits : 0 - 17 (18 bit)
RTC_CNTL_BROWN_OUT
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BROWN_OUT_CLOSE_FLASH_ENA :
bits : 14 - 14 (1 bit)
BROWN_OUT_PD_RF_ENA :
bits : 15 - 15 (1 bit)
BROWN_OUT_RST_WAIT :
bits : 16 - 25 (10 bit)
BROWN_OUT_RST_ENA :
bits : 26 - 26 (1 bit)
DBROWN_OUT_THRES :
bits : 27 - 29 (3 bit)
BROWN_OUT_ENA :
bits : 30 - 30 (1 bit)
BROWN_OUT_DET :
bits : 31 - 31 (1 bit)
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