\n
address_offset : 0x0 Bytes (0x0)
size : 0x220 byte (0x0)
mem_usage : registers
protection : not protected
APB_CTRL_SYSCLK_CONF
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE_DIV_CNT :
bits : 0 - 9 (10 bit)
CLK_320M_EN :
bits : 10 - 10 (1 bit)
CLK_EN :
bits : 11 - 11 (1 bit)
RST_TICK_CNT :
bits : 12 - 12 (1 bit)
QUICK_CLK_CHNG :
bits : 13 - 13 (1 bit)
APB_CTRL_APB_SARADC_CTRL
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SARADC_START_FORCE :
bits : 0 - 0 (1 bit)
SARADC_START :
bits : 1 - 1 (1 bit)
SARADC_SAR2_MUX :
bits : 2 - 2 (1 bit)
SARADC_WORK_MODE :
bits : 3 - 4 (2 bit)
SARADC_SAR_SEL :
bits : 5 - 5 (1 bit)
SARADC_SAR_CLK_GATED :
bits : 6 - 6 (1 bit)
SARADC_SAR_CLK_DIV :
bits : 7 - 14 (8 bit)
SARADC_SAR1_PATT_LEN :
bits : 15 - 18 (4 bit)
SARADC_SAR2_PATT_LEN :
bits : 19 - 22 (4 bit)
SARADC_SAR1_PATT_P_CLEAR :
bits : 23 - 23 (1 bit)
SARADC_SAR2_PATT_P_CLEAR :
bits : 24 - 24 (1 bit)
SARADC_DATA_SAR_SEL :
bits : 25 - 25 (1 bit)
SARADC_DATA_TO_I2S :
bits : 26 - 26 (1 bit)
APB_CTRL_APB_SARADC_CTRL2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SARADC_MEAS_NUM_LIMIT :
bits : 0 - 0 (1 bit)
SARADC_MAX_MEAS_NUM :
bits : 1 - 8 (8 bit)
SARADC_SAR1_INV :
bits : 9 - 9 (1 bit)
SARADC_SAR2_INV :
bits : 10 - 10 (1 bit)
APB_CTRL_APB_SARADC_FSM
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SARADC_RSTB_WAIT :
bits : 0 - 7 (8 bit)
SARADC_STANDBY_WAIT :
bits : 8 - 15 (8 bit)
SARADC_START_WAIT :
bits : 16 - 23 (8 bit)
SARADC_SAMPLE_CYCLE :
bits : 24 - 31 (8 bit)
APB_CTRL_APB_SARADC_SAR1_PATT_TAB1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SARADC_SAR1_PATT_TAB1 :
bits : 0 - 31 (32 bit)
APB_CTRL_APB_SARADC_SAR1_PATT_TAB2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SARADC_SAR1_PATT_TAB2 :
bits : 0 - 31 (32 bit)
APB_CTRL_APB_SARADC_SAR1_PATT_TAB3
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SARADC_SAR1_PATT_TAB3 :
bits : 0 - 31 (32 bit)
APB_CTRL_APB_SARADC_SAR1_PATT_TAB4
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SARADC_SAR1_PATT_TAB4 :
bits : 0 - 31 (32 bit)
APB_CTRL_APB_SARADC_SAR2_PATT_TAB1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SARADC_SAR2_PATT_TAB1 :
bits : 0 - 31 (32 bit)
APB_CTRL_APB_SARADC_SAR2_PATT_TAB2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SARADC_SAR2_PATT_TAB2 :
bits : 0 - 31 (32 bit)
APB_CTRL_APB_SARADC_SAR2_PATT_TAB3
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SARADC_SAR2_PATT_TAB3 :
bits : 0 - 31 (32 bit)
APB_CTRL_APB_SARADC_SAR2_PATT_TAB4
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SARADC_SAR2_PATT_TAB4 :
bits : 0 - 31 (32 bit)
APB_CTRL_APLL_TICK_CONF
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APLL_TICK_NUM :
bits : 0 - 7 (8 bit)
APB_CTRL_XTAL_TICK_CONF
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_TICK_NUM :
bits : 0 - 7 (8 bit)
APB_CTRL_DATE
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATE :
bits : 0 - 31 (32 bit)
APB_CTRL_PLL_TICK_CONF
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_TICK_NUM :
bits : 0 - 7 (8 bit)
APB_CTRL_CK8M_TICK_CONF
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CK8M_TICK_NUM :
bits : 0 - 7 (8 bit)
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