Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR0
PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT0
PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR1
PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT1
TR_GR[1]-TR_GR[0]-TR_OUT_CTL[127]
TR_GR[2]-TR_GR[1]-TR_GR[0]-TR_OUT_CTL[127]
TR_GR[3]-TR_GR[2]-TR_GR[1]-TR_GR[0]-TR_OUT_CTL[127]
TR_GR[4]-TR_GR[3]-TR_GR[2]-TR_GR[1]-TR_GR[0]-TR_OUT_CTL[127]
TR_GR[5]-TR_GR[4]-TR_GR[3]-TR_GR[2]-TR_GR[1]-TR_GR[0]-TR_OUT_CTL[127]
TR_GR[6]-TR_GR[5]-TR_GR[4]-TR_GR[3]-TR_GR[2]-TR_GR[1]-TR_GR[0]-TR_OUT_CTL[127]
TR_GR[7]-TR_GR[6]-TR_GR[5]-TR_GR[4]-TR_GR[3]-TR_GR[2]-TR_GR[1]-TR_GR[0]-TR_OUT_CTL[127]
TR_GR[8]-TR_GR[7]-TR_GR[6]-TR_GR[5]-TR_GR[4]-TR_GR[3]-TR_GR[2]-TR_GR[1]-TR_GR[0]-TR_OUT_CTL[127]
PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR0
PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT0
PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR1
PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT1
PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR0
PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT0
PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR1
PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT1
GR[3]-GR[2]-GR[1]-GR[0]-CLOCK_CTL
PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR0
PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT0
PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR1
PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT1
PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR0
PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT0
PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR1
PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT1
GR[3]-GR[2]-GR[1]-GR[0]-SL_CTL
GR[3]-GR[2]-GR[1]-GR[0]-TIMEOUT_CTL
PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR0
PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT0
PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR1
PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT1
PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR0
PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT0
PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR1
PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT1
PPU_PR[7]-PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR0
PPU_PR[7]-PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT0
PPU_PR[7]-PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR1
PPU_PR[7]-PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT1
PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR0
PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT0
PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR1
PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT1
PPU_PR[8]-PPU_PR[7]-PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR0
PPU_PR[8]-PPU_PR[7]-PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT0
PPU_PR[8]-PPU_PR[7]-PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR1
PPU_PR[8]-PPU_PR[7]-PPU_PR[6]-PPU_PR[5]-PPU_PR[4]-PPU_PR[3]-PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT1
GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-CLOCK_CTL
PPU_GR[7]-PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR0
PPU_GR[7]-PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT0
PPU_GR[7]-PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR1
PPU_GR[7]-PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT1
GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-SL_CTL
GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-TIMEOUT_CTL
PPU_GR[8]-PPU_GR[7]-PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR0
PPU_GR[8]-PPU_GR[7]-PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT0
PPU_GR[8]-PPU_GR[7]-PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR1
PPU_GR[8]-PPU_GR[7]-PPU_GR[6]-PPU_GR[5]-PPU_GR[4]-PPU_GR[3]-PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT1
GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-CLOCK_CTL
GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-SL_CTL
GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-TIMEOUT_CTL
GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-CLOCK_CTL
GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-SL_CTL
GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-TIMEOUT_CTL
GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-CLOCK_CTL
GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-SL_CTL
GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-TIMEOUT_CTL
GR[8]-GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-CLOCK_CTL
GR[8]-GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-SL_CTL
GR[8]-GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-TIMEOUT_CTL
GR[9]-GR[8]-GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-CLOCK_CTL
GR[9]-GR[8]-GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-SL_CTL
GR[9]-GR[8]-GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-TIMEOUT_CTL
PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR0
PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT0
PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ADDR1
PPU_PR[2]-PPU_PR[1]-PPU_PR[0]-ATT1
GR[10]-GR[9]-GR[8]-GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-CLOCK_CTL
GR[10]-GR[9]-GR[8]-GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-SL_CTL
GR[10]-GR[9]-GR[8]-GR[7]-GR[6]-GR[5]-GR[4]-GR[3]-GR[2]-GR[1]-GR[0]-TIMEOUT_CTL
PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR0
PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT0
PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ADDR1
PPU_GR[2]-PPU_GR[1]-PPU_GR[0]-ATT1
Clock control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8_DIV : Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger command register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies the activated trigger when ACTIVATE is '1'. OUT_SEL specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (ACTIVATE is '1'), SW should not modify this register field. If the specified trigger is not present, the trigger activation has no effect.
bits : 0 - 7 (8 bit)
access : read-write
GROUP_SEL : Specifies the trigger group.
bits : 8 - 19 (12 bit)
access : read-write
COUNT : Amount of 'clk_peri' cycles a specific trigger is activated. During activation (ACTIVATE is '1'), HW decrements this field to '0' using a cycle counter. During activation, SW should not modify this register field. A value of 255 is a special case: HW does NOT decrement this field to '0' and trigger activation is under direct control of ACTIVATE when ACTIVATE is '1' the trigger is activated and when ACTIVATE is '0' the trigger is deactivated.
bits : 16 - 39 (24 bit)
access : read-write
OUT_SEL : Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. '0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. '1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer.
bits : 30 - 60 (31 bit)
access : read-write
ACTIVATE : SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SEL and OUT_SEL for COUNT cycles. HW sets this field to '0' when the cycle counter is decremented to '0'. Note: a COUNT value of 255 is a special case and trigger activation is under direct control of the ACTIVATE field (the counter is not decremented).
bits : 31 - 62 (32 bit)
access : read-write
Trigger control register
address_offset : 0x10054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1009C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x101728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1017C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x10180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x10184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x101A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x101A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Trigger control register
address_offset : 0x103918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0x105B0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x10744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x107D04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x108B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x109F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x10AE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x10B48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x10BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x10C100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0x10E500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x10FC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x110B00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x11314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x113300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x11458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x115D00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x11750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x1179C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x11840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x118900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0x11B700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x11D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x11DCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x11E700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x12070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x120C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x121900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x122B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x123F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x124D00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x12744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x127E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x128300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1294C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x12BB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x12E14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x12F500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x13050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x130C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x131D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x13258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x133100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1397C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x13A40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x13A68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x13CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x13CCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x14090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x14180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 0 (slave structure)
address_offset : 0x14184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address.
bits : 0 - 0 (1 bit)
access : read-write
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address.
bits : 3 - 6 (4 bit)
access : read-write
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x141A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x141A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x14280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x14284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x142A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x142A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x142FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x143C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x144E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x14744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x14914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x14B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x14D4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x15058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x151C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x15430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x1557C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x156D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x15BCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x15C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x15CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x16068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x160B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x161E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x16574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x166C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x16744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x169FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x16E1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x16E58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1714C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x172C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x17394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x176C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x17ACC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x17BD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x17D30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x17E40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x17F78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8_DIV : Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x1800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x180DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x183C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x183C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x183E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x183E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x18668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x186D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x18744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1882C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x189C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x19074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x190E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x190FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x19280 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 0 (slave structure)
address_offset : 0x19284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address.
bits : 0 - 0 (1 bit)
access : read-write
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address.
bits : 3 - 6 (4 bit)
access : read-write
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x192A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x192A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Clock control register
address_offset : 0x193C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1954C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x199A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x19A1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x19B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Slave control
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED_0 : Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
bits : 0 - 0 (1 bit)
access : read-only
ENABLED_1 : Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 1 - 2 (2 bit)
access : read-write
ENABLED_2 : Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 2 - 4 (3 bit)
access : read-write
ENABLED_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
ENABLED_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
ENABLED_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
ENABLED_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
ENABLED_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
ENABLED_8 : N/A
bits : 8 - 16 (9 bit)
access : read-write
ENABLED_9 : N/A
bits : 9 - 18 (10 bit)
access : read-write
ENABLED_10 : N/A
bits : 10 - 20 (11 bit)
access : read-write
ENABLED_11 : N/A
bits : 11 - 22 (12 bit)
access : read-write
ENABLED_12 : N/A
bits : 12 - 24 (13 bit)
access : read-write
ENABLED_13 : N/A
bits : 13 - 26 (14 bit)
access : read-write
ENABLED_14 : N/A
bits : 14 - 28 (15 bit)
access : read-write
ENABLED_15 : N/A
bits : 15 - 30 (16 bit)
access : read-write
Clock control register
address_offset : 0x1A040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1A0D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x1A108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1A260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1A3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Timeout control
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
bits : 0 - 15 (16 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1A630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1AB24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1AC68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x1ACC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1AD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1B04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1B0D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1B3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1B72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1B7FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x1B94C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1BB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1BCB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1C0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x1C138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1C394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x1C540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x1C544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x1C560 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x1C564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1C588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x1C5D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1C61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1CAA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1CE5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1CF30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1D0C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x1D268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1D460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1D734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1DAD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1DB78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1DE24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x1DEFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1E010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1E04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x1E16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x1E3C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 0 (slave structure)
address_offset : 0x1E3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address.
bits : 0 - 0 (1 bit)
access : read-write
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address.
bits : 3 - 6 (4 bit)
access : read-write
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x1E3E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x1E3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1E62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1E674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1E7EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1E8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x1EB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1F0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1F1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1F1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1F21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x1F830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x1FABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x1FB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x1FBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x1FDC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Slave control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED_0 : Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
bits : 0 - 0 (1 bit)
access : read-only
ENABLED_1 : Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 1 - 2 (2 bit)
access : read-write
ENABLED_2 : Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 2 - 4 (3 bit)
access : read-write
ENABLED_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
ENABLED_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
ENABLED_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
ENABLED_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
ENABLED_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
ENABLED_8 : N/A
bits : 8 - 16 (9 bit)
access : read-write
ENABLED_9 : N/A
bits : 9 - 18 (10 bit)
access : read-write
ENABLED_10 : N/A
bits : 10 - 20 (11 bit)
access : read-write
ENABLED_11 : N/A
bits : 11 - 22 (12 bit)
access : read-write
ENABLED_12 : N/A
bits : 12 - 24 (13 bit)
access : read-write
ENABLED_13 : N/A
bits : 13 - 26 (14 bit)
access : read-write
ENABLED_14 : N/A
bits : 14 - 28 (15 bit)
access : read-write
ENABLED_15 : N/A
bits : 15 - 30 (16 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x200C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x201A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x203A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x204D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x2055C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x20660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x20700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x20704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x20720 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x20724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x20978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x20C98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x20F34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x2104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x21124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x21174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x2152C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x2158C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x21910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x21BEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x21E1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x21E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x220E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x221E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x222F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x226B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x22780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x22AC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x22CA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x22CD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x23188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x23540 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 0 (slave structure)
address_offset : 0x23544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address.
bits : 0 - 0 (1 bit)
access : read-write
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address.
bits : 3 - 6 (4 bit)
access : read-write
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x23560 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x23564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x236BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x23778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x23860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x23C5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Timeout control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
bits : 0 - 15 (16 bit)
access : read-write
Clock control register
address_offset : 0x2404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x240A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x240C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x24220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x24424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x2442C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x24734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x24900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x24904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x24920 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x24924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x24A98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x24FEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x250E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x25210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x2548C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x25BB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x25CF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x25DA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x25E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x26264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x26788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x267D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x26880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x26A60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x272BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x2735C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x27724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x27DA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x27F34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8_DIV : Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x280C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x2818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x282AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x283EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x28700 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 0 (slave structure)
address_offset : 0x28704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address.
bits : 0 - 0 (1 bit)
access : read-write
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address.
bits : 3 - 6 (4 bit)
access : read-write
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x28720 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x28724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x28898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x28B10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x28B40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x28B44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x28B60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x28B64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Clock control register
address_offset : 0x290B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x2938C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x296F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x29D88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x29E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Slave control
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED_0 : Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
bits : 0 - 0 (1 bit)
access : read-only
ENABLED_1 : Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 1 - 2 (2 bit)
access : read-write
ENABLED_2 : Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 2 - 4 (3 bit)
access : read-write
ENABLED_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
ENABLED_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
ENABLED_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
ENABLED_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
ENABLED_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
ENABLED_8 : N/A
bits : 8 - 16 (9 bit)
access : read-write
ENABLED_9 : N/A
bits : 9 - 18 (10 bit)
access : read-write
ENABLED_10 : N/A
bits : 10 - 20 (11 bit)
access : read-write
ENABLED_11 : N/A
bits : 11 - 22 (12 bit)
access : read-write
ENABLED_12 : N/A
bits : 12 - 24 (13 bit)
access : read-write
ENABLED_13 : N/A
bits : 13 - 26 (14 bit)
access : read-write
ENABLED_14 : N/A
bits : 14 - 28 (15 bit)
access : read-write
ENABLED_15 : N/A
bits : 15 - 30 (16 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x2A2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x2A2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Timeout control
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
bits : 0 - 15 (16 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x2A980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x2AA5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x2AEBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x2B734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x2BAA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x2C0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x2C348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x2C410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x2C698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x2CDC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x2CDC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x2CDE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x2CDE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Clock control register
address_offset : 0x2D0F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x2D18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x2D28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x2D900 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 0 (slave structure)
address_offset : 0x2D904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address.
bits : 0 - 0 (1 bit)
access : read-write
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address.
bits : 3 - 6 (4 bit)
access : read-write
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x2D920 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x2D924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Clock control register
address_offset : 0x2DDD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x2DE84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x2E39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x2EABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x2F7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x300C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x3028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x303F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x30498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x31080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x31084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x310A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x310A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Clock control register
address_offset : 0x3118C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x31E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x3218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x32450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x32B40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 0 (slave structure)
address_offset : 0x32B44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address.
bits : 0 - 0 (1 bit)
access : read-write
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address.
bits : 3 - 6 (4 bit)
access : read-write
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x32B60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x32B64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Clock control register
address_offset : 0x32B80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x33880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x344B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x34584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x3528C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x35380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x35384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x353A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x353A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Clock control register
address_offset : 0x35F98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x3628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x36514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x36CA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x3718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x379BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x37DC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 0 (slave structure)
address_offset : 0x37DC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address.
bits : 0 - 0 (1 bit)
access : read-write
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address.
bits : 3 - 6 (4 bit)
access : read-write
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x37DE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x37DE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x383C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x3857C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x386D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x393F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x396C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x396C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x396E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x396E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Clock control register
address_offset : 0x3A110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x3A5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x3AE34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x3BB5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8_DIV : Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x3C18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x3C28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x3C658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x3C888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x3D5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x3DA40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x3DA44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x3DA60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x3DA64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Slave control
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED_0 : Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
bits : 0 - 0 (1 bit)
access : read-only
ENABLED_1 : Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 1 - 2 (2 bit)
access : read-write
ENABLED_2 : Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 2 - 4 (3 bit)
access : read-write
ENABLED_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
ENABLED_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
ENABLED_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
ENABLED_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
ENABLED_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
ENABLED_8 : N/A
bits : 8 - 16 (9 bit)
access : read-write
ENABLED_9 : N/A
bits : 9 - 18 (10 bit)
access : read-write
ENABLED_10 : N/A
bits : 10 - 20 (11 bit)
access : read-write
ENABLED_11 : N/A
bits : 11 - 22 (12 bit)
access : read-write
ENABLED_12 : N/A
bits : 12 - 24 (13 bit)
access : read-write
ENABLED_13 : N/A
bits : 13 - 26 (14 bit)
access : read-write
ENABLED_14 : N/A
bits : 14 - 28 (15 bit)
access : read-write
ENABLED_15 : N/A
bits : 15 - 30 (16 bit)
access : read-write
Clock control register
address_offset : 0x3E2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Timeout control
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
bits : 0 - 15 (16 bit)
access : read-write
Trigger control register
address_offset : 0x3E6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x3F024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x3F3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x3FD60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8_DIV : Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider command register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : (TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
PA_DIV_SEL : (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '63' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference.
bits : 8 - 21 (14 bit)
access : read-write
PA_TYPE_SEL : Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 14 - 29 (16 bit)
access : read-write
DISABLE : Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately.
bits : 30 - 60 (31 bit)
access : read-write
ENABLE : Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process.
bits : 31 - 62 (32 bit)
access : read-write
Trigger control register
address_offset : 0x4000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x4000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x4004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x4020 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x4024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x4054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x40744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x40AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x417E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x41E00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x41E04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x41E20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x41E24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x4228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x4252C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x427C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x43278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x43FC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x44840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x44D1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x45A74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x463C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x467D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x468C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x47530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x4828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x48294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x4854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x4870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x4894C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x48FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x49D68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x4A9D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x4AAD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x4B84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x4C5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x4CA68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x4D340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x4D3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x4E0C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x4EAFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x4EE44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x4FBCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x5000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 0 (slave structure)
address_offset : 0x5004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address.
bits : 0 - 0 (1 bit)
access : read-write
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address.
bits : 3 - 6 (4 bit)
access : read-write
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x5020 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x5024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x5054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x5090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x50958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x50B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x516E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x5170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x5247C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x52C30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x53214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x53FB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8_DIV : Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0x543C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x54CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x54D50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x55AF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Slave control
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED_0 : Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
bits : 0 - 0 (1 bit)
access : read-only
ENABLED_1 : Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 1 - 2 (2 bit)
access : read-write
ENABLED_2 : Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 2 - 4 (3 bit)
access : read-write
ENABLED_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
ENABLED_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
ENABLED_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
ENABLED_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
ENABLED_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
ENABLED_8 : N/A
bits : 8 - 16 (9 bit)
access : read-write
ENABLED_9 : N/A
bits : 9 - 18 (10 bit)
access : read-write
ENABLED_10 : N/A
bits : 10 - 20 (11 bit)
access : read-write
ENABLED_11 : N/A
bits : 11 - 22 (12 bit)
access : read-write
ENABLED_12 : N/A
bits : 12 - 24 (13 bit)
access : read-write
ENABLED_13 : N/A
bits : 13 - 26 (14 bit)
access : read-write
ENABLED_14 : N/A
bits : 14 - 28 (15 bit)
access : read-write
ENABLED_15 : N/A
bits : 15 - 30 (16 bit)
access : read-write
Timeout control
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
bits : 0 - 15 (16 bit)
access : read-write
Clock control register
address_offset : 0x5689C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x56D74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x57648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x583F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x5854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x58B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x58E1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x591AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x59F64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x5A70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x5A90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control register
address_offset : 0x5AD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x5AEC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x5BAE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x5C8A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x5CF78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x5D66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x5E438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x5F02C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x5F208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x5FFDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Slave control
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED_0 : Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
bits : 0 - 0 (1 bit)
access : read-only
ENABLED_1 : Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 1 - 2 (2 bit)
access : read-write
ENABLED_2 : Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 2 - 4 (3 bit)
access : read-write
ENABLED_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
ENABLED_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
ENABLED_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
ENABLED_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
ENABLED_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
ENABLED_8 : N/A
bits : 8 - 16 (9 bit)
access : read-write
ENABLED_9 : N/A
bits : 9 - 18 (10 bit)
access : read-write
ENABLED_10 : N/A
bits : 10 - 20 (11 bit)
access : read-write
ENABLED_11 : N/A
bits : 11 - 22 (12 bit)
access : read-write
ENABLED_12 : N/A
bits : 12 - 24 (13 bit)
access : read-write
ENABLED_13 : N/A
bits : 13 - 26 (14 bit)
access : read-write
ENABLED_14 : N/A
bits : 14 - 28 (15 bit)
access : read-write
ENABLED_15 : N/A
bits : 15 - 30 (16 bit)
access : read-write
Trigger control register
address_offset : 0x6004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x6054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x60DB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x60DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x610E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x61B90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x62970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x631A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x6370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Clock control register
address_offset : 0x63754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x63B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Timeout control
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
bits : 0 - 15 (16 bit)
access : read-write
Clock control register
address_offset : 0x6453C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x6490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x65260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x65328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x66118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x66F0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x67324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x67D04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Clock control register
address_offset : 0x68B00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x6908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x693EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0x6B4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x6C70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x6CDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x6D588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x6E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x6EB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x6F65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8_DIV : Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x7138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x71734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Slave control
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED_0 : Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
bits : 0 - 0 (1 bit)
access : read-only
ENABLED_1 : Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 1 - 2 (2 bit)
access : read-write
ENABLED_2 : Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 2 - 4 (3 bit)
access : read-write
ENABLED_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
ENABLED_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
ENABLED_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
ENABLED_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
ENABLED_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
ENABLED_8 : N/A
bits : 8 - 16 (9 bit)
access : read-write
ENABLED_9 : N/A
bits : 9 - 18 (10 bit)
access : read-write
ENABLED_10 : N/A
bits : 10 - 20 (11 bit)
access : read-write
ENABLED_11 : N/A
bits : 11 - 22 (12 bit)
access : read-write
ENABLED_12 : N/A
bits : 12 - 24 (13 bit)
access : read-write
ENABLED_13 : N/A
bits : 13 - 26 (14 bit)
access : read-write
ENABLED_14 : N/A
bits : 14 - 28 (15 bit)
access : read-write
ENABLED_15 : N/A
bits : 15 - 30 (16 bit)
access : read-write
Timeout control
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
bits : 0 - 15 (16 bit)
access : read-write
Trigger control register
address_offset : 0x73810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0x758F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x7608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x779D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x7890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x78DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x796C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x79ABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x79B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x7BBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0x7DC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x7F38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x7FD8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0x800C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0x8040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0x8044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0x8060 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0x8064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x81A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x81E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x8308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x83F80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x84B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x84DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x86080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0x88184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x886C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x89E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x8A28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0x8C398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x8D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x8E4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8_DIV : Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x9008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x905BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x90DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x91A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Slave control
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED_0 : Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
bits : 0 - 0 (1 bit)
access : read-only
ENABLED_1 : Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 1 - 2 (2 bit)
access : read-write
ENABLED_2 : Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 2 - 4 (3 bit)
access : read-write
ENABLED_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
ENABLED_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
ENABLED_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
ENABLED_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
ENABLED_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
ENABLED_8 : N/A
bits : 8 - 16 (9 bit)
access : read-write
ENABLED_9 : N/A
bits : 9 - 18 (10 bit)
access : read-write
ENABLED_10 : N/A
bits : 10 - 20 (11 bit)
access : read-write
ENABLED_11 : N/A
bits : 11 - 22 (12 bit)
access : read-write
ENABLED_12 : N/A
bits : 12 - 24 (13 bit)
access : read-write
ENABLED_13 : N/A
bits : 13 - 26 (14 bit)
access : read-write
ENABLED_14 : N/A
bits : 14 - 28 (15 bit)
access : read-write
ENABLED_15 : N/A
bits : 15 - 30 (16 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x9220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Timeout control
address_offset : 0x924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
bits : 0 - 15 (16 bit)
access : read-write
Trigger control register
address_offset : 0x926D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0x947F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0x96910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0x976C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0x98A34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0x9A64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0x9AB5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0x9AE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0x9B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0x9CC88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0x9D08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0x9EDB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xA018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0xA040 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 0 (slave structure)
address_offset : 0xA044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address.
bits : 0 - 0 (1 bit)
access : read-write
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address.
bits : 3 - 6 (4 bit)
access : read-write
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0xA060 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0xA064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Trigger control register
address_offset : 0xA0EEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0xA1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xA2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0xA3024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0xA420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0xA5160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0xA66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0xA72A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0xA938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0xA93E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xAAF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0xAB52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0xABE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0xAD64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0xAD678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xAF7C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xB191C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0xB1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xB348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0xB3A74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8_DIV : Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0xB56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0xB5BD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Slave control
address_offset : 0xB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED_0 : Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
bits : 0 - 0 (1 bit)
access : read-only
ENABLED_1 : Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 1 - 2 (2 bit)
access : read-write
ENABLED_2 : Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 2 - 4 (3 bit)
access : read-write
ENABLED_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
ENABLED_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
ENABLED_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
ENABLED_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
ENABLED_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
ENABLED_8 : N/A
bits : 8 - 16 (9 bit)
access : read-write
ENABLED_9 : N/A
bits : 9 - 18 (10 bit)
access : read-write
ENABLED_10 : N/A
bits : 10 - 20 (11 bit)
access : read-write
ENABLED_11 : N/A
bits : 11 - 22 (12 bit)
access : read-write
ENABLED_12 : N/A
bits : 12 - 24 (13 bit)
access : read-write
ENABLED_13 : N/A
bits : 13 - 26 (14 bit)
access : read-write
ENABLED_14 : N/A
bits : 14 - 28 (15 bit)
access : read-write
ENABLED_15 : N/A
bits : 15 - 30 (16 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0xB620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Timeout control
address_offset : 0xB64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
bits : 0 - 15 (16 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0xB6AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0xB7D30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xB9E94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xBB9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0xBBFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0xBCE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0xBE168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0xBFF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8_DIV : Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0xC028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xC02D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0xC064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0xC0C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
PPU region attributes 0 (slave structure)
address_offset : 0xC0C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0xC0E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0xC0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Clock control register
address_offset : 0xC1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0xC244C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xC3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0xC45C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xC6740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0xC820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0xC88C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0xC948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0xCAA44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0xCAAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xCC50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0xCCBCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0xCDE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0xCED58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xD0EE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0xD29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0xD307C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0xD364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xD4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0xD4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0xD5214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xD73B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xD9550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0xDA20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0xDB6F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0xDBF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Clock control
address_offset : 0xDC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT8_DIV : Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xDD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0xDD89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Slave control
address_offset : 0xDE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED_0 : Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
bits : 0 - 0 (1 bit)
access : read-only
ENABLED_1 : Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 1 - 2 (2 bit)
access : read-write
ENABLED_2 : Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 2 - 4 (3 bit)
access : read-write
ENABLED_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
ENABLED_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
ENABLED_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
ENABLED_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
ENABLED_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
ENABLED_8 : N/A
bits : 8 - 16 (9 bit)
access : read-write
ENABLED_9 : N/A
bits : 9 - 18 (10 bit)
access : read-write
ENABLED_10 : N/A
bits : 10 - 20 (11 bit)
access : read-write
ENABLED_11 : N/A
bits : 11 - 22 (12 bit)
access : read-write
ENABLED_12 : N/A
bits : 12 - 24 (13 bit)
access : read-write
ENABLED_13 : N/A
bits : 13 - 26 (14 bit)
access : read-write
ENABLED_14 : N/A
bits : 14 - 28 (15 bit)
access : read-write
ENABLED_15 : N/A
bits : 15 - 30 (16 bit)
access : read-write
Timeout control
address_offset : 0xDE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
bits : 0 - 15 (16 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0xDEAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0xDF48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0xDFA48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Slave control
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED_0 : Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
bits : 0 - 0 (1 bit)
access : read-only
ENABLED_1 : Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 1 - 2 (2 bit)
access : read-write
ENABLED_2 : Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
bits : 2 - 4 (3 bit)
access : read-write
ENABLED_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
ENABLED_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
ENABLED_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
ENABLED_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
ENABLED_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
ENABLED_8 : N/A
bits : 8 - 16 (9 bit)
access : read-write
ENABLED_9 : N/A
bits : 9 - 18 (10 bit)
access : read-write
ENABLED_10 : N/A
bits : 10 - 20 (11 bit)
access : read-write
ENABLED_11 : N/A
bits : 11 - 22 (12 bit)
access : read-write
ENABLED_12 : N/A
bits : 12 - 24 (13 bit)
access : read-write
ENABLED_13 : N/A
bits : 13 - 26 (14 bit)
access : read-write
ENABLED_14 : N/A
bits : 14 - 28 (15 bit)
access : read-write
ENABLED_15 : N/A
bits : 15 - 30 (16 bit)
access : read-write
Trigger control register
address_offset : 0xE03C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xE1BF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xE3DAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Timeout control
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
bits : 0 - 15 (16 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0xE550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xE57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0xE5F64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0xE664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0xE8120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0xE99C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0xE9F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Trigger control register
address_offset : 0xEA2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xEC4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xEDE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0xEE66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0xEEB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0xF0838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
PPU region address 0 (slave structure)
address_offset : 0xF0C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 0 (slave structure)
address_offset : 0xF0C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address.
bits : 0 - 0 (1 bit)
access : read-write
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address.
bits : 3 - 6 (4 bit)
access : read-write
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
PPU region address 1 (master structure)
address_offset : 0xF0E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
PPU region attributes 1 (master structure)
address_offset : 0xF0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : See corresponding field for PPU structure with programmable address.
bits : 1 - 2 (2 bit)
access : read-write
UX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : See corresponding field for PPU structure with programmable address. Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : See corresponding field for PPU structure with programmable address.
bits : 4 - 8 (5 bit)
access : read-write
PX : See corresponding field for PPU structure with programmable address. Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : See corresponding field for PPU structure with programmable address.
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : See corresponding field for PPU structure with programmable address.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : See corresponding field for PPU structure with programmable address.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : See corresponding field for PPU structure with programmable address. '7': 256 B region
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : See corresponding field for PPU structure with programmable address.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See corresponding field for PPU structure with programmable address.
bits : 31 - 62 (32 bit)
access : read-write
Trigger control register
address_offset : 0xF2A08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Clock control register
address_offset : 0xF2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0xF3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0xF4BDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 24.5 divider)
address_offset : 0xF548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT24_DIV : Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 39 (32 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xF658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Trigger control register
address_offset : 0xF6DB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.0 divider)
address_offset : 0xF814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Trigger control register
address_offset : 0xF8F90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xFB170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Trigger control register
address_offset : 0xFD354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
Divider control register (for 16.5 divider)
address_offset : 0xFE50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
FRAC5_DIV : Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 3 - 10 (8 bit)
access : read-write
INT16_DIV : Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 31 (24 bit)
access : read-write
Divider control register (for 8.0 divider)
address_offset : 0xFECC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
bits : 0 - 0 (1 bit)
access : read-only
INT8_DIV : Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
Clock control register
address_offset : 0xFEF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SEL : Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
bits : 0 - 5 (6 bit)
access : read-write
TYPE_SEL : Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
bits : 6 - 13 (8 bit)
access : read-write
Trigger control register
address_offset : 0xFF53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_SEL : Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
bits : 0 - 7 (8 bit)
access : read-write
TR_INV : Specifies if the output trigger is inverted.
bits : 8 - 16 (9 bit)
access : read-write
TR_EDGE : Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
bits : 9 - 18 (10 bit)
access : read-write
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