\n
address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
CM0+ control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLV_STALL : Processor debug access control: '0': Access. '1': Stall access. This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses.
bits : 0 - 0 (1 bit)
access : read-write
ENABLED : Processor enable: '0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. '1': Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details).
bits : 1 - 2 (2 bit)
access : read-write
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
CM0+ clock control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_INT_DIV : Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
PERI_INT_DIV : Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'.
bits : 24 - 55 (32 bit)
access : read-write
RAM 0 control 0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_WS : Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 0 - 1 (2 bit)
access : read-write
FAST_WS : Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 8 - 17 (10 bit)
access : read-write
RAM 0 power control
address_offset : 0x1148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x12B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x142C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x15A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
RAM 1 control 0
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_WS : Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 0 - 1 (2 bit)
access : read-write
FAST_WS : Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 8 - 17 (10 bit)
access : read-write
RAM1 power control
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for SRAM1
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
RAM 2 control 0
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_WS : Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 0 - 1 (2 bit)
access : read-write
FAST_WS : Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 8 - 17 (10 bit)
access : read-write
RAM2 power control
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for SRAM2
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
Power up delay used for all SRAM power domains
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UP : Number clock cycles delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write
ROM control
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_WS : Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different 'clk_hf' frequencies.
bits : 0 - 1 (2 bit)
access : read-write
FAST_WS : Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 8 - 17 (10 bit)
access : read-write
UDB power control
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for UDBs
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RESET
See CM4_PWR_CTL
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
UDB power control
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UP : Number clock cycles delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write
CM0+ interrupt control 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX0_SEL : System interrupt select for CPU interrupt source 0. If the field value is 240, no system interrupt is connected and the CPU interrupt source is always '0'/de-activated.
bits : 0 - 7 (8 bit)
access : read-write
MUX1_SEL : System interrupt select for CPU interrupt source 1.
bits : 8 - 23 (16 bit)
access : read-write
MUX2_SEL : System interrupt select for CPU interrupt source 2.
bits : 16 - 39 (24 bit)
access : read-write
MUX3_SEL : System interrupt select for CPU interrupt source 3.
bits : 24 - 55 (32 bit)
access : read-write
Debug port status
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWJ_CONNECTED : Specifies if the SWJ debug port is connected; i.e. debug host interface is active: '0': Not connected/not active. '1': Connected/active.
bits : 0 - 0 (1 bit)
access : read-only
SWJ_DEBUG_EN : Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: '0': Disabled. '1': Enabled.
bits : 1 - 2 (2 bit)
access : read-only
SWJ_JTAG_SEL : Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). '0': SWD selected. '1': JTAG selected.
bits : 2 - 4 (3 bit)
access : read-only
Buffer control
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRITE_BUFF : Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered, independent of the transfer's bufferable attribute. '1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write.
bits : 0 - 0 (1 bit)
access : read-write
DDFT control
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDFT_OUT0_SEL : Select signal for CPUSS DDFT[0] 0: clk_r of the Main flash (which is clk_hf for SONOS Flash) 1: Flash data output bit '0' (r_q[0]) 2: Flash data output bit '32' (r_q[32]) 3: Flash data output bit '64' (r_q[64]) 4: Flash data output bit '127' (r_q[127]) 5: bist_fm_enabled 6: bist_fail 7: cm0_sleeping 8: cm0_sleepdeep 9: cm0_sleep_hold_ack_n 10: cm4_sleeping 11: cm4_sleepdeep 12: cm4_sleep_hold_ack_n 13: cm4_power 14: cm4_act_retain_n 15: cm4_act_isolate_n 16: cm4_enabled 17: cm4_reset_n 18: cm4_pwr_done 19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) 20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0)
bits : 0 - 4 (5 bit)
access : read-write
DDFT_OUT1_SEL : Select signal for CPUSS DDFT[0] 0: clk_r of the Main flash (which is clk_hf for SONOS Flash) 1: Flash data output bit '0' (r_q[0]) 2: Flash data output bit '32' (r_q[32]) 3: Flash data output bit '64' (r_q[64]) 4: Flash data output bit '127' (r_q[127]) 5: bist_fm_enabled 6: bist_fail 7: cm0_sleeping 8: cm0_sleepdeep 9: cm0_sleep_hold_ack_n 10: cm4_sleeping 11: cm4_sleepdeep 12: cm4_sleep_hold_ack_n 13: cm4_power 14: cm4_act_retain_n 15: cm4_act_isolate_n 16: cm4_enabled 17: cm4_reset_n 18: cm4_pwr_done 19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) 20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0)
bits : 8 - 20 (13 bit)
access : read-write
CM0+ interrupt control 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX0_SEL : System interrupt select for CPU interrupt source 4.
bits : 0 - 7 (8 bit)
access : read-write
MUX1_SEL : System interrupt select for CPU interrupt source 5.
bits : 8 - 23 (16 bit)
access : read-write
MUX2_SEL : System interrupt select for CPU interrupt source 6.
bits : 16 - 39 (24 bit)
access : read-write
MUX3_SEL : System interrupt select for CPU interrupt source 7.
bits : 24 - 55 (32 bit)
access : read-write
SysTick timer control
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TENMS : Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327.
bits : 0 - 23 (24 bit)
access : read-write
CLOCK_SOURCE : Specifies an external clock source: '0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). '1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. '3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source.
bits : 24 - 49 (26 bit)
access : read-write
SKEW : Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: '0': Precise. '1': Imprecise.
bits : 30 - 60 (31 bit)
access : read-write
NOREF : Specifies if an external clock source is provided: '0': An external clock source is provided. '1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ interrupt control 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX0_SEL : System interrupt select for CPU interrupt source 8.
bits : 0 - 7 (8 bit)
access : read-write
MUX1_SEL : System interrupt select for CPU interrupt source 9.
bits : 8 - 23 (16 bit)
access : read-write
MUX2_SEL : System interrupt select for CPU interrupt source 10.
bits : 16 - 39 (24 bit)
access : read-write
MUX3_SEL : System interrupt select for CPU interrupt source 11.
bits : 24 - 55 (32 bit)
access : read-write
RAM 0 power control
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
CM0+ vector table base
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR24 : Address of CM0+ vector table. Note: the CM0+ vector table is at an address that is a 256 B multiple.
bits : 8 - 39 (32 bit)
access : read-write
CM0+ interrupt control 3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX0_SEL : System interrupt select for CPU interrupt source 12.
bits : 0 - 7 (8 bit)
access : read-write
MUX1_SEL : System interrupt select for CPU interrupt source 13.
bits : 8 - 23 (16 bit)
access : read-write
MUX2_SEL : System interrupt select for CPU interrupt source 14.
bits : 16 - 39 (24 bit)
access : read-write
MUX3_SEL : System interrupt select for CPU interrupt source 15.
bits : 24 - 55 (32 bit)
access : read-write
CM4 vector table base
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR22 : Address of CM4 vector table. Note: the CM4 vector table is at an address that is a 1024 B multiple.
bits : 10 - 41 (32 bit)
access : read-write
CM0+ interrupt control 4
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX0_SEL : System interrupt select for CPU interrupt source 16.
bits : 0 - 7 (8 bit)
access : read-write
MUX1_SEL : System interrupt select for CPU interrupt source 17.
bits : 8 - 23 (16 bit)
access : read-write
MUX2_SEL : System interrupt select for CPU interrupt source 18.
bits : 16 - 39 (24 bit)
access : read-write
MUX3_SEL : System interrupt select for CPU interrupt source 19.
bits : 24 - 55 (32 bit)
access : read-write
CM0+ protection context 0 handler
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt.
bits : 0 - 31 (32 bit)
access : read-write
CM0+ interrupt control 5
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX0_SEL : System interrupt select for CPU interrupt source 20.
bits : 0 - 7 (8 bit)
access : read-write
MUX1_SEL : System interrupt select for CPU interrupt source 21.
bits : 8 - 23 (16 bit)
access : read-write
MUX2_SEL : System interrupt select for CPU interrupt source 22.
bits : 16 - 39 (24 bit)
access : read-write
MUX3_SEL : System interrupt select for CPU interrupt source 23.
bits : 24 - 55 (32 bit)
access : read-write
CM0+ interrupt control 6
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX0_SEL : System interrupt select for CPU interrupt source 24.
bits : 0 - 7 (8 bit)
access : read-write
MUX1_SEL : System interrupt select for CPU interrupt source 25.
bits : 8 - 23 (16 bit)
access : read-write
MUX2_SEL : System interrupt select for CPU interrupt source 26.
bits : 16 - 39 (24 bit)
access : read-write
MUX3_SEL : System interrupt select for CPU interrupt source 27.
bits : 24 - 55 (32 bit)
access : read-write
CM0+ interrupt control 7
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX0_SEL : System interrupt select for CPU interrupt source 28.
bits : 0 - 7 (8 bit)
access : read-write
MUX1_SEL : System interrupt select for CPU interrupt source 29.
bits : 8 - 23 (16 bit)
access : read-write
MUX2_SEL : System interrupt select for CPU interrupt source 30.
bits : 16 - 39 (24 bit)
access : read-write
MUX3_SEL : System interrupt select for CPU interrupt source 31.
bits : 24 - 55 (32 bit)
access : read-write
RAM 0 power control
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
Identity
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context of the transfer that reads the register.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier of the transfer that reads the register.
bits : 8 - 19 (12 bit)
access : read-only
Protection status
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE : Protection state: '0': UNKNOWN. '1': VIRGIN. '2': NORMAL. '3': SECURE. '4': DEAD. The following state transistions are allowed (and enforced by HW): - UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD - NORMAL => DEAD - SECURE => DEAD An attempt to make a NOT allowed state transition will NOT affect this register field.
bits : 0 - 2 (3 bit)
access : read-write
RAM 0 power control
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
CM0+ NMI control
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX0_SEL : System interrupt select for CPU NMI. The reset value ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
bits : 0 - 7 (8 bit)
access : read-write
Memory BIST status
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SFP_READY : Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0.
bits : 0 - 0 (1 bit)
access : read-only
SFP_FAIL : Report status of the BIST run, only valid if SFP_READY=1
bits : 1 - 2 (2 bit)
access : read-only
RAM 0 power control
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
CM0+ status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLEEPING : Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.
bits : 0 - 0 (1 bit)
access : read-only
SLEEPDEEP : Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.
bits : 1 - 2 (2 bit)
access : read-only
CM4 power control
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for CM4
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Switch CM4 off
Power off, clock off, isolate, reset and no retain.
1 : RESET
Reset CM4
Clock off, no isolated, no retain and reset.
Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot.
2 : RETAINED
Put CM4 in Retained mode
This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached.
Power off, clock off, isolate, no reset and retain.
3 : ENABLED
Switch CM4 on.
Power on, clock on, no isolate, no reset and no retain.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
CM4 power control
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UP : Number clock cycles delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write
CM4 status
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLEEPING : Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.
bits : 0 - 0 (1 bit)
access : read-only
SLEEPDEEP : Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.
bits : 1 - 2 (2 bit)
access : read-only
PWR_DONE : After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. Note: this flag can also change as a result of a change in debug power up req
bits : 4 - 8 (5 bit)
access : read-only
RAM 0 power control
address_offset : 0x8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
CM4 clock control
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAST_INT_DIV : Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
CM4 NMI control
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX0_SEL : System interrupt select for CPU NMI. The reset value ensure that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
bits : 0 - 7 (8 bit)
access : read-write
RAM 0 power control
address_offset : 0xA54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0xBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0xE74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
ROM trim control
address_offset : 0xF000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RM : N/A
bits : 0 - 3 (4 bit)
access : read-write
RME : Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external pin Read-Write margin settting.
bits : 4 - 8 (5 bit)
access : read-write
RAM trim control
address_offset : 0xF004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RM : N/A
bits : 0 - 3 (4 bit)
access : read-write
RME : Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external RM[3:0] Read-Write margin settting.
bits : 4 - 8 (5 bit)
access : read-write
WPULSE : Write Assist Pulse to control pulse width of negative voltage on SRAM bitline.
bits : 5 - 12 (8 bit)
access : read-write
RA : Read Assist control for WL under-drive.
bits : 8 - 17 (10 bit)
access : read-write
WA : Write assist enable control (Active High). - WA[1:0] Write Assist pins to control negative voltage on SRAM bitline.
bits : 12 - 26 (15 bit)
access : read-write
RAM 0 power control
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
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