\n
address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
Fault control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_EN : Trigger output enable: '0': Disabled. The trigger output 'tr_fault' is '0'. '1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3).
bits : 0 - 0 (1 bit)
access : read-write
OUT_EN : IO output signal enable: '0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. '1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'.
bits : 1 - 2 (2 bit)
access : read-write
RESET_REQ_EN : Reset request enable: '0': Disabled. '1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal.
bits : 2 - 4 (3 bit)
access : read-write
Fault control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_EN : Trigger output enable: '0': Disabled. The trigger output 'tr_fault' is '0'. '1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3).
bits : 0 - 0 (1 bit)
access : read-write
OUT_EN : IO output signal enable: '0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. '1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'.
bits : 1 - 2 (2 bit)
access : read-write
RESET_REQ_EN : Reset request enable: '0': Disabled. '1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal.
bits : 2 - 4 (3 bit)
access : read-write
Fault status
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDX : The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'.
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
0 : MPU_0
Bus master 0 MPU/SMPU.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0' MPU violation; '1': SMPU violation.
1 : MPU_1
Bus master 1 MPU. See MPU_0 description.
2 : MPU_2
Bus master 2 MPU. See MPU_0 description.
3 : MPU_3
Bus master 3 MPU. See MPU_0 description.
4 : MPU_4
Bus master 4 MPU. See MPU_0 description.
5 : MPU_5
Bus master 5 MPU. See MPU_0 description.
6 : MPU_6
Bus master 6 MPU. See MPU_0 description.
7 : MPU_7
Bus master 7 MPU. See MPU_0 description.
8 : MPU_8
Bus master 8 MPU. See MPU_0 description.
9 : MPU_9
Bus master 9 MPU. See MPU_0 description.
10 : MPU_10
Bus master 10 MPU. See MPU_0 description.
11 : MPU_11
Bus master 11 MPU. See MPU_0 description.
12 : MPU_12
Bus master 12 MPU. See MPU_0 description.
13 : MPU_13
Bus master 13 MPU. See MPU_0 description.
14 : MPU_14
Bus master 14 MPU. See MPU_0 description.
15 : MPU_15
Bus master 15 MPU. See MPU_0 description.
16 : CM4_SYS_MPU
CM4 system bus AHB-Lite interface MPU. See MPU_0 description.
28 : MS_PPU_0
Peripheral master interface 0 PPU.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0': PPU violation, '1': peripheral bus error.
29 : MS_PPU_1
Peripheral master interface 0 PPU. See MS_PPU_0 description.
30 : MS_PPU_2
Peripheral master interface 1 PPU. See MS_PPU_0 description.
31 : MS_PPU_3
Peripheral master interface 2 PPU. See MS_PPU_0 description.
32 : GROUP_PPU_0
Peripheral group 0 PPU.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:30]: '0': PPU violation, '1': timeout detected, '2': peripheral bus error.
33 : GROUP_PPU_1
Peripheral group 1 PPU. See GROUP_PPU_0 description.
34 : GROUP_PPU_2
Peripheral group 2 PPU. See GROUP_PPU_0 description.
35 : GROUP_PPU_3
Peripheral group 3 PPU. See GROUP_PPU_0 description.
36 : GROUP_PPU_4
Peripheral group 4 PPU. See GROUP_PPU_0 description.
37 : GROUP_PPU_5
Peripheral group 5 PPU. See GROUP_PPU_0 description.
38 : GROUP_PPU_6
Peripheral group 6 PPU. See GROUP_PPU_0 description.
39 : GROUP_PPU_7
Peripheral group 7 PPU. See GROUP_PPU_0 description.
40 : GROUP_PPU_8
Peripheral group 8 PPU. See GROUP_PPU_0 description.
41 : GROUP_PPU_9
Peripheral group 9 PPU. See GROUP_PPU_0 description.
42 : GROUP_PPU_10
Peripheral group 10 PPU. See GROUP_PPU_0 description.
43 : GROUP_PPU_11
Peripheral group 11 PPU. See GROUP_PPU_0 description.
44 : GROUP_PPU_12
Peripheral group 12 PPU. See GROUP_PPU_0 description.
45 : GROUP_PPU_13
Peripheral group 13 PPU. See GROUP_PPU_0 description.
46 : GROUP_PPU_14
Peripheral group 14 PPU. See GROUP_PPU_0 description.
47 : GROUP_PPU_15
Peripheral group 15 PPU. See GROUP_PPU_0 description.
50 : FLASHC_MAIN_BUS_ERROR
Flash controller, main interface, bus error:
FAULT_DATA0[31:0]: Violating address.
FAULT_DATA1[31]: '0': FLASH macro interface bus error; '1': memory hole.
FAULT_DATA1[15:12]: Protection context identifier.
FAULT_DATA1[11:8]: Master identifier.
End of enumeration elements list.
VALID : Valid indication: '0': Invalid. '1': Valid. HW sets this field to '1' when new fault source data is captured. New fault source data is ONLY captured when VALID is '0'. SW can clear this field to '0' when the fault is handled (by SW).
bits : 31 - 62 (32 bit)
access : read-write
Fault pending 0
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOURCE : This field specifies the following sources: Bit 0: CM0 MPU. Bit 1: CRYPTO MPU. Bit 2: DW 0 MPU. Bit 3: DW 1 MPU. ... Bit 14: CM4 code bus MPU. Bit 15: DAP MPU. Bit 16: CM4 s+G92ystem bus MPU. Bit 28: Peripheral master interface 0 PPU. Bit 29: Peripheral master interface 1 PPU. Bit 30: Peripheral master interface 2 PPU. Bit 31: Peripheral master interface 3 PPU.
bits : 0 - 31 (32 bit)
access : read-only
Fault pending 1
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOURCE : This field specifies the following sources: Bit 0: Peripheral group 0 PPU. Bit 1: Peripheral group 1 PPU. Bit 2: Peripheral group 2 PPU. Bit 3: Peripheral group 3 PPU. Bit 4: Peripheral group 4 PPU. Bit 5: Peripheral group 5 PPU. Bit 6: Peripheral group 6 PPU. Bit 7: Peripheral group 7 PPU. ... Bit 15: Peripheral group 15 PPU. Bit 18: Flash controller, main interface, bus error.
bits : 0 - 31 (32 bit)
access : read-only
Fault pending 2
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOURCE : This field specifies the following sources: Bit 0 - 31: TBD.
bits : 0 - 31 (32 bit)
access : read-only
Fault mask 0
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : Fault source enables: Bits 31-0: Fault sources 31 to 0.
bits : 0 - 31 (32 bit)
access : read-write
Fault mask 1
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : Fault source enables: Bits 31-0: Fault sources 63 to 32.
bits : 0 - 31 (32 bit)
access : read-write
Fault mask 2
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : Fault source enables: Bits 31-0: Fault sources 95 to 64.
bits : 0 - 31 (32 bit)
access : read-write
Fault data
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers.
bits : 0 - 31 (32 bit)
access : read-only
Interrupt
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULT : This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: - STATUS.VALID is set to '1'. - STATUS.IDX specifies the fault source index. - DATA0 through DATA3 captures the fault source dara. SW writes a '1' to these field to clear the interrupt cause to '0'.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULT : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULT : Mask bit for corresponding field in the INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FAULT : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Fault data
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers.
bits : 0 - 31 (32 bit)
access : read-only
Fault data
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers.
bits : 0 - 31 (32 bit)
access : read-only
Fault pending 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOURCE : This field specifies the following sources: Bit 0: CM0 MPU. Bit 1: CRYPTO MPU. Bit 2: DW 0 MPU. Bit 3: DW 1 MPU. ... Bit 14: CM4 code bus MPU. Bit 15: DAP MPU. Bit 16: CM4 s+G92ystem bus MPU. Bit 28: Peripheral master interface 0 PPU. Bit 29: Peripheral master interface 1 PPU. Bit 30: Peripheral master interface 2 PPU. Bit 31: Peripheral master interface 3 PPU.
bits : 0 - 31 (32 bit)
access : read-only
Fault pending 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOURCE : This field specifies the following sources: Bit 0: Peripheral group 0 PPU. Bit 1: Peripheral group 1 PPU. Bit 2: Peripheral group 2 PPU. Bit 3: Peripheral group 3 PPU. Bit 4: Peripheral group 4 PPU. Bit 5: Peripheral group 5 PPU. Bit 6: Peripheral group 6 PPU. Bit 7: Peripheral group 7 PPU. ... Bit 15: Peripheral group 15 PPU. Bit 18: Flash controller, main interface, bus error.
bits : 0 - 31 (32 bit)
access : read-only
Fault pending 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOURCE : This field specifies the following sources: Bit 0 - 31: TBD.
bits : 0 - 31 (32 bit)
access : read-only
Fault data
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers.
bits : 0 - 31 (32 bit)
access : read-only
Fault mask 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : Fault source enables: Bits 31-0: Fault sources 31 to 0.
bits : 0 - 31 (32 bit)
access : read-write
Fault mask 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : Fault source enables: Bits 31-0: Fault sources 63 to 32.
bits : 0 - 31 (32 bit)
access : read-write
Fault mask 2
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : Fault source enables: Bits 31-0: Fault sources 95 to 64.
bits : 0 - 31 (32 bit)
access : read-write
Fault data
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers.
bits : 0 - 31 (32 bit)
access : read-only
Fault status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDX : The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'.
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
0 : MPU_0
Bus master 0 MPU/SMPU.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0' MPU violation; '1': SMPU violation.
1 : MPU_1
Bus master 1 MPU. See MPU_0 description.
2 : MPU_2
Bus master 2 MPU. See MPU_0 description.
3 : MPU_3
Bus master 3 MPU. See MPU_0 description.
4 : MPU_4
Bus master 4 MPU. See MPU_0 description.
5 : MPU_5
Bus master 5 MPU. See MPU_0 description.
6 : MPU_6
Bus master 6 MPU. See MPU_0 description.
7 : MPU_7
Bus master 7 MPU. See MPU_0 description.
8 : MPU_8
Bus master 8 MPU. See MPU_0 description.
9 : MPU_9
Bus master 9 MPU. See MPU_0 description.
10 : MPU_10
Bus master 10 MPU. See MPU_0 description.
11 : MPU_11
Bus master 11 MPU. See MPU_0 description.
12 : MPU_12
Bus master 12 MPU. See MPU_0 description.
13 : MPU_13
Bus master 13 MPU. See MPU_0 description.
14 : MPU_14
Bus master 14 MPU. See MPU_0 description.
15 : MPU_15
Bus master 15 MPU. See MPU_0 description.
16 : CM4_SYS_MPU
CM4 system bus AHB-Lite interface MPU. See MPU_0 description.
28 : MS_PPU_0
Peripheral master interface 0 PPU.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0': PPU violation, '1': peripheral bus error.
29 : MS_PPU_1
Peripheral master interface 0 PPU. See MS_PPU_0 description.
30 : MS_PPU_2
Peripheral master interface 1 PPU. See MS_PPU_0 description.
31 : MS_PPU_3
Peripheral master interface 2 PPU. See MS_PPU_0 description.
32 : GROUP_PPU_0
Peripheral group 0 PPU.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:30]: '0': PPU violation, '1': timeout detected, '2': peripheral bus error.
33 : GROUP_PPU_1
Peripheral group 1 PPU. See GROUP_PPU_0 description.
34 : GROUP_PPU_2
Peripheral group 2 PPU. See GROUP_PPU_0 description.
35 : GROUP_PPU_3
Peripheral group 3 PPU. See GROUP_PPU_0 description.
36 : GROUP_PPU_4
Peripheral group 4 PPU. See GROUP_PPU_0 description.
37 : GROUP_PPU_5
Peripheral group 5 PPU. See GROUP_PPU_0 description.
38 : GROUP_PPU_6
Peripheral group 6 PPU. See GROUP_PPU_0 description.
39 : GROUP_PPU_7
Peripheral group 7 PPU. See GROUP_PPU_0 description.
40 : GROUP_PPU_8
Peripheral group 8 PPU. See GROUP_PPU_0 description.
41 : GROUP_PPU_9
Peripheral group 9 PPU. See GROUP_PPU_0 description.
42 : GROUP_PPU_10
Peripheral group 10 PPU. See GROUP_PPU_0 description.
43 : GROUP_PPU_11
Peripheral group 11 PPU. See GROUP_PPU_0 description.
44 : GROUP_PPU_12
Peripheral group 12 PPU. See GROUP_PPU_0 description.
45 : GROUP_PPU_13
Peripheral group 13 PPU. See GROUP_PPU_0 description.
46 : GROUP_PPU_14
Peripheral group 14 PPU. See GROUP_PPU_0 description.
47 : GROUP_PPU_15
Peripheral group 15 PPU. See GROUP_PPU_0 description.
50 : FLASHC_MAIN_BUS_ERROR
Flash controller, main interface, bus error:
FAULT_DATA0[31:0]: Violating address.
FAULT_DATA1[31]: '0': FLASH macro interface bus error; '1': memory hole.
FAULT_DATA1[15:12]: Protection context identifier.
FAULT_DATA1[11:8]: Master identifier.
End of enumeration elements list.
VALID : Valid indication: '0': Invalid. '1': Valid. HW sets this field to '1' when new fault source data is captured. New fault source data is ONLY captured when VALID is '0'. SW can clear this field to '0' when the fault is handled (by SW).
bits : 31 - 62 (32 bit)
access : read-write
Interrupt
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULT : This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: - STATUS.VALID is set to '1'. - STATUS.IDX specifies the fault source index. - DATA0 through DATA3 captures the fault source dara. SW writes a '1' to these field to clear the interrupt cause to '0'.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULT : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULT : Mask bit for corresponding field in the INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FAULT : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
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