\n
address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-ACQUIRE
STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-RELEASE
STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-NOTIFY
STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-DATA
STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-LOCK_STATUS
STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-ACQUIRE
STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-RELEASE
STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-NOTIFY
STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-DATA
STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-LOCK_STATUS
INTR_STRUCT[1]-INTR_STRUCT[0]-INTR
INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_SET
INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_MASK
INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_MASKED
STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-ACQUIRE
STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-RELEASE
STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-NOTIFY
STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-DATA
STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-LOCK_STATUS
STRUCT[1]-STRUCT[0]-LOCK_STATUS
INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR
INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_SET
INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_MASK
INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_MASKED
STRUCT[7]-STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-ACQUIRE
STRUCT[7]-STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-RELEASE
STRUCT[7]-STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-NOTIFY
STRUCT[7]-STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-DATA
STRUCT[7]-STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-LOCK_STATUS
INTR_STRUCT[3]-INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR
INTR_STRUCT[3]-INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_SET
INTR_STRUCT[3]-INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_MASK
INTR_STRUCT[3]-INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_MASKED
STRUCT[8]-STRUCT[7]-STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-ACQUIRE
STRUCT[8]-STRUCT[7]-STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-RELEASE
STRUCT[8]-STRUCT[7]-STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-NOTIFY
STRUCT[8]-STRUCT[7]-STRUCT[6]-STRUCT[5]-STRUCT[4]-STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-DATA
INTR_STRUCT[4]-INTR_STRUCT[3]-INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR
INTR_STRUCT[4]-INTR_STRUCT[3]-INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_SET
INTR_STRUCT[4]-INTR_STRUCT[3]-INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_MASK
INTR_STRUCT[4]-INTR_STRUCT[3]-INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_MASKED
STRUCT[2]-STRUCT[1]-STRUCT[0]-ACQUIRE
INTR_STRUCT[5]-INTR_STRUCT[4]-INTR_STRUCT[3]-INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR
INTR_STRUCT[5]-INTR_STRUCT[4]-INTR_STRUCT[3]-INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_SET
INTR_STRUCT[5]-INTR_STRUCT[4]-INTR_STRUCT[3]-INTR_STRUCT[2]-INTR_STRUCT[1]-INTR_STRUCT[0]-INTR_MASK
STRUCT[2]-STRUCT[1]-STRUCT[0]-RELEASE
STRUCT[2]-STRUCT[1]-STRUCT[0]-NOTIFY
STRUCT[2]-STRUCT[1]-STRUCT[0]-DATA
STRUCT[2]-STRUCT[1]-STRUCT[0]-LOCK_STATUS
STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-ACQUIRE
STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-RELEASE
STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-NOTIFY
STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-DATA
STRUCT[3]-STRUCT[2]-STRUCT[1]-STRUCT[0]-LOCK_STATUS
IPC acquire
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC lock status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
Interrupt
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
Interrupt
address_offset : 0x10F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0x10F04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0x10F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0x10F0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC acquire
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
IPC acquire
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
IPC acquire
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
Interrupt
address_offset : 0x2020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0x2024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0x2028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0x202C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC release
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC acquire
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
IPC data
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
Interrupt
address_offset : 0x3060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0x3064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0x3068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0x306C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC acquire
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
Interrupt
address_offset : 0x40C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0x40C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0x40C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0x40CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC acquire
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
Interrupt
address_offset : 0x5140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0x5144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0x5148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0x514C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC acquire
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
IPC acquire
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
Interrupt
address_offset : 0x61E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0x61E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0x61E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0x61EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC release
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC acquire
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0x6E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0x6EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0x6F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
IPC lock status
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
Interrupt
address_offset : 0x72A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0x72A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0x72A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0x72AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC notification
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
Interrupt
address_offset : 0x8380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0x8384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0x8388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0x838C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC acquire
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0x84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
Interrupt
address_offset : 0x9480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0x9484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0x9488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0x948C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC acquire
address_offset : 0x9C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0x9C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0x9C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0x9CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0x9D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
Interrupt
address_offset : 0xA5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0xA5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0xA5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0xA5AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC acquire
address_offset : 0xB60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0xB64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0xB68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0xB6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
Interrupt
address_offset : 0xB6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0xB6E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0xB6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0xB6EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC lock status
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
IPC data
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC acquire
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
Interrupt
address_offset : 0xC840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0xC844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0xC848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0xC84C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC data
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
IPC acquire
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0xD28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0xD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
Interrupt
address_offset : 0xD9C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0xD9C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0xD9C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0xD9CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
Interrupt
address_offset : 0xEB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0xEB64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0xEB68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0xEB6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
IPC acquire
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC notification
address_offset : 0xF08 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
IPC data
address_offset : 0xF0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
bits : 31 - 62 (32 bit)
access : read-only
Interrupt
address_offset : 0xFD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt set
address_offset : 0xFD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt mask
address_offset : 0xFD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
Interrupt masked
address_offset : 0xFD2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
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