PROT

P : Privileged setting ('0': user mode; '1': privileged mode). Notes: This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. The default/reset field value provides privileged mode access capabilities.
bits : 0 - 0 (1 bit)
access : read-write

NS : Security setting ('0': secure mode; '1': non-secure mode). Notes: This field is ONLY used for masters that do NOT provide their own secure/non-escure access control attribute. Note that the default/reset field value provides non-secure mode access capabilities to all masters.
bits : 1 - 2 (2 bit)
access : read-write

PRIO : Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). Notes: The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). Masters with the same priority setting form a 'priority group'. Within a 'priority group', roundrobin arbitration is performed.
bits : 8 - 17 (10 bit)
access : read-write

PC_MASK_0 : Protection context mask for protection context '0'. This field is a constant '0': - PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed.
bits : 16 - 32 (17 bit)
access : read-only

PC_MASK_15_TO_1 : Protection context mask for protection contexts '15' downto '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': - PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]).
bits : 17 - 48 (32 bit)
access : read-write

SMPU - MS4_CTL

SMPU - - Master 4 protection context control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write

NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write

PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write

PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only

PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write

MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ADDR

MPU region address
address_offset : 0x101840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write

ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write

MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ATT

MPU region attrributes
address_offset : 0x101844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write

UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write

UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-write

PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write

PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write

PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-write

NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write

REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write

ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write

SMPU_STRUCT[7]-SMPU_STRUCT[6]-SMPU_STRUCT[5]-SMPU_STRUCT[4]-SMPU_STRUCT[3]-SMPU_STRUCT[2]-SMPU_STRUCT[1]-SMPU_STRUCT[0]-ADDR0

SMPU region address 0 (slave structure)
address_offset : 0x10700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write

ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write

SMPU_STRUCT[7]-SMPU_STRUCT[6]-SMPU_STRUCT[5]-SMPU_STRUCT[4]-SMPU_STRUCT[3]-SMPU_STRUCT[2]-SMPU_STRUCT[1]-SMPU_STRUCT[0]-ATT0

SMPU region attributes 0 (slave structure)
address_offset : 0x10704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write

UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write

UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-write

PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write

PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write

PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-write

NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write

PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only

PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write

PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evalution'. '1': PC field participates in 'matching'. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write

SMPU_STRUCT[7]-SMPU_STRUCT[6]-SMPU_STRUCT[5]-SMPU_STRUCT[4]-SMPU_STRUCT[3]-SMPU_STRUCT[2]-SMPU_STRUCT[1]-SMPU_STRUCT[0]-ADDR1

SMPU region address 1 (master structure)
address_offset : 0x10720 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only

ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only

SMPU_STRUCT[7]-SMPU_STRUCT[6]-SMPU_STRUCT[5]-SMPU_STRUCT[4]-SMPU_STRUCT[3]-SMPU_STRUCT[2]-SMPU_STRUCT[1]-SMPU_STRUCT[0]-ATT1

SMPU region attributes 1 (master structure)
address_offset : 0x10724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed). Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only

UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write

UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed). Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only

PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed). Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only

PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write

PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed). Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only

NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write

PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only

REGION_SIZE : This field specifies the region size: '7': 256 B region (8 32 B subregions) Note: this field is read-only.
bits : 24 - 52 (29 bit)
access : read-only

ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write

MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ADDR

MPU region address
address_offset : 0x1072E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ATT

MPU region attrributes
address_offset : 0x1072E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write

UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write

UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-write

PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write

PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write

PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-write

NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write

MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ADDR

MPU region address
address_offset : 0x108C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ATT

MPU region attrributes
address_offset : 0x108C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write

UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write

UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-write

PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write

PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write

PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-write

NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write

MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ADDR

MPU region address
address_offset : 0x10CDA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ATT

MPU region attrributes
address_offset : 0x10CDA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write

UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write

UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-write

PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write

PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write

PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-write

NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write

MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ADDR

MPU region address
address_offset : 0x112880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ATT

MPU region attrributes
address_offset : 0x112884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write

UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write

UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-write

PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write

PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write

PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-write

NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write

MPU[3]-MPU[2]-MPU[1]-MPU[0]-MS_CTL

Master control
address_offset : 0x11800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC : N/A
bits : 0 - 3 (4 bit)
access : read-write

PC_SAVED : Saved protection context. Modifications to this field are constrained by the associated MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields.
bits : 16 - 35 (20 bit)
access : read-write

MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ADDR

MPU region address
address_offset : 0x118680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ATT

MPU region attrributes
address_offset : 0x118684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write

UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write

UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-write

PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write

PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write

PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-write

NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write

MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ADDR

MPU region address
address_offset : 0x11E4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ATT

MPU region attrributes
address_offset : 0x11E4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write

UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write

UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-write

PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write

PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write

PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-write

NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write

MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ADDR

MPU region address
address_offset : 0x1242E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-MPU_STRUCT[7]-MPU_STRUCT[6]-MPU_STRUCT[5]-MPU_STRUCT[4]-MPU_STRUCT[3]-MPU_STRUCT[2]-MPU_STRUCT[1]-MPU_STRUCT[0]-ATT

MPU region attrributes
address_offset : 0x1242E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR : User read enable: '0': Disabled (user, read acceses are NOT allowed). '1': Enabled (user, read acceses are allowed).
bits : 0 - 0 (1 bit)
access : read-write

UW : User write enable: '0': Disabled (user, write acceses are NOT allowed). '1': Enabled (user, write acceses are allowed).
bits : 1 - 2 (2 bit)
access : read-write

UX : User execute enable: '0': Disabled (user, execute acceses are NOT allowed). '1': Enabled (user, execute acceses are allowed).
bits : 2 - 4 (3 bit)
access : read-write

PR : Privileged read enable: '0': Disabled (privileged, read acceses are NOT allowed). '1': Enabled (privileged, read acceses are allowed).
bits : 3 - 6 (4 bit)
access : read-write

PW : Privileged write enable: '0': Disabled (privileged, write acceses are NOT allowed). '1': Enabled (privileged, write acceses are allowed).
bits : 4 - 8 (5 bit)
access : read-write

PX : Privileged execute enable: '0': Disabled (privileged, execute acceses are NOT allowed). '1': Enabled (privileged, execute acceses are allowed).
bits : 5 - 10 (6 bit)
access : read-write

NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write

SMPU_STRUCT[8]-SMPU_STRUCT[7]-SMPU_STRUCT[6]-SMPU_STRUCT[5]-SMPU_STRUCT[4]-SMPU_STRUCT[3]-SMPU_STRUCT[2]-SMPU_STRUCT[1]-SMPU_STRUCT[0]-ADDR0

SMPU region address 0 (slave structure)
address_offset : 0x12900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write

SMPU_STRUCT[8]-SMPU_STRUCT[7]-SMPU_STRUCT[6]-SMPU_STRUCT[5]-SMPU_STRUCT[4]-SMPU_STRUCT[3]-SMPU_STRUCT[2]-SMPU_STRUCT[1]-SMPU_STRUCT[0]-ATT0

SMPU region attributes 0 (slave structure)
address_offset : 0x12904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0