Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAIN_WS : FLASH macro main interface wait states: '0': 0 wait states. ... '15': 15 wait states
bits : 0 - 3 (4 bit)
access : read-write
REMAP : Specifies remapping of FLASH macro main region. '0': No remapping. '1': Remapping. The highest address bit of the FLASH main region is inverted. This effectively remaps the location of FLASH main region physical sectors in the logical address space. In other words, the higher half physical sectors are swapped with the lower half physical sectors. Note: remapping only affects reading of the FLASH main region (over the R interface). It does NOT affect programming/erasing of the FLASH memory region (over the C interface). E.g., for a 512 KB / 4 Mb main region, the logical address space ranges from [0x1000:0000, 0x1007:ffff] (the highest bit if the FLASH main region is bit 18). The memory has four physical sectors: sectors 0, 1, 2 and 3. If REMAP is '0', the physical regions logical addresses are as follows: - The physical region 0: [0x1000:0000, 0x1001:ffff]. - The physical region 1: [0x1002:0000, 0x1003:ffff]. - The physical region 2: [0x1004:0000, 0x1005:ffff]. - The physical region 3: [0x1006:0000, 0x1007:ffff]. If REMAP is '1', the physical regions logical addresses are as follows: - The physical region 0: [0x1004:0000, 0x1005:ffff]. - The physical region 1: [0x1006:0000, 0x1007:ffff]. - The physical region 2: [0x1000:0000, 0x1001:ffff]. - The physical region 3: [0x1002:0000, 0x1003:ffff]. Note: when the REMAP is changed, SW should invalidate the caches and buffers.
bits : 8 - 16 (9 bit)
access : read-write
Flash Macro Registers - - Flash macro control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FM_MODE : Flash macro mode selection: '0': Normal functional mode. '1': Sets 'pre-program control bit' for soft pre-program operation of all selected SONOS cells. the control bit is cleared by the HW after any program operation. '2': Sets ... '15': TBD
bits : 0 - 3 (4 bit)
access : read-write
FM_SEQ : Flash macro sequence select: '0': TBD '1': TBD '2': TBD '3': TBD
bits : 8 - 17 (10 bit)
access : read-write
DAA_MUX_SEL : Direct memory cell access address.
bits : 16 - 38 (23 bit)
access : read-write
IF_SEL : Interface selection. Specifies the interface that is used for flash memory read operations: '0': R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. '1': C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure.
bits : 24 - 48 (25 bit)
access : read-write
WR_EN : '0': normal mode '1': Fm Write Enable
bits : 25 - 50 (26 bit)
access : read-write
Flash Macro Registers - - Supervisory flash geometry
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORD_SIZE_LOG2 : Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2.
bits : 0 - 3 (4 bit)
access : read-only
PAGE_SIZE_LOG2 : Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2.
bits : 4 - 11 (8 bit)
access : read-only
ROW_COUNT : Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT
bits : 8 - 31 (24 bit)
access : read-only
BANK_COUNT : Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT.
bits : 24 - 55 (32 bit)
access : read-only
BIST control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPCODE : This field specifies how the data check should be performed after reading the data from Flash memory. '0': Read the Flash and compare the output to BIST_DATA (R0). '1': Read the Flash and compare the output to the binary complement of BIST_DATA (R1). '2': Read the Flash and compare with BIST_DATA[] and compliment of BIST_DATA alternately (R01). The expected data of the first read is BIST_DATA, expected data of the second read is binary compliment of BIST_DATA, third read expected data is BIST_DATA, fourth read expected data is binary compliment of BIST_DATA and so on.
bits : 0 - 1 (2 bit)
access : read-write
UP : Specifies direction in which Flash BIST steps through addresses: ''0': BIST steps through the Flash from the maximum row and column addresses (as specified by a design time configurtion parameter when ADDR_START_ENABLED is '0' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is '1') to the minimum row and column addresses. '1': BIST steps through the Flash from the minimum row and column addresses ('0' when ADDR_START_ENABLED is '0' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is '1') to the maximum row and column addresses.
bits : 2 - 4 (3 bit)
access : read-write
ROW_FIRST : Specifies how the Flash BIST addresses are generated: '0': Column address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its mimimum/maximum value and only then is the row address incremented/decremented. '1': Row address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its mimimum/maximum value and only then is the column address incremented/decremented.
bits : 3 - 6 (4 bit)
access : read-write
ADDR_START_ENABLED : Specifies Flash BIST start addresses: '0': Row and column addresses start with their maximum/minimum values. '1': Row and column addresses start with their values as specified by BIST_ADDR_START. This feature is supported only for simple increment/decrement patterns. It is not supported with address compliment pattern (BIST_CTL.ADDR_COMPLIMENT_ENABLED) or address pattern which increments/decrements both row address and column address (BIST_CTL.INCR_DECR_BOTH) for every read.
bits : 4 - 8 (5 bit)
access : read-write
ADDR_COMPLIMENT_ENABLED : Specifies to generate address compliment patterns. '0': Generate normal increment/decrement patterns. '1': Generate address patterns which interleaves compliment of previous address in between. Example: The following is an exaple pattern, With UP=1 and ROW_FIRST =0 00_00 11_11 00_01 11_10 00_10 11_01 ...
bits : 5 - 10 (6 bit)
access : read-write
INCR_DECR_BOTH : Specifies to generate patterns where both column address and row address are incremented/decremented simultaneously. '0': Generate normal increment/decrement patterns. '1': Generate address patterns with both row and column address changing. Example: With UP = 1 and ROW_FIRST = 0 00_00 01_01 10_10 11_11 00_01 01_10 10_11 11_00 00_10 ...
bits : 6 - 12 (7 bit)
access : read-write
STOP_ON_ERROR : Specifies the BIST to continue indefinitely, regardless of occurrence of errors or not. '0': BIST controller doesn't stop on the data failures, it continues regardless of the errors. '1': BIST controller stops on when the first data failure is encounted.
bits : 7 - 14 (8 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST command
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : 1': Start FLASH BIST. Hardware set this field to '0' when BIST is completed.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x10744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST address start register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COL_ADDR_START : Column start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of columns of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with n columns, the legal range is [0, n-1].
bits : 0 - 15 (16 bit)
access : read-write
ROW_ADDR_START : Row start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of rows of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with m columns, the legal range is [0, m-1].
bits : 16 - 47 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x10B48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x10FC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x1179C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x11840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x120C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x123F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1294C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x13050 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x131D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x13A68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x13CB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Timer control
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples.
bits : 0 - 15 (16 bit)
access : read-write
SCALE : Timer tick scale: '0': 1 microsecond. '1': 100 microseconds.
bits : 16 - 32 (17 bit)
access : read-write
PUMP_CLOCK_SEL : Pump clock select: '0': internal clock. '1': external clock.
bits : 24 - 48 (25 bit)
access : read-write
PRE_PROG : '1' during pre-program operation
bits : 25 - 50 (26 bit)
access : read-write
PRE_PROG_CSL : '0' CSL lines driven by CSL_DAC '1' CSL lines driven by VNEG_G
bits : 26 - 52 (27 bit)
access : read-write
PUMP_EN : Pump enable: '0': disabled '1': enabled (also requires FM_CTL.IF_SEL to be '1', this additional restriction is reuired to prevent non intential clearing of the FM). SW sets this field to '1' to generate a single PE pulse. HW clears this field when timer is expired.
bits : 29 - 58 (30 bit)
access : read-write
ACLK_EN : ACLK enable (generates a single cycle pulse for the FM): '0': disabled '1': enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated.
bits : 30 - 60 (31 bit)
access : read-write
TIMER_EN : Timer enable: '0': disabled '1': enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired.
bits : 31 - 62 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x1420 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x142FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x14914 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x14B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x15430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x1557C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0x1564 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x15CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x161E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x16574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x16AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
BIST address register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COL_ADDR : Current column address.
bits : 0 - 15 (16 bit)
access : read-only
ROW_ADDR : Current row address.
bits : 16 - 47 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x16E1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x16E58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
BIST status register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAIL : 0': BIST passed. '1': BIST failed.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x176C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x17ACC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x17F78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x17F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Analog control 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSLDAC : Trimming of common source line DAC.
bits : 8 - 18 (11 bit)
access : read-write
VCC_SEL : Vcc select: '0': 1.2 V : LP reset value '1': 0.95 V: ULP reset value Note: the flash macro compiler has a configuration option that specifies the default/reset value of this field.
bits : 24 - 48 (25 bit)
access : read-write
FLIP_AMUXBUS_AB : Flips amuxbusa and amuxbusb '0': amuxbusa, amuxbusb '1': amuxbusb, amuxbusb
bits : 27 - 54 (28 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x1800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x18744 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1882C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x190E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x193C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0x1948 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x199A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x1A040 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1A260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x1A9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1AB24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x1ACC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1B3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x1B94C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1BCB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x1BF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Analog control 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDAC : Trimming of the output margin Voltage as a function of Vpos and Vneg.
bits : 0 - 7 (8 bit)
access : read-write
PDAC : Trimming of positive pump output Voltage:
bits : 16 - 35 (20 bit)
access : read-write
NDAC : Trimming of negative pump output Voltage:
bits : 24 - 51 (28 bit)
access : read-write
VPROT_OVERRIDE : '0': vprot = BG.vprot. '1': vprot = vcc
bits : 28 - 56 (29 bit)
access : read-write
R_GRANT_CTL : r_grant control: '0': r_grant normal functionality '1': forces r_grant LO synchronized on clk_r
bits : 29 - 58 (30 bit)
access : read-write
RST_SFT_HVPL : '1': Page Latches Soft Reset
bits : 30 - 60 (31 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1C588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x1C5D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1CE5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x1D268 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0x1D50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1D734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x1DEFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1E010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1E8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x1EB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x1EB94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1F1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x1F830 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x1FABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - N/A, DNU
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DNU_0X20_1 : N/A
bits : 1 - 2 (2 bit)
access : read-only
DNU_0X20_2 : N/A
bits : 2 - 4 (3 bit)
access : read-only
DNU_0X20_3 : N/A
bits : 3 - 6 (4 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x200C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x2014 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x203A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x204D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x20C98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x21174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2158C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x217C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
BIST data register(s)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x21E1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x21E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x22780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x22AC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0x22E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x23080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x23778 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x23984 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Test mode control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEST_MODE : Test mode control: '0'-'31': TBD
bits : 0 - 4 (5 bit)
access : read-write
PN_CTL : Postive/negative margin mode control: '0': negative margin control '1': positive margin control
bits : 8 - 16 (9 bit)
access : read-write
TM_PE : PUMP_EN override: Pump Enable =PUMP_EN | PE_TM
bits : 9 - 18 (10 bit)
access : read-write
TM_DISPOS : Test mode positive pump disable
bits : 10 - 20 (11 bit)
access : read-write
TM_DISNEG : Test mode negative pump disable
bits : 11 - 22 (12 bit)
access : read-write
EN_CLK_MON : 1: enables the oscillator output monitor
bits : 16 - 32 (17 bit)
access : read-write
CSL_DEBUG : Engineering Debug Register
bits : 17 - 34 (18 bit)
access : read-write
ENABLE_OSC : 0': the oscillator enable logic has control over the internal oscillator '1': forces oscillator enable HI
bits : 18 - 36 (19 bit)
access : read-write
UNSCRAMBLE_WA : See BSN-242 memo '0': normal '1': disables the Word Address scrambling
bits : 31 - 62 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x2404 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2428C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x2442C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0x2458 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x24B98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x250E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x254A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data actual register(s)
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the actual Flash data output that caused the BIST failure.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0x25CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x25DA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x25DBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x266D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x26A60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x26FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x2744 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x27724 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x27910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Wiat State control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_FM_MEM_RD : Number of C interface wait cycles (on 'clk_c') for a read from the memory
bits : 0 - 3 (4 bit)
access : read-write
WAIT_FM_HV_RD : Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. Common for reading HV Page Latches and the DATA_COMP_RESULT bit
bits : 8 - 19 (12 bit)
access : read-write
WAIT_FM_HV_WR : Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches.
bits : 16 - 34 (19 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x28234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x283EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x28B5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x28C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x290B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x29488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data expected register(s)
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the expected Flash data output.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x29D88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x29DB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2A6EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x2AA5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2B024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x2B734 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2B960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Monitor Status
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
POS_PUMP_VLO : POS pump VLO
bits : 1 - 2 (2 bit)
access : read-only
NEG_PUMP_VHI : NEG pump VHI
bits : 2 - 4 (3 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2C2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x2C410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2CBE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x2D0F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2D52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x2DDD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2DE78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2E7C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x2EABC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2F11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x2F7A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x2FA74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Scratch Control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUMMY32 : Scratchpad register fields. Provided for test purposes.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x300C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x303D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x30498 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x30D30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x3118C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x31694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x31E84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x31FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data register(s)
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x32968 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x32B80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x332D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x33880 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x33C4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - High voltage control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER_CLOCK_FREQ : Specifies the frequency in MHz of the timer clock 'clk_t' as provide to the flash macro. E.g., if '4', the timer clock 'clk_t' has a frequency of 4 MHz.
bits : 0 - 7 (8 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x34584 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x345C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x34F40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x3528C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x358C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x35F98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x36244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x36BCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x36CA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x37558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x379BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x37EE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Aclk control
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ACLK_GEN : A write to this register generates a ACLK pulse for the flash macro (also requires FM_CTL.IF_SEL to be '1').
bits : 0 - 0 (1 bit)
access : write-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x383C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x386D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
BIST data actual register(s)
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the actual Flash data output that caused the BIST failure.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3887C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x39214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x393F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x39BB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x3A110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3A550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x3AE34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3AEF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3B89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x3BB5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Interrupt
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER_EXPIRED : Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x3C18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3C248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x3C888 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3CBF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3D5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x3D5B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3DF64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x3E2EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
BIST data expected register(s)
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the expected Flash data output.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3E920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x3F024 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3F2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x3FCA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x3FD60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash power control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Controls 'enable' pin of the Flash memory.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_HV : Controls 'enable_hv' pin of the Flash memory.
bits : 1 - 2 (2 bit)
access : read-write
Flash Macro Registers - - Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HV_TIMER_RUNNING : Indicates if the high voltage timer is running: '0': not running '1': running
bits : 0 - 0 (1 bit)
access : read-only
HV_REGS_ISOLATED : Indicates the isolation status at HV trim and redundancy registers inputs '0' - Not isolated, writing permitted '1' - isolated writing disabled
bits : 1 - 2 (2 bit)
access : read-only
ILLEGAL_HVOP : Indicates a bulk,sector erase, program has been requested when axa=1 '0' - no error '1' - illegal HV operation error
bits : 2 - 4 (3 bit)
access : read-only
TURBO_N : After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. Used in the testchip boot only as an 'FM READY' flag. '0' - turbo mode '1' - normal mode
bits : 3 - 6 (4 bit)
access : read-only
WR_EN_MON : FM_CTL.WR_EN bit after being synchronized in clk_r domain
bits : 4 - 8 (5 bit)
access : read-only
IF_SEL_MON : FM_CTL.IF_SEL bit after being synchronized in clk_r domain
bits : 5 - 10 (6 bit)
access : read-only
Flash Macro Registers - - Interrupt set
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER_EXPIRED : Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
CM0+ cache control
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAY : Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2.
bits : 16 - 33 (18 bit)
access : read-write
SET_ADDR : Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2.
bits : 24 - 50 (27 bit)
access : read-write
PREF_EN : Prefetch enable: '0': Disabled. '1': Enabled. Prefetching requires the cache to be enabled; i.e. ENABLED is '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Cache enable: '0': Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ cache control
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for CM0 cache
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4066C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
CM0+ cache control
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRUP_DELAY : Number clock cycles delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x40AA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
CM0+ cache command
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : FLASH cache invalidation. SW writes a '1' to clear the cache. W sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The cache's LRU structure is also reset to its default state.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x41038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x417E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x41A08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x423DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x4252C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x42DB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x43278 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x43790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data register(s)
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x43FC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Interrupt mask
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER_EXPIRED : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
CM0+ cache status 0
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALID16 : Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.
bits : 0 - 15 (16 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x44170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
CM0+ cache status 1
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.
bits : 0 - 31 (32 bit)
access : read-only
CM0+ cache status 2
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LRU : Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): Bit 5: 0_LRU_1: way 0 less recently used than way 1. Bit 4: 0_LRU_2. Bit 3: 0_LRU_3. Bit 2: 1_LRU_2. Bit 1: 1_LRU_3. Bit 0: 2_LRU_3.
bits : 0 - 5 (6 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x44B54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x44D1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4553C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x45A74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x45F28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x467D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x46918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4730C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x47530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x47D04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Interrupt masked
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMER_EXPIRED : Logical and of corresponding request and mask fields.
bits : 0 - 0 (1 bit)
access : read-only
CM4 cache control
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAY : See CM0_CA_CTL.
bits : 16 - 33 (18 bit)
access : read-write
SET_ADDR : See CM0_CA_CTL.
bits : 24 - 50 (27 bit)
access : read-write
PREF_EN : See CM0_CA_CTL.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See CM0_CA_CTL.
bits : 31 - 62 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x4828 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x48294 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
CM4 cache control
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for CM4 cache
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RSVD
undefined
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x48700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
CM4 cache control
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRUP_DELAY : Number clock cycles delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write
CM4 cache command
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : See CM0_CA_CMD.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x48FFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x49100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x49B04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x49D68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4A50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x4AAD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4AF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x4B84C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4B928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data actual register(s)
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the actual Flash data output that caused the BIST failure.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data (for all page latches)
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Write all high Voltage page latches with the same 32-bit data in a single write cycle
bits : 0 - 31 (32 bit)
access : write-only
CM4 cache status 0
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALID16 : See CM0_CA_STATUS0.
bits : 0 - 15 (16 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4C33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
CM4 cache status 1
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : See CM0_CA_STATUS1.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x4C5C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
CM4 cache status 2
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LRU : See CM0_CA_STATUS2.
bits : 0 - 5 (6 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4CD54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x4D340 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4D770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x4E0C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4E190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4EBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x4EE44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x4F5DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x4FBCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Cal control BG LO trim bits
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCT_TRIM_LO_HV : LO Bandgap Voltage Temperature Compensation trim control.
bits : 0 - 4 (5 bit)
access : read-write
CDAC_LO_HV : LO Temperature compensated trim DAC. To control Vcstat slope for Vpos.
bits : 5 - 12 (8 bit)
access : read-write
VBG_TRIM_LO_HV : LO Bandgap Voltage trim control.
bits : 8 - 20 (13 bit)
access : read-write
VBG_TC_TRIM_LO_HV : LO Bandgap Voltage Temperature Compensation trim control
bits : 13 - 28 (16 bit)
access : read-write
IPREF_TRIM_LO_HV : LO Bandgap IPTAT trim control.
bits : 16 - 35 (20 bit)
access : read-write
Cryptography buffer control
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREF_EN : Prefetch enable: '0': Disabled. '1': Enabled. Prefetching requires the buffer to be enabled; i.e. ENABLED is '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Cache enable: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x50008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Cryptography buffer command
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : FLASH buffer invalidation. SW writes a '1' to clear the buffer. HW sets this field to '0' when the operation is completed.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x50958 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x50A38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5146C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x516E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x51EA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x5247C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x528E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x53214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x53320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data expected register(s)
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the expected Flash data output.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x53D64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x53FB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Cal control BG HI trim bits
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCT_TRIM_HI_HV : HI Bandgap Voltage Temperature Compensation trim control.
bits : 0 - 4 (5 bit)
access : read-write
CDAC_HI_HV : HI Temperature compensated trim DAC. To control Vcstat slope for Vpos.
bits : 5 - 12 (8 bit)
access : read-write
VBG_TRIM_HI_HV : HI Bandgap Voltage trim control.
bits : 8 - 20 (13 bit)
access : read-write
VBG_TC_TRIM_HI_HV : HI Bandgap Voltage Temperature Compensation trim control.
bits : 13 - 28 (16 bit)
access : read-write
IPREF_TRIM_HI_HV : HI Bandgap IPTAT trim control.
bits : 16 - 35 (20 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x543C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x547AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x54D50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x551F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data register(s)
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x55AF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x55C48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5669C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x5689C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x570F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x57648 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x57B50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Cal control BG LO and HI ipref trim, ref sel, fm_active, turbo_ext
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICREF_TRIM_LO_HV : LO Bandgap Current trim control.
bits : 0 - 4 (5 bit)
access : read-write
ICREF_TC_TRIM_LO_HV : LO Bandgap Current Temperature Compensation trim control
bits : 5 - 12 (8 bit)
access : read-write
ICREF_TRIM_HI_HV : HI Bandgap Current trim control.
bits : 8 - 20 (13 bit)
access : read-write
ICREF_TC_TRIM_HI_HV : HI Bandgap Current Temperature Compensation trim control.
bits : 13 - 28 (16 bit)
access : read-write
VREF_SEL_HV : Voltage reference: '0': internal bandgap reference '1': external voltage reference
bits : 16 - 32 (17 bit)
access : read-write
IREF_SEL_HV : Current reference: '0': internal current reference '1': external current reference
bits : 17 - 34 (18 bit)
access : read-write
FM_ACTIVE_HV : 0: No Action 1: Forces FM SYS in active mode
bits : 18 - 36 (19 bit)
access : read-write
TURBO_EXT_HV : 0: turbo signal generated internally 1: turbo cleared by clk_pump_ext HI
bits : 19 - 38 (20 bit)
access : read-write
Datawire 0 buffer control
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREF_EN : See CRYPTO_BUFF_CTL.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See CRYPTO_BUFF_CTL.
bits : 31 - 62 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x583F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x585B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Datawire 0 buffer command
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : See CRYPTO_BUFF_CMD.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x58B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x59014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x591AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x59A7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x59F64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5A4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x5AD20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5AF58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5B9CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x5BAE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Cal control osc trim bits, idac, sdac, itim, bdac.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSC_TRIM_HV : Flash macro pump clock trim control.
bits : 0 - 3 (4 bit)
access : read-write
OSC_RANGE_TRIM_HV : 0: Oscillator High Frequency Range 1: Oscillator Low Frequency range
bits : 4 - 8 (5 bit)
access : read-write
IDAC_HV : N/A
bits : 5 - 13 (9 bit)
access : read-write
SDAC_HV : N/A
bits : 9 - 19 (11 bit)
access : read-write
ITIM_HV : Trimming of timing current
bits : 11 - 25 (15 bit)
access : read-write
VDDHI_HV : 0': vdd<2.3V '1': vdd>=2.3V
bits : 15 - 30 (16 bit)
access : read-write
TURBO_PULSEW_HV : Turbo pulse width trim
bits : 16 - 33 (18 bit)
access : read-write
BGLO_EN_HV : LO Bandgap Enable
bits : 18 - 36 (19 bit)
access : read-write
BGHI_EN_HV : HI Bandgap Enable
bits : 19 - 38 (20 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5C444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x5C8A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5CEC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x5D66C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5D940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5E3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x5E438 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5EE4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x5F208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
BIST data actual register(s)
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the actual Flash data output that caused the BIST failure.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x5F8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x5FFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Bookmark register - keeps the current FW HV seq
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BOOKMARK : Used by FW. Keeps the Current HV cycle sequence
bits : 0 - 31 (32 bit)
access : write-only
Datawire 1 buffer control
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREF_EN : See CRYPTO_BUFF_CTL.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See CRYPTO_BUFF_CTL.
bits : 31 - 62 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x60368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x6054 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Datawire 1 buffer command
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : See CRYPTO_BUFF_CMD.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x60DB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x60DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x60DFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x61894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x61B90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x62330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x62970 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x62DD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x63754 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x63874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6431C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x6453C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x64DC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x65328 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x65878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x66118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6632C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x66DE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x66F0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
BIST data register(s)
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x678A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x67D04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Debug access port buffer control
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREF_EN : See CRYPTO_BUFF_CTL.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See CRYPTO_BUFF_CTL.
bits : 31 - 62 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x68360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Debug access port buffer command
address_offset : 0x688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : See CRYPTO_BUFF_CMD.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x68B00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x68E24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data expected register(s)
address_offset : 0x694 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the expected Flash data output.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x698EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x69900 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6A3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x6A704 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6AE88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x6B50C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6B95C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x6C318 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6C434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x6C70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6CF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x6D128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6D9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x6DF3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6E4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x6ED54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6EFBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x6FAA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x6FB70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
External master 0 buffer control
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREF_EN : See CRYPTO_BUFF_CTL.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See CRYPTO_BUFF_CTL.
bits : 31 - 62 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x70598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
External master 0 buffer command
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : See CRYPTO_BUFF_CMD.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x70990 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7108C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x717B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x71B84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x725DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x72680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data actual register(s)
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the actual Flash data output that caused the BIST failure.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x73180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x73408 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x73C84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x74238 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7478C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x7506C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x75298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x75DA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x75EA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x768BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x76CE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x773D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x77B20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x77EF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
External master 1 buffer control
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREF_EN : See CRYPTO_BUFF_CTL.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : See CRYPTO_BUFF_CTL.
bits : 31 - 62 (32 bit)
access : read-write
External master 1 buffer command
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : See CRYPTO_BUFF_CMD.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x7890 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x78964 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x78A10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data register(s)
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x79534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x796C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x797AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7A05C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x7A5F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7AB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x7B448 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7B6B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7C1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x7C29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7CD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x7D0F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7D860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x7DF50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7E3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x7EDB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7EEE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data expected register(s)
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the expected Flash data output.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x7FA2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x7FC14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Command
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : FLASH cache and buffer invalidation for ALL cache and buffers. SW writes a '1' to clear the cache and buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state.
bits : 0 - 0 (1 bit)
access : read-write
Flash Macro Registers - - Flash macro address
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Row address.
bits : 0 - 15 (16 bit)
access : read-write
BA : Bank address.
bits : 16 - 39 (24 bit)
access : read-write
AXA : Auxiliairy address field: '0': regular flash memory. '1': supervisory flash memory.
bits : 24 - 48 (25 bit)
access : read-write
Flash Macro Registers - - Redundancy Control normal sectors 0,1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RED_ADDR_0 : Bad Row Pair Address for Sector 0
bits : 0 - 7 (8 bit)
access : read-write
RED_EN_0 : '1': Redundancy Enable for Sector 0
bits : 8 - 16 (9 bit)
access : read-write
RED_ADDR_1 : Bad Row Pair Address for Sector 1
bits : 16 - 39 (24 bit)
access : read-write
RED_EN_1 : '1': Redundancy Enable for Sector 1
bits : 24 - 48 (25 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x80578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x80A7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x810C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x818E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x81A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x81C1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x82758 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x82774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x832D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x835CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x83E30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Redundancy Controll normal sectors 2,3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RED_ADDR_2 : Bad Row Pair Address for Sector 2
bits : 0 - 7 (8 bit)
access : read-write
RED_EN_2 : 1': Redundancy Enable for Sector 2
bits : 8 - 16 (9 bit)
access : read-write
RED_ADDR_3 : Bad Row Pair Address for Sector 3
bits : 16 - 39 (24 bit)
access : read-write
RED_EN_3 : 1': Redundancy Enable for Sector 3
bits : 24 - 48 (25 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x84444 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x84994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x84B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x852C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x854FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x86068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x86140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x86BD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x86FC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
BIST data actual register(s)
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the actual Flash data output that caused the BIST failure.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x8774C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x87E4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Redundancy Controll normal sectors 4,5
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DNU_45_1 : Not Used
bits : 0 - 0 (1 bit)
access : read-write
REG_ACT_HV : Forces the VBST regulator in active mode all the time
bits : 1 - 2 (2 bit)
access : read-write
DNU_45_3 : Not Used
bits : 2 - 4 (3 bit)
access : read-write
FDIV_TRIM_HV_0 : '2b00' F = 1MHz see fdiv_trim_hv<1> value as well '2b01' F = 0.5MHz '2b10' F = 2MHz '2b11' F = 4Mhz
bits : 3 - 6 (4 bit)
access : read-write
DNU_45_5 : Not Used
bits : 4 - 8 (5 bit)
access : read-write
FDIV_TRIM_HV_1 : '2b00' F = 1MHz see fdiv_trim_hv<0> value as well '2b01' F = 0.5MHz '2b10' F = 2MHz '2b11' F = 4Mhz
bits : 5 - 10 (6 bit)
access : read-write
DNU_45_6 : Not Used
bits : 6 - 12 (7 bit)
access : read-write
VLIM_TRIM_HV_0 : '2b00' V2 = 650mV see vlim_trim_hv<1> value as well '2b01' V2 = 600mV '2b10' V2 = 750mV '2b11' V2 = 700mV
bits : 7 - 14 (8 bit)
access : read-write
DNU_45_8 : Not Used
bits : 8 - 16 (9 bit)
access : read-write
DNU_45_23_16 : Not Used
bits : 16 - 39 (24 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x882C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x88CD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x88E40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x899C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x89B68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x89E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x8A544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x8A9FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x8B0CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data register(s)
address_offset : 0x8B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x8B894 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x8BC58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Redundancy Controll normal sectors 6,7
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLIM_TRIM_HV_1 : '2b00' V2 = 650mV see vlim_trim_hv<0> value as well '2b01' V2 = 600mV '2b10' V2 = 750mV '2b11' V2 = 700mV
bits : 0 - 0 (1 bit)
access : read-write
DNU_67_1 : Not Used
bits : 1 - 2 (2 bit)
access : read-write
VPROT_ACT_HV : Forces VPROT in active mode all the time
bits : 2 - 4 (3 bit)
access : read-write
DNU_67_3 : Not Used
bits : 3 - 6 (4 bit)
access : read-write
IPREF_TC_HV : Reduces the IPREF Tempco by not subtracting ICREF form IPREF - IPREF will be 1uA
bits : 4 - 8 (5 bit)
access : read-write
DNU_67_5 : Not Used
bits : 5 - 10 (6 bit)
access : read-write
IPREF_TRIMA_HI_HV : Adds 200-300nA boost on IPREF_HI
bits : 6 - 12 (7 bit)
access : read-write
DNU_67_7 : Not Used
bits : 7 - 14 (8 bit)
access : read-write
IPREF_TRIMA_LO_HV : Adds 200-300nA boost on IPREF_LO
bits : 8 - 16 (9 bit)
access : read-write
DNU_67_23_16 : Not Used
bits : 16 - 39 (24 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x8C730 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x8C7E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x8D37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x8D5D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x8DF14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x8E474 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x8EAB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x8F31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x8F650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Redundancy Controll special sectors 0,1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RED_ADDR_SM0 : Bad Row Pair Address for Special Sector 0
bits : 0 - 7 (8 bit)
access : read-write
RED_EN_SM0 : Redundancy Enable for Special Sector 0
bits : 8 - 16 (9 bit)
access : read-write
RED_ADDR_SM1 : Bad Row Pair Address for Special Sector 1
bits : 16 - 39 (24 bit)
access : read-write
RED_EN_SM1 : Redundancy Enable for Special Sector 1
bits : 24 - 48 (25 bit)
access : read-write
TRKD : Sense Amp Control tracking delay
bits : 30 - 60 (31 bit)
access : read-write
R_GRANT_EN : '0': r_grant handshake disabled, r_grant always 1. '1': r_grand handshake enabled
bits : 31 - 62 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x901C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x901F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x90D9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x90DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x91078 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x91948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x91F2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x9220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x924F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x92DE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x930AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x93C64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x93CA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x94820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x94B60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
BIST data expected register(s)
address_offset : 0x950 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the expected Flash data output.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x953E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x95A24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x95FA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x968EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x96B6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Do Not Use
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x97738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x977B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x98308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x98688 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x98EDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x9955C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x99AB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x9A434 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x9A64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x9A690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x9B270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x9B310 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
BIST data actual register(s)
address_offset : 0x9B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the actual Flash data output that caused the BIST failure.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x9BE54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x9C1F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x9CA3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x9D08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x9D0D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x9D628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
BIST data register(s)
address_offset : 0x9DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x9DFBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x9E218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x9EE0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x9EEA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0x9FA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0x9FD98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xA0600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xA0C8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xA1B84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xA2A80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xA2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xA3980 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xA4884 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xA578C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xA6698 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xA75A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xA84BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xA938 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xA93D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xAA2F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xAAF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xAB210 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
BIST data expected register(s)
address_offset : 0xAB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the expected Flash data output.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xAC134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xAD05C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xADF88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xAEEB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
BIST data actual register(s)
address_offset : 0xAFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the actual Flash data output that caused the BIST failure.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xAFDEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xB0D24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xB1C60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xB2BA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xB348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xB3AE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xB4A2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xB56C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xB5978 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xB68C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xB781C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xB8774 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xB96D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xBA630 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xBB594 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xBB9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xBC4FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xBD468 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xBE3D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xBF34C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Regular flash geometry
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORD_SIZE_LOG2 : Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: '0': 1 Byte '1': 2 Bytes '2': 4 Bytes ... '7': 128 Bytes The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively.
bits : 0 - 3 (4 bit)
access : read-only
PAGE_SIZE_LOG2 : Number of Bytes per page (log 2): '0': 1 Byte '1': 2 Bytes '2': 4 Bytes ... '15': 32768 Bytes The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively.
bits : 4 - 11 (8 bit)
access : read-only
ROW_COUNT : Number of rows (minus 1): '0': 1 row '1': 2 rows '2': 3 rows ... '65535': 65536 rows
bits : 8 - 31 (24 bit)
access : read-only
BANK_COUNT : Number of banks (minus 1): '0': 1 bank '1': 2 banks ... '255': 256 banks
bits : 24 - 55 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC02C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC1240 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC1A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
BIST data expected register(s)
address_offset : 0xC1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : This field specified the expected Flash data output.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC21C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC3144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xC3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC40CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC5058 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC5FE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC6F7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC7F14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC8EB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xC9E50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xCADF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xCBD9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xCC50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xCCD48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xCDCF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xCDE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xCECAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xCFC64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xD0C20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xD1BE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xD2BA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xD3B6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xD4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xD4B38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xD5B08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xD6ADC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xD7AB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xD8A90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xD9A70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xDA20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xDAA54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xDBA3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xDCA28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xDD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xDDA18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xDEA0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xDFA04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xE0A00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xE57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xE664 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xEDE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xF2AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
Flash Macro Registers - - Do Not Use
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA_COMP_RESULT : The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
bits : 0 - 0 (1 bit)
access : read-only
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xF658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro high Voltage page latches data
address_offset : 0xFECC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write
Flash Macro Registers - - Flash macro memory sense amplifier and column decoder data
address_offset : 0xFEF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA32 : Sense amplifier and cloumn multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only
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