Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
MCWDT_STRUCT[0]-MCWDT_INTR_SET
MCWDT_STRUCT[0]-MCWDT_INTR_MASK
MCWDT_STRUCT[0]-MCWDT_INTR_MASKED
MCWDT_STRUCT[1]-MCWDT_STRUCT[0]-MCWDT_CNTLOW
MCWDT_STRUCT[1]-MCWDT_STRUCT[0]-MCWDT_CNTHIGH
MCWDT_STRUCT[1]-MCWDT_STRUCT[0]-MCWDT_MATCH
MCWDT_STRUCT[1]-MCWDT_STRUCT[0]-MCWDT_CONFIG
MCWDT_STRUCT[1]-MCWDT_STRUCT[0]-MCWDT_CTL
MCWDT_STRUCT[1]-MCWDT_STRUCT[0]-MCWDT_INTR
MCWDT_STRUCT[1]-MCWDT_STRUCT[0]-MCWDT_INTR_SET
MCWDT_STRUCT[1]-MCWDT_STRUCT[0]-MCWDT_INTR_MASK
MCWDT_STRUCT[1]-MCWDT_STRUCT[0]-MCWDT_INTR_MASKED
MCWDT_STRUCT[1]-MCWDT_STRUCT[0]-MCWDT_LOCK
Power Mode Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWER_MODE : Current power mode of the device. LPACTIVE/LPSLEEP are implemented as firmware configuration of multiple registers and are reported here as ACTIVE/SLEEP, respectively. Note that this field cannot be read in all power modes on actual silicon.
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : RESET
System is resetting.
1 : ACTIVE
At least one CPU is running.
2 : SLEEP
No CPUs are running. Peripherals may be running.
3 : DEEPSLEEP
Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present.
End of enumeration elements list.
DEBUG_SESSION : Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
0 : NO_SESSION
No debug session active
1 : SESSION_ACTIVE
Debug session is active. Power modes behave differently to keep the debug session active.
End of enumeration elements list.
LPM_READY : Indicates whether certain low power functions are ready. The low current circuits take longer to startup after POR/XRES/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers.
bits : 5 - 10 (6 bit)
access : read-only
IREF_LPMODE : Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less. 1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less.
bits : 18 - 36 (19 bit)
access : read-write
VREFBUF_OK : Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1.
bits : 19 - 38 (20 bit)
access : read-only
DPSLP_REG_DIS : Disable the DeepSleep regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: DeepSleep Regulator is on. 1: DeepSleep Regulator is off.
bits : 20 - 40 (21 bit)
access : read-write
RET_REG_DIS : Disable the Retention regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Retention Regulator is on. 1: Retention Regulator is off.
bits : 21 - 42 (22 bit)
access : read-write
NWELL_REG_DIS : Disable the Nwell regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Nwell Regulator is on. 1: Nwell Regulator is off.
bits : 22 - 44 (23 bit)
access : read-write
LINREG_DIS : Disable the linear Core Regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Linear regulator is on. 1: Linear regulator is off.
bits : 23 - 46 (24 bit)
access : read-write
LINREG_LPMODE : Control the power mode of the ULP Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: ULP Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. 1: ULP Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit.
bits : 24 - 48 (25 bit)
access : read-write
PORBOD_LPMODE : Control the power mode of the ULP POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: ULP POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: ULP POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.
bits : 25 - 50 (26 bit)
access : read-write
BGREF_LPMODE : Control the power mode of the ULP Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: ULP Active Bandgap Voltage and Current Reference operates in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: ULP Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0.
bits : 26 - 52 (27 bit)
access : read-write
PLL_LS_BYPASS : Bypass level shifter inside the PLL. 0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. 1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current.
bits : 27 - 54 (28 bit)
access : read-write
VREFBUF_LPMODE : Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: ULP Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 1: ULP Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.
bits : 28 - 56 (29 bit)
access : read-write
VREFBUF_DIS : Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
bits : 29 - 58 (30 bit)
access : read-write
ACT_REF_DIS : Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Active Reference is enabled 1: Active Reference is disabled
bits : 30 - 60 (31 bit)
access : read-write
ACT_REF_OK : Indicates that the normal mode of the Active Reference is ready.
bits : 31 - 62 (32 bit)
access : read-only
HIBERNATE Data Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
Clock Path Select Register
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
Clock Root Select Register
address_offset : 0x1198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
PLL Configuration Register
address_offset : 0x1204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
Clock DSI Select Register
address_offset : 0x1228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
PLL Status Register
address_offset : 0x12C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
Clock Path Select Register
address_offset : 0x13A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
Buck Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUCK_OUT1_SEL : Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 0.85V 1: 0.875V 2: 0.90V 3: 0.95V 4: 1.05V 5: 1.10V 6: 1.15V 7: 1.20V
bits : 0 - 2 (3 bit)
access : read-write
BUCK_EN : Master enable for buck converter. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
bits : 30 - 60 (31 bit)
access : read-write
BUCK_OUT1_EN : Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The SAS specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1.
bits : 31 - 62 (32 bit)
access : read-write
Clock Root Select Register
address_offset : 0x1528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
Clock DSI Select Register
address_offset : 0x153C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
Clock Path Select Register
address_offset : 0x16FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
Buck Control Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUCK_OUT2_SEL : Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 1.15V 1: 1.20V 2: 1.25V 3: 1.30V 4: 1.35V 5: 1.40V 6: 1.45V 7: 1.50V
bits : 0 - 2 (3 bit)
access : read-write
BUCK_OUT2_HW_SEL : Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies.
bits : 30 - 60 (31 bit)
access : read-write
BUCK_OUT2_EN : Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time.
bits : 31 - 62 (32 bit)
access : read-write
Watchdog Counter Control Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_EN : Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes.
bits : 0 - 0 (1 bit)
access : read-write
WDT_LOCK : Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes.
bits : 30 - 61 (32 bit)
access : read-write
Enumeration:
0 : NO_CHG
No effect
1 : CLR0
Clears bit 0
2 : CLR1
Clears bit 1
3 : SET01
Sets both bits 0 and 1
End of enumeration elements list.
PLL Configuration Register
address_offset : 0x180C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
HIBERNATE Data Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
Watchdog Counter Count Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled.
bits : 0 - 15 (16 bit)
access : read-write
Clock DSI Select Register
address_offset : 0x1854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
Watchdog Counter Match Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match).
bits : 0 - 15 (16 bit)
access : read-write
IGNORE_BITS : The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12.
bits : 16 - 35 (20 bit)
access : read-write
Clock Root Select Register
address_offset : 0x18BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
PLL Status Register
address_offset : 0x190C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
Clock Path Select Register
address_offset : 0x1A54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
Clock DSI Select Register
address_offset : 0x1B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
Low Voltage Detector (LVD) Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HVLVD1_OK : HVLVD1 output. 0: below voltage threshold 1: above voltage threshold
bits : 0 - 0 (1 bit)
access : read-only
Clock Root Select Register
address_offset : 0x1C54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
Clock Path Select Register
address_offset : 0x1DB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
PLL Configuration Register
address_offset : 0x1E18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
Clock DSI Select Register
address_offset : 0x1E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
PLL Status Register
address_offset : 0x1F58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
Clock Root Select Register
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
Multi-Counter Watchdog Sub-counters 0/1
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_CTR0 : Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled.
bits : 0 - 15 (16 bit)
access : read-write
WDT_CTR1 : Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled
bits : 16 - 47 (32 bit)
access : read-write
Multi-Counter Watchdog Sub-counter 2
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_CTR2 : Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled
bits : 0 - 31 (32 bit)
access : read-write
HIBERNATE Data Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
Multi-Counter Watchdog Counter Match Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_MATCH0 : Match value for sub-counter 0 of this MCWDT
bits : 0 - 15 (16 bit)
access : read-write
WDT_MATCH1 : Match value for sub-counter 1 of this MCWDT
bits : 16 - 47 (32 bit)
access : read-write
Multi-Counter Watchdog Counter Configuration
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_MODE0 : Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : NOTHING
Do nothing
1 : INT
Assert WDT_INTx
2 : RESET
Assert WDT Reset
3 : INT_THEN_RESET
Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt
End of enumeration elements list.
WDT_CLEAR0 : Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1.
bits : 2 - 4 (3 bit)
access : read-write
WDT_CASCADE0_1 : Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. 0: Independent counters 1: Cascaded counters
bits : 3 - 6 (4 bit)
access : read-write
WDT_MODE1 : Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1).
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : NOTHING
Do nothing
1 : INT
Assert WDT_INTx
2 : RESET
Assert WDT Reset
3 : INT_THEN_RESET
Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt
End of enumeration elements list.
WDT_CLEAR1 : Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1.
bits : 10 - 20 (11 bit)
access : read-write
WDT_CASCADE1_2 : Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. 0: Independent counters 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1.
bits : 11 - 22 (12 bit)
access : read-write
WDT_MODE2 : Watchdog Counter 2 Mode.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : NOTHING
Free running counter with no interrupt requests
1 : INT
Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2).
End of enumeration elements list.
WDT_BITS2 : Bit to observe for WDT_INT2: 0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) .. 31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks)
bits : 24 - 52 (29 bit)
access : read-write
Clock Path Select Register
address_offset : 0x2110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
Multi-Counter Watchdog Counter Control
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_ENABLE0 : Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
bits : 0 - 0 (1 bit)
access : read-write
WDT_ENABLED0 : Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles.
bits : 1 - 2 (2 bit)
access : read-only
WDT_RESET0 : Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.
bits : 3 - 6 (4 bit)
access : read-write
WDT_ENABLE1 : Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
bits : 8 - 16 (9 bit)
access : read-write
WDT_ENABLED1 : Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles.
bits : 9 - 18 (10 bit)
access : read-only
WDT_RESET1 : Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.
bits : 11 - 22 (12 bit)
access : read-write
WDT_ENABLE2 : Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
bits : 16 - 32 (17 bit)
access : read-write
WDT_ENABLED2 : Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles.
bits : 17 - 34 (18 bit)
access : read-only
WDT_RESET2 : Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.
bits : 19 - 38 (20 bit)
access : read-write
Multi-Counter Watchdog Counter Interrupt Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCWDT_INT0 : MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3.
bits : 0 - 0 (1 bit)
access : read-write
MCWDT_INT1 : MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3.
bits : 1 - 2 (2 bit)
access : read-write
MCWDT_INT2 : MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3.
bits : 2 - 4 (3 bit)
access : read-write
Clock DSI Select Register
address_offset : 0x21B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
Multi-Counter Watchdog Counter Interrupt Set Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCWDT_INT0 : Set interrupt for MCWDT_INT0
bits : 0 - 0 (1 bit)
access : read-write
MCWDT_INT1 : Set interrupt for MCWDT_INT1
bits : 1 - 2 (2 bit)
access : read-write
MCWDT_INT2 : Set interrupt for MCWDT_INT2
bits : 2 - 4 (3 bit)
access : read-write
Multi-Counter Watchdog Counter Interrupt Mask Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCWDT_INT0 : Mask for sub-counter 0
bits : 0 - 0 (1 bit)
access : read-write
MCWDT_INT1 : Mask for sub-counter 1
bits : 1 - 2 (2 bit)
access : read-write
MCWDT_INT2 : Mask for sub-counter 2
bits : 2 - 4 (3 bit)
access : read-write
Multi-Counter Watchdog Counter Interrupt Masked Register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MCWDT_INT0 : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
MCWDT_INT1 : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
MCWDT_INT2 : Logical and of corresponding request and mask bits.
bits : 2 - 4 (3 bit)
access : read-only
Multi-Counter Watchdog Counter Lock Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCWDT_LOCK : Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that.
bits : 30 - 61 (32 bit)
access : read-write
Enumeration:
0 : NO_CHG
No effect
1 : CLR0
Clears bit 0
2 : CLR1
Clears bit 1
3 : SET01
Sets both bits 0 and 1
End of enumeration elements list.
Clock Root Select Register
address_offset : 0x2390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
PLL Configuration Register
address_offset : 0x2428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
Clock Path Select Register
address_offset : 0x2474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
Clock DSI Select Register
address_offset : 0x24DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
PLL Status Register
address_offset : 0x25A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
Clock Root Select Register
address_offset : 0x2734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
Clock Path Select Register
address_offset : 0x27DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
Clock DSI Select Register
address_offset : 0x2808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
HIBERNATE Data Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
PLL Configuration Register
address_offset : 0x2A3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
Clock Root Select Register
address_offset : 0x2ADC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
Clock DSI Select Register
address_offset : 0x2B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
Clock Path Select Register
address_offset : 0x2B48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
PLL Status Register
address_offset : 0x2BFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
Clock DSI Select Register
address_offset : 0x2E6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
Clock Root Select Register
address_offset : 0x2E88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
Clock Path Select Register
address_offset : 0x2EB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
PLL Configuration Register
address_offset : 0x3054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
Clock DSI Select Register
address_offset : 0x31A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
Clock Path Select Register
address_offset : 0x322C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
Clock Root Select Register
address_offset : 0x3238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
PLL Status Register
address_offset : 0x3254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
HIBERNATE Data Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
Clock DSI Select Register
address_offset : 0x34E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
Clock Path Select Register
address_offset : 0x35A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
Clock Root Select Register
address_offset : 0x35EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
PLL Configuration Register
address_offset : 0x3670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
PLL Status Register
address_offset : 0x38B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
Clock Path Select Register
address_offset : 0x3920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
Clock Root Select Register
address_offset : 0x39A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
HIBERNATE Data Register
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
PLL Configuration Register
address_offset : 0x3C90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
Clock Root Select Register
address_offset : 0x3D60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
PLL Status Register
address_offset : 0x3F10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
HIBERNATE Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOKEN : Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 7 (8 bit)
access : read-write
UNLOCK : This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description.
bits : 8 - 23 (16 bit)
access : read-write
FREEZE : Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write.
bits : 17 - 34 (18 bit)
access : read-write
MASK_HIBALARM : When set, HIBERNATE will wakeup for a RTC interrupt
bits : 18 - 36 (19 bit)
access : read-write
MASK_HIBWDT : When set, HIBERNATE will wakeup if WDT matches
bits : 19 - 38 (20 bit)
access : read-write
POLARITY_HIBPIN : Each bit sets the active polarity of the corresponding wakeup pin. 0: Pin input of 0 will wakeup the part from HIBERNATE 1: Pin input of 1 will wakeup the part from HIBERNATE
bits : 20 - 43 (24 bit)
access : read-write
MASK_HIBPIN : When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins.
bits : 24 - 51 (28 bit)
access : read-write
HIBERNATE_DISABLE : Hibernate disable bit. 0: Normal operation, HIBERNATE works as described 1: Further writes to this register are ignored Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written..
bits : 30 - 60 (31 bit)
access : read-write
HIBERNATE : Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode.
bits : 31 - 62 (32 bit)
access : read-write
PLL Configuration Register
address_offset : 0x42B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
Multi-Counter Watchdog Sub-counters 0/1
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_CTR0 : Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled.
bits : 0 - 15 (16 bit)
access : read-write
WDT_CTR1 : Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled
bits : 16 - 47 (32 bit)
access : read-write
Multi-Counter Watchdog Sub-counter 2
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_CTR2 : Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled
bits : 0 - 31 (32 bit)
access : read-write
Multi-Counter Watchdog Counter Match Register
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_MATCH0 : Match value for sub-counter 0 of this MCWDT
bits : 0 - 15 (16 bit)
access : read-write
WDT_MATCH1 : Match value for sub-counter 1 of this MCWDT
bits : 16 - 47 (32 bit)
access : read-write
Multi-Counter Watchdog Counter Configuration
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_MODE0 : Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0).
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : NOTHING
Do nothing
1 : INT
Assert WDT_INTx
2 : RESET
Assert WDT Reset
3 : INT_THEN_RESET
Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt
End of enumeration elements list.
WDT_CLEAR0 : Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1.
bits : 2 - 4 (3 bit)
access : read-write
WDT_CASCADE0_1 : Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. 0: Independent counters 1: Cascaded counters
bits : 3 - 6 (4 bit)
access : read-write
WDT_MODE1 : Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1).
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : NOTHING
Do nothing
1 : INT
Assert WDT_INTx
2 : RESET
Assert WDT Reset
3 : INT_THEN_RESET
Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt
End of enumeration elements list.
WDT_CLEAR1 : Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1.
bits : 10 - 20 (11 bit)
access : read-write
WDT_CASCADE1_2 : Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. 0: Independent counters 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1.
bits : 11 - 22 (12 bit)
access : read-write
WDT_MODE2 : Watchdog Counter 2 Mode.
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
0 : NOTHING
Free running counter with no interrupt requests
1 : INT
Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2).
End of enumeration elements list.
WDT_BITS2 : Bit to observe for WDT_INT2: 0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) .. 31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks)
bits : 24 - 52 (29 bit)
access : read-write
HIBERNATE Data Register
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
Multi-Counter Watchdog Counter Control
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_ENABLE0 : Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
bits : 0 - 0 (1 bit)
access : read-write
WDT_ENABLED0 : Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles.
bits : 1 - 2 (2 bit)
access : read-only
WDT_RESET0 : Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.
bits : 3 - 6 (4 bit)
access : read-write
WDT_ENABLE1 : Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
bits : 8 - 16 (9 bit)
access : read-write
WDT_ENABLED1 : Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles.
bits : 9 - 18 (10 bit)
access : read-only
WDT_RESET1 : Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.
bits : 11 - 22 (12 bit)
access : read-write
WDT_ENABLE2 : Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
bits : 16 - 32 (17 bit)
access : read-write
WDT_ENABLED2 : Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles.
bits : 17 - 34 (18 bit)
access : read-only
WDT_RESET2 : Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.
bits : 19 - 38 (20 bit)
access : read-write
PLL Status Register
address_offset : 0x4574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
Multi-Counter Watchdog Counter Interrupt Register
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCWDT_INT0 : MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3.
bits : 0 - 0 (1 bit)
access : read-write
MCWDT_INT1 : MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3.
bits : 1 - 2 (2 bit)
access : read-write
MCWDT_INT2 : MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3.
bits : 2 - 4 (3 bit)
access : read-write
Multi-Counter Watchdog Counter Interrupt Set Register
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCWDT_INT0 : Set interrupt for MCWDT_INT0
bits : 0 - 0 (1 bit)
access : read-write
MCWDT_INT1 : Set interrupt for MCWDT_INT1
bits : 1 - 2 (2 bit)
access : read-write
MCWDT_INT2 : Set interrupt for MCWDT_INT2
bits : 2 - 4 (3 bit)
access : read-write
Multi-Counter Watchdog Counter Interrupt Mask Register
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCWDT_INT0 : Mask for sub-counter 0
bits : 0 - 0 (1 bit)
access : read-write
MCWDT_INT1 : Mask for sub-counter 1
bits : 1 - 2 (2 bit)
access : read-write
MCWDT_INT2 : Mask for sub-counter 2
bits : 2 - 4 (3 bit)
access : read-write
Multi-Counter Watchdog Counter Interrupt Masked Register
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MCWDT_INT0 : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
MCWDT_INT1 : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
MCWDT_INT2 : Logical and of corresponding request and mask bits.
bits : 2 - 4 (3 bit)
access : read-only
Multi-Counter Watchdog Counter Lock Register
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCWDT_LOCK : Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that.
bits : 30 - 61 (32 bit)
access : read-write
Enumeration:
0 : NO_CHG
No effect
1 : CLR0
Clears bit 0
2 : CLR1
Clears bit 1
3 : SET01
Sets both bits 0 and 1
End of enumeration elements list.
PLL Configuration Register
address_offset : 0x48DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
PLL Status Register
address_offset : 0x4BDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
HIBERNATE Data Register
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
PLL Configuration Register
address_offset : 0x4F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
Clock selection register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LFCLK_SEL : Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ILO
ILO - Internal Low-speed Oscillator
1 : WCO
WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used).
2 : ALTLF
ALTLF - Alternate Low-Frequency Clock. Capability is product-specific
3 : PILO
PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode.
End of enumeration elements list.
PUMP_SEL : Selects clock PATH
bits : 8 - 19 (12 bit)
access : read-write
PUMP_DIV : Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source.
bits : 12 - 26 (15 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
4 : DIV_BY_16
Divide selected clock source by 16
End of enumeration elements list.
PUMP_ENABLE : Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: 1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. 2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. 3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV.
bits : 15 - 30 (16 bit)
access : read-write
Timer Clock Control Register
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER_SEL : Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal Main Oscillator
1 : HF0_DIV
Select the output of the predivider configured by TIMER_HF0_DIV.
End of enumeration elements list.
TIMER_HF0_DIV : Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle.
1 : DIV_BY_2
Divide HFCLK0 by 2.
2 : DIV_BY_4
Divide HFCLK0 by 4.
3 : DIV_BY_8
Divide HFCLK0 by 8.
End of enumeration elements list.
TIMER_DIV : Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled.
bits : 16 - 39 (24 bit)
access : read-write
ENABLE : Enable for TIMERCLK. 0: TIMERCLK is off 1: TIMERCLK is enabled
bits : 31 - 62 (32 bit)
access : read-write
ILO Configuration
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ILO_BACKUP : If backup domain is present, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. 0: ILO turns off at XRES/BOD event or HIBERNATE entry. 1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE : Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.
bits : 31 - 62 (32 bit)
access : read-write
IMO Configuration
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during DEEPSLEEP, HIBERNATE, and XRES.
bits : 31 - 62 (32 bit)
access : read-write
Fast Clock Output Select Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAST_SEL0 : Select signal for fast clock output #0
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : NC
Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0.
1 : ECO
External Crystal Oscillator (ECO)
2 : EXTCLK
External clock input (EXTCLK)
3 : ALTHF
Alternate High-Frequency (ALTHF) clock input to SRSS
4 : TIMERCLK
Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.
5 : PATH_SEL0
Selects the clock path chosen by PATH_SEL0 field
6 : HFCLK_SEL0
Selects the output of the HFCLK_SEL0 mux
7 : SLOW_SEL0
Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0
End of enumeration elements list.
PATH_SEL0 : Selects a clock path to use in fast clock output #0 logic. For FLL path, it connects after the bypass mux. For PLL path(s), it connects after the CLK_PLL_DDFT mux. 0: FLL output 1-15: PLL output on path1-path15 (if available)
bits : 4 - 11 (8 bit)
access : read-write
HFCLK_SEL0 : Selects a HFCLK tree for use in fast clock output #0
bits : 8 - 19 (12 bit)
access : read-write
FAST_SEL1 : Select signal for fast clock output #1
bits : 16 - 35 (20 bit)
access : read-write
Enumeration:
0 : NC
Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1.
1 : ECO
External Crystal Oscillator (ECO)
2 : EXTCLK
External clock input (EXTCLK)
3 : ALTHF
Alternate High-Frequency (ALTHF) clock input to SRSS
4 : TIMERCLK
Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.
5 : PATH_SEL1
Selects the clock path chosen by PATH_SEL1 field
6 : HFCLK_SEL1
Selects the output of the HFCLK_SEL1 mux
7 : SLOW_SEL1
Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1
End of enumeration elements list.
PATH_SEL1 : Selects a clock path to use in fast clock output #1 logic. For FLL path, it connects after the bypass mux. For PLL path(s), it connects after the CLK_PLL_DDFT mux. 1-15: PLL output on path1-path15 (if available)
bits : 20 - 43 (24 bit)
access : read-write
HFCLK_SEL1 : Selects a HFCLK tree for use in fast clock output #1 logic
bits : 24 - 51 (28 bit)
access : read-write
Slow Clock Output Select Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_SEL0 : Select signal for slow clock output #0
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : NC
Disabled - output is 0. For power savings, clocks are blocked before entering any muxes.
1 : ILO
Internal Low Speed Oscillator (ILO)
2 : WCO
Watch-Crystal Oscillator (WCO)
3 : BAK
Root of the Backup domain clock tree (BAK)
4 : ALTLF
Alternate low-frequency clock input to SRSS (ALTLF)
5 : LFCLK
Root of the low-speed clock tree (LFCLK)
6 : IMO
Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
7 : SLPCTRL
Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
8 : PILO
Precision Internal Low Speed Oscillator (PILO)
End of enumeration elements list.
SLOW_SEL1 : Select signal for slow clock output #1
bits : 4 - 11 (8 bit)
access : read-write
Enumeration:
0 : NC
Disabled - output is 0. For power savings, clocks are blocked before entering any muxes.
1 : ILO
Internal Low Speed Oscillator (ILO)
2 : WCO
Watch-Crystal Oscillator (WCO)
3 : BAK
Root of the Backup domain clock tree (BAK)
4 : ALTLF
Alternate low-frequency clock input to SRSS (ALTLF)
5 : LFCLK
Root of the low-speed clock tree (LFCLK)
6 : IMO
Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
7 : SLPCTRL
Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
8 : PILO
Precision Internal Low Speed Oscillator (PILO)
End of enumeration elements list.
Clock Calibration Counter 1
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_COUNTER1 : Down-counter clocked on fast DDFT output #0 (see TST_DDFT_FAST_CTL). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1.
bits : 0 - 23 (24 bit)
access : read-write
CAL_COUNTER_DONE : Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up
bits : 31 - 62 (32 bit)
access : read-only
Clock Calibration Counter 2
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAL_COUNTER2 : Up-counter clocked on fast DDFT output #1 (see TST_DDFT_FAST_CTL). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER)
bits : 0 - 23 (24 bit)
access : read-only
PLL Status Register
address_offset : 0x5248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
ECO Configuration Register
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC_EN : Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and will grow until it saturates to the supply rail (1.8V nom). WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal.
bits : 1 - 2 (2 bit)
access : read-write
ECO_EN : Master enable for ECO oscillator.
bits : 31 - 62 (32 bit)
access : read-write
ECO Status Register
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ECO_OK : Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec.
bits : 0 - 0 (1 bit)
access : read-only
ECO_READY : Indicates the ECO internal oscillator circuit has fully stabilized.
bits : 1 - 2 (2 bit)
access : read-only
Precision ILO Configuration Register
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PILO_FFREQ : Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz.
bits : 0 - 9 (10 bit)
access : read-write
PILO_CLK_EN : Enable the PILO clock output. See PILO_EN field for required sequencing.
bits : 29 - 58 (30 bit)
access : read-write
PILO_RESET_N : Reset the PILO. See PILO_EN field for required sequencing.
bits : 30 - 60 (31 bit)
access : read-write
PILO_EN : Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle.
bits : 31 - 62 (32 bit)
access : read-write
PLL Configuration Register
address_offset : 0x5538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
FLL Configuration Register
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLL_MULT : Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1)
bits : 0 - 17 (18 bit)
access : read-write
FLL_OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: no division 1: divide by 2
bits : 24 - 48 (25 bit)
access : read-write
FLL_ENABLE : Master enable for FLL. Do not enable until the reference clock has stabilized. 0: Block is powered off 1: Block is powered on
bits : 31 - 62 (32 bit)
access : read-write
FLL Configuration Register 2
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLL_REF_DIV : Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 8191: divide by 8191
bits : 0 - 12 (13 bit)
access : read-write
LOCK_TOL : Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. 0: tolerate error of 1 count value 1: tolerate error of 2 count values ... 511: tolerate error of 512 count values
bits : 16 - 40 (25 bit)
access : read-write
FLL Configuration Register 3
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLL_LF_IGAIN : FLL Loop Filter Integral Gain Setting 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal
bits : 0 - 3 (4 bit)
access : read-write
FLL_LF_PGAIN : FLL Loop Filter Proportional Gain Setting 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal
bits : 4 - 11 (8 bit)
access : read-write
SETTLING_COUNT : Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. 0: no settling time 1: wait one reference clock cycle ... 8191: wait 8191 reference clock cycles
bits : 8 - 28 (21 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after FLL output.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects FLL reference input (bypass mode). When locked, automatically selects FLL output.
1 : AUTO1
Same as AUTO
2 : FLL_REF
Select FLL reference input (bypass mode). Ignores lock indicator
3 : FLL_OUT
Select FLL output. Ignores lock indicator.
End of enumeration elements list.
PLL Status Register
address_offset : 0x58B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
FLL Configuration Register 4
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCO_LIMIT : Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)
bits : 0 - 7 (8 bit)
access : read-write
CCO_RANGE : Frequency range of CCO
bits : 8 - 18 (11 bit)
access : read-write
Enumeration:
0 : RANGE0
Target frequency is in range [48, 64) MHz
1 : RANGE1
Target frequency is in range [64, 85) MHz
2 : RANGE2
Target frequency is in range [85, 113) MHz
3 : RANGE3
Target frequency is in range [113, 150) MHz
4 : RANGE4
Target frequency is in range [150, 200] MHz
End of enumeration elements list.
CCO_FREQ : CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range.
bits : 16 - 40 (25 bit)
access : read-write
CCO_HW_UPDATE_DIS : Disable CCO frequency update by FLL hardware 0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. 1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation.
bits : 30 - 60 (31 bit)
access : read-write
CCO_ENABLE : Enable the CCO. It is required to enable the CCO before using the FLL. 0: Block is powered off 1: Block is powered on
bits : 31 - 62 (32 bit)
access : read-write
HIBERNATE Data Register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
FLL Status Register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : FLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : N/A
bits : 1 - 2 (2 bit)
access : read-write
CCO_READY : This indicates that the CCO is internally settled and ready to use.
bits : 2 - 4 (3 bit)
access : read-only
PLL Configuration Register
address_offset : 0x5B6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
PLL Status Register
address_offset : 0x5F2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
Clock DSI Select Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
PLL Configuration Register
address_offset : 0x61A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
HIBERNATE Data Register
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
PLL Status Register
address_offset : 0x65A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
Clock Path Select Register
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
HIBERNATE Data Register
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
Clock Root Select Register
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
SRSS Interrupt Register
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_MATCH : WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C.
bits : 0 - 0 (1 bit)
access : read-write
HVLVD1 : Interrupt for low voltage detector HVLVD1
bits : 1 - 2 (2 bit)
access : read-write
CLK_CAL : Clock calibration counter is done
bits : 5 - 10 (6 bit)
access : read-write
SRSS Interrupt Set Register
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_MATCH : Set interrupt for low voltage detector WDT_MATCH
bits : 0 - 0 (1 bit)
access : read-write
HVLVD1 : Set interrupt for low voltage detector HVLVD1
bits : 1 - 2 (2 bit)
access : read-write
CLK_CAL : Set interrupt for clock calibration counter done
bits : 5 - 10 (6 bit)
access : read-write
SRSS Interrupt Mask Register
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_MATCH : Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts.
bits : 0 - 0 (1 bit)
access : read-write
HVLVD1 : Mask for low voltage detector HVLVD1
bits : 1 - 2 (2 bit)
access : read-write
CLK_CAL : Mask for clock calibration done
bits : 5 - 10 (6 bit)
access : read-write
SRSS Interrupt Masked Register
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDT_MATCH : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
HVLVD1 : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
CLK_CAL : Logical and of corresponding request and mask bits.
bits : 5 - 10 (6 bit)
access : read-only
SRSS Interrupt Configuration Register
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HVLVD1_EDGE_SEL : Sets which edge(s) will trigger an IRQ for HVLVD1
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
HIBERNATE Data Register
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
Reference Trim Register
address_offset : 0x7F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT_REF_TCTRIM : Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range
bits : 0 - 3 (4 bit)
access : read-write
ACT_REF_ITRIM : Active-Reference current trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range
bits : 4 - 11 (8 bit)
access : read-write
ACT_REF_ABSTRIM : Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range
bits : 8 - 20 (13 bit)
access : read-write
ACT_REF_IBOOST : Active-Reference current boost. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: normal operation others: risk mitigation
bits : 14 - 28 (15 bit)
access : read-write
DPSLP_REF_TCTRIM : DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range
bits : 16 - 35 (20 bit)
access : read-write
DPSLP_REF_ABSTRIM : DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
bits : 20 - 44 (25 bit)
access : read-write
DPSLP_REF_ITRIM : DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
bits : 28 - 59 (32 bit)
access : read-write
BOD/OVP Trim Register
address_offset : 0x7F04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HVPORBOD_TRIPSEL : HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
bits : 0 - 2 (3 bit)
access : read-write
HVPORBOD_OFSTRIM : HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
bits : 4 - 10 (7 bit)
access : read-write
HVPORBOD_ITRIM : HVPORBOD current trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
bits : 7 - 16 (10 bit)
access : read-write
LVPORBOD_TRIPSEL : LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
bits : 10 - 22 (13 bit)
access : read-write
LVPORBOD_OFSTRIM : LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
bits : 14 - 30 (17 bit)
access : read-write
LVPORBOD_ITRIM : LVPORBOD current trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
bits : 17 - 36 (20 bit)
access : read-write
CCO Trim Register
address_offset : 0x7F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCO_RCSTRIM : CCO reference current source trim.
bits : 0 - 5 (6 bit)
access : read-write
CCO_STABLE_CNT : Terminal count for the stabilization counter from CCO_ENABLE until stable.
bits : 24 - 53 (30 bit)
access : read-write
ENABLE_CNT : Enables the automatic stabilization counter.
bits : 31 - 62 (32 bit)
access : read-write
CCO Trim Register 2
address_offset : 0x7F0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCO_FCTRIM1 : CCO frequency 1st range calibration
bits : 0 - 4 (5 bit)
access : read-write
CCO_FCTRIM2 : CCO frequency 2nd range calibration
bits : 5 - 14 (10 bit)
access : read-write
CCO_FCTRIM3 : CCO frequency 3rd range calibration
bits : 10 - 24 (15 bit)
access : read-write
CCO_FCTRIM4 : CCO frequency 4th range calibration
bits : 15 - 34 (20 bit)
access : read-write
CCO_FCTRIM5 : CCO frequency 5th range calibration
bits : 20 - 44 (25 bit)
access : read-write
Wakeup Trim Register
address_offset : 0x7F30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKE_DELAY : Wakeup holdoff. Spec (fastest) wake time is achieve with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO.
bits : 0 - 7 (8 bit)
access : read-write
Low Voltage Detector (LVD) Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HVLVD1_TRIPSEL : Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. 0: rise=1.225V (nom), fall=1.2V (nom) 1: rise=1.425V (nom), fall=1.4V (nom) 2: rise=1.625V (nom), fall=1.6V (nom) 3: rise=1.825V (nom), fall=1.8V (nom) 4: rise=2.025V (nom), fall=2V (nom) 5: rise=2.125V (nom), fall=2.1V (nom) 6: rise=2.225V (nom), fall=2.2V (nom) 7: rise=2.325V (nom), fall=2.3V (nom) 8: rise=2.425V (nom), fall=2.4V (nom) 9: rise=2.525V (nom), fall=2.5V (nom) 10: rise=2.625V (nom), fall=2.6V (nom) 11: rise=2.725V (nom), fall=2.7V (nom) 12: rise=2.825V (nom), fall=2.8V (nom) 13: rise=2.925V (nom), fall=2.9V (nom) 14: rise=3.025V (nom), fall=3.0V (nom) 15: rise=3.125V (nom), fall=3.1V (nom)
bits : 0 - 3 (4 bit)
access : read-write
HVLVD1_SRCSEL : Source selection for HVLVD1
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : VDDD
Select VDDD
1 : AMUXBUSA
Select AMUXBUSA (VDDD branch)
2 : RSVD
N/A
3 : VDDIO
N/A
4 : AMUXBUSB
Select AMUXBUSB (VDDD branch)
End of enumeration elements list.
HVLVD1_EN : Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it further recommended to read the realted PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup.
bits : 7 - 14 (8 bit)
access : read-write
Reset Cause Observation Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET_WDT : A basic WatchDog Timer (WDT) reset has occurred since last power cycle.
bits : 0 - 0 (1 bit)
access : read-write
RESET_ACT_FAULT : Fault logging system requested a reset from its Active logic.
bits : 1 - 2 (2 bit)
access : read-write
RESET_DPSLP_FAULT : Fault logging system requested a reset from its DeepSleep logic.
bits : 2 - 4 (3 bit)
access : read-write
RESET_CSV_WCO_LOSS : Clock supervision logic requested a reset due to loss of a watch-crystal clock.
bits : 3 - 6 (4 bit)
access : read-write
RESET_SOFT : A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware.
bits : 4 - 8 (5 bit)
access : read-write
RESET_MCWDT0 : Multi-Counter Watchdog timer reset #0 has occurred since last power cycle.
bits : 5 - 10 (6 bit)
access : read-write
RESET_MCWDT1 : Multi-Counter Watchdog timer reset #1 has occurred since last power cycle.
bits : 6 - 12 (7 bit)
access : read-write
RESET_MCWDT2 : Multi-Counter Watchdog timer reset #2 has occurred since last power cycle.
bits : 7 - 14 (8 bit)
access : read-write
RESET_MCWDT3 : Multi-Counter Watchdog timer reset #3 has occurred since last power cycle.
bits : 8 - 16 (9 bit)
access : read-write
Reset Cause Observation Register 2
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET_CSV_HF_LOSS : Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK
bits : 0 - 15 (16 bit)
access : read-write
RESET_CSV_HF_FREQ : Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK
bits : 16 - 47 (32 bit)
access : read-write
HIBERNATE Data Register
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
HIBERNATE Data Register
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
Clock DSI Select Register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
HIBERNATE Data Register
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
Clock Path Select Register
address_offset : 0x9C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
HIBERNATE Data Register
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIB_DATA : Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
bits : 0 - 31 (32 bit)
access : read-write
Clock Root Select Register
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
PLL Configuration Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACK_DIV : Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
bits : 0 - 6 (7 bit)
access : read-write
REFERENCE_DIV : Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
bits : 8 - 20 (13 bit)
access : read-write
OUTPUT_DIV : Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
bits : 16 - 36 (21 bit)
access : read-write
PLL_LF_MODE : VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
bits : 27 - 54 (28 bit)
access : read-write
BYPASS_SEL : Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
1 : AUTO1
Same as AUTO
2 : PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
3 : PLL_OUT
Select PLL output. Ignores lock indicator.
End of enumeration elements list.
ENABLE : Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
bits : 31 - 62 (32 bit)
access : read-write
Clock DSI Select Register
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
PLL Status Register
address_offset : 0xC80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : PLL Lock Indicator
bits : 0 - 0 (1 bit)
access : read-only
UNLOCK_OCCURRED : This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
bits : 1 - 2 (2 bit)
access : read-write
Clock Path Select Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PATH_MUX : Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : IMO
IMO - Internal R/C Oscillator
1 : EXTCLK
EXTCLK - External Clock Pin
2 : ECO
ECO - External-Crystal Oscillator
3 : ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
4 : DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
End of enumeration elements list.
Clock Root Select Register
address_offset : 0xE0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROOT_MUX : Selects a clock path as the root of HFCLK
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : PATH0
Select PATH0 (can be configured for FLL)
1 : PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
2 : PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
3 : PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
4 : PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
5 : PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
6 : PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
7 : PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
8 : PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
9 : PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
10 : PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
11 : PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
12 : PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
13 : PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
14 : PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
15 : PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
End of enumeration elements list.
ROOT_DIV : Selects predivider value for this clock root and DSI input.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
1 : DIV_BY_2
Divide selected clock source by 2
2 : DIV_BY_4
Divide selected clock source by 4
3 : DIV_BY_8
Divide selected clock source by 8
End of enumeration elements list.
ENABLE : Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
bits : 31 - 62 (32 bit)
access : read-write
Clock DSI Select Register
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSI_MUX : Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DSI_OUT0
DSI0 - dsi_out[0]
1 : DSI_OUT1
DSI1 - dsi_out[1]
2 : DSI_OUT2
DSI2 - dsi_out[2]
3 : DSI_OUT3
DSI3 - dsi_out[3]
4 : DSI_OUT4
DSI4 - dsi_out[4]
5 : DSI_OUT5
DSI5 - dsi_out[5]
6 : DSI_OUT6
DSI6 - dsi_out[6]
7 : DSI_OUT7
DSI7 - dsi_out[7]
8 : DSI_OUT8
DSI8 - dsi_out[8]
9 : DSI_OUT9
DSI9 - dsi_out[9]
10 : DSI_OUT10
DSI10 - dsi_out[10]
11 : DSI_OUT11
DSI11 - dsi_out[11]
12 : DSI_OUT12
DSI12 - dsi_out[12]
13 : DSI_OUT13
DSI13 - dsi_out[13]
14 : DSI_OUT14
DSI14 - dsi_out[14]
15 : DSI_OUT15
DSI15 - dsi_out[15]
16 : ILO
ILO - Internal Low-speed Oscillator
17 : WCO
WCO - Watch-Crystal Oscillator
18 : ALTLF
ALTLF - Alternate Low-Frequency Clock
19 : PILO
PILO - Precision Internal Low-speed Oscillator
End of enumeration elements list.
LVD Trim Register
address_offset : 0xFF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HVLVD1_OFSTRIM : HVLVD1 offset trim
bits : 0 - 2 (3 bit)
access : read-write
HVLVD1_ITRIM : HVLVD1 current trim
bits : 4 - 10 (7 bit)
access : read-write
ILO Trim Register
address_offset : 0xFF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ILO_FTRIM : ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency.
bits : 0 - 5 (6 bit)
access : read-write
Power System Trim Register
address_offset : 0xFF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT_REG_TRIM : Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula: 5'h07: 900mV (nominal) 5'h17: 1100mV (nominal)
bits : 0 - 4 (5 bit)
access : read-write
ACT_REG_BOOST : Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: 2'b00: 50uA 2'b01: 100uA 2'b10: 150uA 2'b11: 200uA The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. 50mA chip: 2'b00 (default); 100mA chip: 2'b00 (default); 150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); 200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); 250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); 300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
bits : 30 - 61 (32 bit)
access : read-write
ECO Trim Register
address_offset : 0xFF20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTRIM : Watch Dog Trim - Delta voltage below stead state level 0x0 - 50mV 0x1 - 75mV 0x2 - 100mV 0x3 - 125mV 0x4 - 150mV 0x5 - 175mV 0x6 - 200mV 0x7 - 225mV
bits : 0 - 2 (3 bit)
access : read-write
ATRIM : Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. 0x0 - 150mV 0x1 - 175mV 0x2 - 200mV 0x3 - 225mV 0x4 - 250mV 0x5 - 275mV 0x6 - 300mV 0x7 - 325mV 0x8 - 350mV 0x9 - 375mV 0xA - 400mV 0xB - 425mV 0xC - 450mV 0xD - 475mV 0xE - 500mV 0xF - 525mV
bits : 4 - 11 (8 bit)
access : read-write
FTRIM : Filter Trim - 3rd harmonic oscillation
bits : 8 - 17 (10 bit)
access : read-write
RTRIM : Feedback resistor Trim
bits : 10 - 21 (12 bit)
access : read-write
GTRIM : Gain Trim - Startup time
bits : 12 - 25 (14 bit)
access : read-write
ITRIM : Current Trim
bits : 16 - 37 (22 bit)
access : read-write
PILO Trim Register
address_offset : 0xFF24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PILO_CFREQ : Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz.
bits : 0 - 5 (6 bit)
access : read-write
PILO_OSC_TRIM : Trim for current in oscillator block.
bits : 12 - 26 (15 bit)
access : read-write
PILO_COMP_TRIM : Trim for comparator bias current.
bits : 16 - 33 (18 bit)
access : read-write
PILO_NBIAS_TRIM : Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier
bits : 18 - 37 (20 bit)
access : read-write
PILO_RES_TRIM : Trim for beta-multiplier branch current
bits : 20 - 44 (25 bit)
access : read-write
PILO_ISLOPE_TRIM : Trim for beta-multiplier current slope
bits : 26 - 53 (28 bit)
access : read-write
PILO_VTDIFF_TRIM : Trim for VT-DIFF output (internal power supply)
bits : 28 - 58 (31 bit)
access : read-write
PILO Trim Register 2
address_offset : 0xFF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PILO_VREF_TRIM : Trim for voltage reference
bits : 0 - 7 (8 bit)
access : read-write
PILO_IREFBM_TRIM : Trim for beta-multiplier current reference
bits : 8 - 20 (13 bit)
access : read-write
PILO_IREF_TRIM : Trim for current reference
bits : 16 - 39 (24 bit)
access : read-write
PILO Trim Register 3
address_offset : 0xFF2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PILO_ENGOPT : Engineering options for PILO circuits 0: Short vdda to vpwr 1: Beta:mult current change 2: Iref generation Ptat current addition 3: Disable current path in secondary Beta:mult startup circuit 4: Double oscillator current 5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block 6: Spare 7: Ptat component increase in Iref 8: vpwr_rc and vpwr_dig_rc shorting testmode 9: Switch b/w psub connection for cascode nfet for vref generation 10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. 15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy.
bits : 0 - 15 (16 bit)
access : read-write
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