Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
CH_STRUCT[1]-CH_STRUCT[0]-CH_CTL
CH_STRUCT[1]-CH_STRUCT[0]-CH_STATUS
CH_STRUCT[1]-CH_STRUCT[0]-CH_IDX
CH_STRUCT[1]-CH_STRUCT[0]-CH_CURR_PTR
CH_STRUCT[1]-CH_STRUCT[0]-INTR
CH_STRUCT[1]-CH_STRUCT[0]-INTR_SET
CH_STRUCT[1]-CH_STRUCT[0]-INTR_MASK
CH_STRUCT[1]-CH_STRUCT[0]-INTR_MASKED
CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_CTL
CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_STATUS
CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_IDX
CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_CURR_PTR
CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR
CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_SET
CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_MASK
CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_MASKED
CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_CTL
CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_STATUS
CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_IDX
CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_CURR_PTR
CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR
CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_SET
CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_MASK
CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_MASKED
CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_CTL
CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_STATUS
CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_IDX
CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_CURR_PTR
CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR
CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_SET
CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_MASK
CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_MASKED
CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_CTL
CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_STATUS
CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_IDX
CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_CURR_PTR
CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR
CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_SET
CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_MASK
CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_MASKED
CH_STRUCT[6]-CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_CTL
CH_STRUCT[6]-CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_STATUS
CH_STRUCT[6]-CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-CH_IDX
CH_STRUCT[6]-CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR
CH_STRUCT[6]-CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_SET
CH_STRUCT[6]-CH_STRUCT[5]-CH_STRUCT[4]-CH_STRUCT[3]-CH_STRUCT[2]-CH_STRUCT[1]-CH_STRUCT[0]-INTR_MASK
Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLED : IP enable: '0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
System interrupt control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Reflects the INTR.CH bit fields of all channels.
bits : 0 - 31 (32 bit)
access : read-only
Channel control
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x102C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x1034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x103C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Status of interrupts masked
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Reflects the INTR_MASKED.CH bit fields of all channels.
bits : 0 - 31 (32 bit)
access : read-only
Channel control
address_offset : 0x1860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x1864 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x1868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x186C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x1870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x1874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x1878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x187C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Active descriptor control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Copy of DESCR_CTL of the currently active descriptor.
bits : 0 - 31 (32 bit)
access : read-only
Channel control
address_offset : 0x20C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x20C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x20C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x20CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x20D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x20D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x20D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x20DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Active descriptor source
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Copy of DESCR_SRC of the currently active descriptor.
bits : 0 - 31 (32 bit)
access : read-only
Active descriptor destination
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Copy of DESCR_DST of the currently active descriptor.
bits : 0 - 31 (32 bit)
access : read-only
Channel control
address_offset : 0x2940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x2944 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x2948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x294C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x2950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x2954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x2958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x295C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Active descriptor X loop control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Copy of DESCR_X_CTL of the currently active descriptor.
bits : 0 - 31 (32 bit)
access : read-only
Channel control
address_offset : 0x31E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x31E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x31E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x31EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x31F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x31F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x31F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x31FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Active descriptor Y loop control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Copy of DESCR_Y_CTL of the currently active descriptor.
bits : 0 - 31 (32 bit)
access : read-only
Active descriptor next pointer
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Copy of DESCR_NEXT_PTR of the currently active descriptor.
bits : 2 - 33 (32 bit)
access : read-only
Channel control
address_offset : 0x3AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x3AA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x3AA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x3AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x3AB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x3AB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x3AB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x3ABC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : Active channel, user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : Active channel, secure/non-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
B : Active channel, non-bufferable/bufferable access control: '0': non-bufferable '1': bufferable.
bits : 2 - 4 (3 bit)
access : read-only
PC : Active channel protection context.
bits : 4 - 11 (8 bit)
access : read-only
CH_IDX : Active channel index.
bits : 8 - 20 (13 bit)
access : read-only
PRIO : Active channel priority.
bits : 16 - 33 (18 bit)
access : read-only
PREEMPTABLE : Active channel preemptable.
bits : 18 - 36 (19 bit)
access : read-only
STATE : State of the DW controller. '0': Default/inactive state. '1': Loading descriptor. '2': Loading data element from source location. '3': Storing data element to destination location. '4': Update of active control information (e.g. source and destination addresses). '5': Wait for trigger de-activation.
bits : 20 - 42 (23 bit)
access : read-only
ACTIVE : Active channel present: '0': No. '1': Yes.
bits : 31 - 62 (32 bit)
access : read-only
Active source
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRC_ADDR : Current address of source location.
bits : 0 - 31 (32 bit)
access : read-only
Channel control
address_offset : 0x4380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x4384 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x4388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x438C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x4390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x4394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x4398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x439C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Active destination
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DST_ADDR : Current address of destination location.
bits : 0 - 31 (32 bit)
access : read-only
Channel control
address_offset : 0x4C80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x4C84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x4C88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x4C8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x4C90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x4C94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x4C98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x4C9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Channel control
address_offset : 0x55A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x55A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x55A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x55AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x55B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x55B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x55B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x55BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Channel control
address_offset : 0x5EE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x5EE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x5EE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x5EEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x5EF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x5EF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x5EF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x5EFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Channel control
address_offset : 0x6840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x6844 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x6848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x684C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x6850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x6854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x6858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x685C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Channel control
address_offset : 0x71C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x71C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x71C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x71CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x71D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x71D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x71D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x71DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Channel control
address_offset : 0x7B60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x7B64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x7B68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x7B6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x7B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x7B74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x7B78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x7B7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Pending channels
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH_PENDING : Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)).
bits : 0 - 31 (32 bit)
access : read-only
Channel control
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Channel control
address_offset : 0x8520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x8524 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x8528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x852C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x8530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x8534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x8538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x853C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
Channel control
address_offset : 0x8F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').
bits : 0 - 0 (1 bit)
access : read-write
NS : Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').
bits : 1 - 2 (2 bit)
access : read-write
B : Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').
bits : 2 - 4 (3 bit)
access : read-write
PC : Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context.
bits : 4 - 11 (8 bit)
access : read-write
PRIO : Channel priority: '0': highest priority. '1' '2' '3': lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, roundrobin arbitration is applied. Roundrobin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).
bits : 16 - 33 (18 bit)
access : read-write
PREEMPTABLE : Specifies if the channel is preemptable. '0': Not preemptable. '1': Preemptable. This field allows higher priority pending channels (from a higer priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.
bits : 18 - 36 (19 bit)
access : read-write
ENABLED : Channel enable: '0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pensding channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). '1': Enabled. SW sets this field to '1' to enable a specific channel. HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).
bits : 31 - 62 (32 bit)
access : read-write
Channel status
address_offset : 0x8F04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR_CAUSE : Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '1', '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').
bits : 0 - 3 (4 bit)
access : read-only
Channel current indices
address_offset : 0x8F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X_IDX : Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 0 - 7 (8 bit)
access : read-write
Y_IDX : Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to '0' when it updates CH_CURR_PTR.
bits : 8 - 23 (16 bit)
access : read-write
Channel current descriptor pointer
address_offset : 0x8F0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of current descriptor. When this field is '0', there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.
bits : 2 - 33 (32 bit)
access : read-write
Interrupt
address_offset : 0x8F10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt set
address_offset : 0x8F14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write
Interrupt mask
address_offset : 0x8F18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt masked
address_offset : 0x8F1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH : Logical and of corresponding INTR and INTR_MASK fields.
bits : 0 - 0 (1 bit)
access : read-only
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