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HSIOM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PRT[0]-PORT_SEL0

PRT[1]-PRT[0]-PORT_SEL0

AMUX_SPLIT_CTL[6]

AMUX_SPLIT_CTL[7]

PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[8]

PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[9]

AMUX_SPLIT_CTL[10]

AMUX_SPLIT_CTL[11]

PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

AMUX_SPLIT_CTL[12]

PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[13]

AMUX_SPLIT_CTL[14]

AMUX_SPLIT_CTL[15]

PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

AMUX_SPLIT_CTL[16]

PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[17]

AMUX_SPLIT_CTL[18]

AMUX_SPLIT_CTL[19]

AMUX_SPLIT_CTL[20]

PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[21]

PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

AMUX_SPLIT_CTL[22]

AMUX_SPLIT_CTL[23]

PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[24]

AMUX_SPLIT_CTL[25]

PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[26]

AMUX_SPLIT_CTL[27]

AMUX_SPLIT_CTL[28]

AMUX_SPLIT_CTL[29]

PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[0]

AMUX_SPLIT_CTL[30]

PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[31]

AMUX_SPLIT_CTL[32]

AMUX_SPLIT_CTL[33]

AMUX_SPLIT_CTL[34]

AMUX_SPLIT_CTL[35]

AMUX_SPLIT_CTL[36]

PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[37]

AMUX_SPLIT_CTL[38]

AMUX_SPLIT_CTL[39]

AMUX_SPLIT_CTL[40]

AMUX_SPLIT_CTL[41]

AMUX_SPLIT_CTL[42]

AMUX_SPLIT_CTL[43]

PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[44]

AMUX_SPLIT_CTL[45]

PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

AMUX_SPLIT_CTL[1]

AMUX_SPLIT_CTL[46]

AMUX_SPLIT_CTL[47]

PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[48]

AMUX_SPLIT_CTL[49]

PRT[14]-PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

AMUX_SPLIT_CTL[50]

PRT[14]-PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[51]

AMUX_SPLIT_CTL[52]

AMUX_SPLIT_CTL[53]

AMUX_SPLIT_CTL[54]

AMUX_SPLIT_CTL[55]

AMUX_SPLIT_CTL[56]

AMUX_SPLIT_CTL[57]

AMUX_SPLIT_CTL[58]

AMUX_SPLIT_CTL[59]

AMUX_SPLIT_CTL[60]

AMUX_SPLIT_CTL[61]

AMUX_SPLIT_CTL[2]

AMUX_SPLIT_CTL[62]

AMUX_SPLIT_CTL[63]

PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

AMUX_SPLIT_CTL[3]

PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

AMUX_SPLIT_CTL[4]

AMUX_SPLIT_CTL[5]

PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1


PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[0]-PORT_SEL0 PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[1]-PRT[0]-PORT_SEL0 PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[6]

AMUX splitter cell control
address_offset : 0x10054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[6] AMUX_SPLIT_CTL[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[7]

AMUX splitter cell control
address_offset : 0x12070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[7] AMUX_SPLIT_CTL[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[1]-PRT[0]-PORT_SEL1 PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[8]

AMUX splitter cell control
address_offset : 0x14090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[8] AMUX_SPLIT_CTL[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[9]

AMUX splitter cell control
address_offset : 0x160B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[9] AMUX_SPLIT_CTL[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[10]

AMUX splitter cell control
address_offset : 0x180DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[10] AMUX_SPLIT_CTL[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[11]

AMUX splitter cell control
address_offset : 0x1A108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[11] AMUX_SPLIT_CTL[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[12]

AMUX splitter cell control
address_offset : 0x1C138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[12] AMUX_SPLIT_CTL[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[13]

AMUX splitter cell control
address_offset : 0x1E16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[13] AMUX_SPLIT_CTL[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[14]

AMUX splitter cell control
address_offset : 0x201A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[14] AMUX_SPLIT_CTL[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[15]

AMUX splitter cell control
address_offset : 0x221E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[15] AMUX_SPLIT_CTL[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[16]

AMUX splitter cell control
address_offset : 0x24220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[16] AMUX_SPLIT_CTL[16] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[17]

AMUX splitter cell control
address_offset : 0x26264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[17] AMUX_SPLIT_CTL[17] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[18]

AMUX splitter cell control
address_offset : 0x282AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[18] AMUX_SPLIT_CTL[18] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[19]

AMUX splitter cell control
address_offset : 0x2A2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[19] AMUX_SPLIT_CTL[19] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[20]

AMUX splitter cell control
address_offset : 0x2C348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[20] AMUX_SPLIT_CTL[20] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[21]

AMUX splitter cell control
address_offset : 0x2E39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[21] AMUX_SPLIT_CTL[21] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[22]

AMUX splitter cell control
address_offset : 0x303F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[22] AMUX_SPLIT_CTL[22] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[23]

AMUX splitter cell control
address_offset : 0x32450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[23] AMUX_SPLIT_CTL[23] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[24]

AMUX splitter cell control
address_offset : 0x344B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[24] AMUX_SPLIT_CTL[24] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[25]

AMUX splitter cell control
address_offset : 0x36514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[25] AMUX_SPLIT_CTL[25] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[26]

AMUX splitter cell control
address_offset : 0x3857C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[26] AMUX_SPLIT_CTL[26] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[27]

AMUX splitter cell control
address_offset : 0x3A5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[27] AMUX_SPLIT_CTL[27] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[28]

AMUX splitter cell control
address_offset : 0x3C658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[28] AMUX_SPLIT_CTL[28] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[29]

AMUX splitter cell control
address_offset : 0x3E6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[29] AMUX_SPLIT_CTL[29] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[0]-PORT_SEL1 PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[0]

AMUX splitter cell control
address_offset : 0x4000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[0] AMUX_SPLIT_CTL[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[30]

AMUX splitter cell control
address_offset : 0x40744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[30] AMUX_SPLIT_CTL[30] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[31]

AMUX splitter cell control
address_offset : 0x427C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[31] AMUX_SPLIT_CTL[31] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[32]

AMUX splitter cell control
address_offset : 0x44840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[32] AMUX_SPLIT_CTL[32] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[33]

AMUX splitter cell control
address_offset : 0x468C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[33] AMUX_SPLIT_CTL[33] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[34]

AMUX splitter cell control
address_offset : 0x4894C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[34] AMUX_SPLIT_CTL[34] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[35]

AMUX splitter cell control
address_offset : 0x4A9D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[35] AMUX_SPLIT_CTL[35] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[36]

AMUX splitter cell control
address_offset : 0x4CA68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[36] AMUX_SPLIT_CTL[36] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[37]

AMUX splitter cell control
address_offset : 0x4EAFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[37] AMUX_SPLIT_CTL[37] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[38]

AMUX splitter cell control
address_offset : 0x50B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[38] AMUX_SPLIT_CTL[38] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[39]

AMUX splitter cell control
address_offset : 0x52C30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[39] AMUX_SPLIT_CTL[39] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[40]

AMUX splitter cell control
address_offset : 0x54CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[40] AMUX_SPLIT_CTL[40] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[41]

AMUX splitter cell control
address_offset : 0x56D74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[41] AMUX_SPLIT_CTL[41] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[42]

AMUX splitter cell control
address_offset : 0x58E1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[42] AMUX_SPLIT_CTL[42] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[43]

AMUX splitter cell control
address_offset : 0x5AEC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[43] AMUX_SPLIT_CTL[43] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[44]

AMUX splitter cell control
address_offset : 0x5CF78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[44] AMUX_SPLIT_CTL[44] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[45]

AMUX splitter cell control
address_offset : 0x5F02C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[45] AMUX_SPLIT_CTL[45] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[1]

AMUX splitter cell control
address_offset : 0x6004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[1] AMUX_SPLIT_CTL[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[46]

AMUX splitter cell control
address_offset : 0x610E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[46] AMUX_SPLIT_CTL[46] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[47]

AMUX splitter cell control
address_offset : 0x631A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[47] AMUX_SPLIT_CTL[47] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[48]

AMUX splitter cell control
address_offset : 0x65260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[48] AMUX_SPLIT_CTL[48] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[49]

AMUX splitter cell control
address_offset : 0x67324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[49] AMUX_SPLIT_CTL[49] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[14]-PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[14]-PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[14]-PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[50]

AMUX splitter cell control
address_offset : 0x693EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[50] AMUX_SPLIT_CTL[50] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[14]-PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0x694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[14]-PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[14]-PRT[13]-PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[51]

AMUX splitter cell control
address_offset : 0x6B4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[51] AMUX_SPLIT_CTL[51] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[52]

AMUX splitter cell control
address_offset : 0x6D588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[52] AMUX_SPLIT_CTL[52] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[53]

AMUX splitter cell control
address_offset : 0x6F65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[53] AMUX_SPLIT_CTL[53] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[54]

AMUX splitter cell control
address_offset : 0x71734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[54] AMUX_SPLIT_CTL[54] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[55]

AMUX splitter cell control
address_offset : 0x73810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[55] AMUX_SPLIT_CTL[55] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[56]

AMUX splitter cell control
address_offset : 0x758F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[56] AMUX_SPLIT_CTL[56] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[57]

AMUX splitter cell control
address_offset : 0x779D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[57] AMUX_SPLIT_CTL[57] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[58]

AMUX splitter cell control
address_offset : 0x79ABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[58] AMUX_SPLIT_CTL[58] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[59]

AMUX splitter cell control
address_offset : 0x7BBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[59] AMUX_SPLIT_CTL[59] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[60]

AMUX splitter cell control
address_offset : 0x7DC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[60] AMUX_SPLIT_CTL[60] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[61]

AMUX splitter cell control
address_offset : 0x7FD8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[61] AMUX_SPLIT_CTL[61] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[2]

AMUX splitter cell control
address_offset : 0x800C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[2] AMUX_SPLIT_CTL[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[62]

AMUX splitter cell control
address_offset : 0x81E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[62] AMUX_SPLIT_CTL[62] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[63]

AMUX splitter cell control
address_offset : 0x83F80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[63] AMUX_SPLIT_CTL[63] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[3]

AMUX splitter cell control
address_offset : 0xA018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[3] AMUX_SPLIT_CTL[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write


AMUX_SPLIT_CTL[4]

AMUX splitter cell control
address_offset : 0xC028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[4] AMUX_SPLIT_CTL[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


AMUX_SPLIT_CTL[5]

AMUX splitter cell control
address_offset : 0xE03C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMUX_SPLIT_CTL[5] AMUX_SPLIT_CTL[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWITCH_AA_SL SWITCH_AA_SR SWITCH_AA_S0 SWITCH_BB_SL SWITCH_BB_SR SWITCH_BB_S0

SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write

SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write

SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write

SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write

SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write


PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0

Port selection 0
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO0_SEL IO1_SEL IO2_SEL IO3_SEL

IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : GPIO

GPIO controls 'out'

1 : GPIO_DSI

GPIO controls 'out', DSI controls 'output enable'

2 : DSI_DSI

DSI controls 'out' and 'output enable'

3 : DSI_GPIO

DSI controls 'out', GPIO controls 'output enable'

4 : AMUXA

Analog mux bus A

5 : AMUXB

Analog mux bus B

6 : AMUXA_DSI

Analog mux bus A, DSI control

7 : AMUXB_DSI

Analog mux bus B, DSI control

8 : ACT_0

Active functionality 0

9 : ACT_1

Active functionality 1

10 : ACT_2

Active functionality 2

11 : ACT_3

Active functionality 3

12 : DS_0

DeepSleep functionality 0

13 : DS_1

DeepSleep functionality 1

14 : DS_2

DeepSleep functionality 2

15 : DS_3

DeepSleep functionality 3

16 : ACT_4

Active functionality 4

17 : ACT_5

Active functionality 5

18 : ACT_6

Active functionality 6

19 : ACT_7

Active functionality 7

20 : ACT_8

Active functionality 8

21 : ACT_9

Active functionality 9

22 : ACT_10

Active functionality 10

23 : ACT_11

Active functionality 11

24 : ACT_12

Active functionality 12

25 : ACT_13

Active functionality 13

26 : ACT_14

Active functionality 14

27 : ACT_15

Active functionality 15

28 : DS_4

DeepSleep functionality 4

29 : DS_5

DeepSleep functionality 5

30 : DS_6

DeepSleep functionality 6

31 : DS_7

DeepSleep functionality 7

End of enumeration elements list.

IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write

IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write

IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write


PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1

Port selection 1
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO4_SEL IO5_SEL IO6_SEL IO7_SEL

IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write

IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write

IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write

IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write



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