\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1
PRT[2]-PRT[1]-PRT[0]-PORT_SEL0
PRT[2]-PRT[1]-PRT[0]-PORT_SEL1
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1
PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0
PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL0
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-PORT_SEL1
Port selection 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
Port selection 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x10054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x12070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x14090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
Port selection 1
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x160B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x180DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x1A108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x1C138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 1
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x1E16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x201A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x221E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x24220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 1
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x26264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x282AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x2A2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x2C348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
Port selection 1
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x2E39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x303F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x32450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x344B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x36514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
Port selection 1
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x3857C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x3A5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x3C658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x3E6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x4000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x40744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
Port selection 1
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x427C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x44840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x468C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x4894C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x4A9D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x4CA68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
Port selection 1
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x4EAFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x50B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x52C30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x54CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x56D74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x58E1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x5AEC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
Port selection 1
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x5CF78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x5F02C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x6004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x610E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x631A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x65260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x67324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x693EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 1
address_offset : 0x694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x6B4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x6D588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x6F65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x71734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x73810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x758F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x779D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x79ABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x7BBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x7DC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x7FD8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x800C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x81E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0x83F80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0xA018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
AMUX splitter cell control
address_offset : 0xC028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
AMUX splitter cell control
address_offset : 0xE03C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWITCH_AA_SL : T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 0 - 0 (1 bit)
access : read-write
SWITCH_AA_SR : T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed.
bits : 1 - 2 (2 bit)
access : read-write
SWITCH_AA_S0 : T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed.
bits : 2 - 4 (3 bit)
access : read-write
SWITCH_BB_SL : T-switch control for Left AMUXBUSB switch.
bits : 4 - 8 (5 bit)
access : read-write
SWITCH_BB_SR : T-switch control for Right AMUXBUSB switch.
bits : 5 - 10 (6 bit)
access : read-write
SWITCH_BB_S0 : T-switch control for AMUXBUSB vssa/ground switch.
bits : 6 - 12 (7 bit)
access : read-write
Port selection 0
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO0_SEL : Selects connection for IO pin 0 route.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : GPIO
GPIO controls 'out'
1 : GPIO_DSI
GPIO controls 'out', DSI controls 'output enable'
2 : DSI_DSI
DSI controls 'out' and 'output enable'
3 : DSI_GPIO
DSI controls 'out', GPIO controls 'output enable'
4 : AMUXA
Analog mux bus A
5 : AMUXB
Analog mux bus B
6 : AMUXA_DSI
Analog mux bus A, DSI control
7 : AMUXB_DSI
Analog mux bus B, DSI control
8 : ACT_0
Active functionality 0
9 : ACT_1
Active functionality 1
10 : ACT_2
Active functionality 2
11 : ACT_3
Active functionality 3
12 : DS_0
DeepSleep functionality 0
13 : DS_1
DeepSleep functionality 1
14 : DS_2
DeepSleep functionality 2
15 : DS_3
DeepSleep functionality 3
16 : ACT_4
Active functionality 4
17 : ACT_5
Active functionality 5
18 : ACT_6
Active functionality 6
19 : ACT_7
Active functionality 7
20 : ACT_8
Active functionality 8
21 : ACT_9
Active functionality 9
22 : ACT_10
Active functionality 10
23 : ACT_11
Active functionality 11
24 : ACT_12
Active functionality 12
25 : ACT_13
Active functionality 13
26 : ACT_14
Active functionality 14
27 : ACT_15
Active functionality 15
28 : DS_4
DeepSleep functionality 4
29 : DS_5
DeepSleep functionality 5
30 : DS_6
DeepSleep functionality 6
31 : DS_7
DeepSleep functionality 7
End of enumeration elements list.
IO1_SEL : Selects connection for IO pin 1 route.
bits : 8 - 20 (13 bit)
access : read-write
IO2_SEL : Selects connection for IO pin 2 route.
bits : 16 - 36 (21 bit)
access : read-write
IO3_SEL : Selects connection for IO pin 3 route.
bits : 24 - 52 (29 bit)
access : read-write
Port selection 1
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IO4_SEL : Selects connection for IO pin 4 route. See PORT_SEL0 for connection details.
bits : 0 - 4 (5 bit)
access : read-write
IO5_SEL : Selects connection for IO pin 5 route.
bits : 8 - 20 (13 bit)
access : read-write
IO6_SEL : Selects connection for IO pin 6 route.
bits : 16 - 36 (21 bit)
access : read-write
IO7_SEL : Selects connection for IO pin 7 route.
bits : 24 - 52 (29 bit)
access : read-write
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