Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_CLR
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_SET
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_INV
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-IN
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASK
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASKED
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_SET
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_CFG
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_OUT
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_SIO
PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN_GPIO5V
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_CLR
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_SET
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_INV
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-IN
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASK
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASKED
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_SET
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_CFG
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_OUT
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_SIO
PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN_GPIO5V
PRT[2]-PRT[1]-PRT[0]-INTR_MASK
PRT[2]-PRT[1]-PRT[0]-INTR_MASKED
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_CLR
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_SET
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_INV
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-IN
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASK
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASKED
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_SET
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_CFG
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_OUT
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_SIO
PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN_GPIO5V
PRT[2]-PRT[1]-PRT[0]-CFG_IN_GPIO5V
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_CLR
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_SET
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_INV
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-IN
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASK
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASKED
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_SET
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_CFG
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_OUT
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_SIO
PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN_GPIO5V
PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT
PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-IN
PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR
PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG
PRT[12]-PRT[11]-PRT[10]-PRT[9]-PRT[8]-PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN
PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT
PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_CLR
PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_SET
PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_INV
PRT[3]-PRT[2]-PRT[1]-PRT[0]-IN
PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR
PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASK
PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASKED
PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_SET
PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_CFG
PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG
PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN
PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_OUT
PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_SIO
PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN_GPIO5V
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_CLR
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_SET
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_INV
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-IN
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASK
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASKED
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_SET
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_CFG
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_OUT
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_SIO
PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN_GPIO5V
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_CLR
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_SET
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_INV
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-IN
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASK
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASKED
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_SET
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_CFG
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_OUT
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_SIO
PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN_GPIO5V
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_CLR
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_SET
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_INV
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-IN
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASK
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASKED
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_SET
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_CFG
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_OUT
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_SIO
PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN_GPIO5V
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_CLR
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_SET
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-OUT_INV
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-IN
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASK
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_MASKED
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_SET
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-INTR_CFG
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_OUT
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_SIO
PRT[7]-PRT[6]-PRT[5]-PRT[4]-PRT[3]-PRT[2]-PRT[1]-PRT[0]-CFG_IN_GPIO5V
Port output data register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port output data register
address_offset : 0x1200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x1204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x1208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x120C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x1210 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x1214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x1218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x121C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x1220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x1224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0x1228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x122C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x1230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0x1234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x123C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port interrupt status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port output data register
address_offset : 0x1680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x1684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x1688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x168C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x1690 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x1694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x1698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x169C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x16A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x16A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0x16A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x16AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x16B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x16BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port interrupt mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port output data register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port output data register
address_offset : 0x1B80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x1B84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x1B88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x1B8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x1B90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x1B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x1B98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x1B9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x1BA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x1BA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0x1BA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x1BAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x1BB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0x1BB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x1BBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port output data register
address_offset : 0x2100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x2104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x2108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x210C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x2110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x2114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x2118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x211C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x2120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x2124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0x2128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x212C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x2130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0x2134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x213C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port output data register
address_offset : 0x2700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x2704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x2708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x270C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x2710 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x2714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x2718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x271C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x2720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x2724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0x2728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x272C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x2730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0x2734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x273C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port configuration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output data register
address_offset : 0x2D80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x2D84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x2D88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x2D8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x2D90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x2D94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x2D98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x2D9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x2DA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x2DA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0x2DA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x2DAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x2DB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0x2DB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x2DBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port output data register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port SIO configuration register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port output data register
address_offset : 0x3480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x3484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x3488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x348C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x3490 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x3494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x3498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x349C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x34A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x34A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0x34A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x34AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x34B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0x34B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x34BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Interrupt port cause register 0
address_offset : 0x4000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PORT_INT : Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt
bits : 0 - 31 (32 bit)
access : read-only
Interrupt port cause register 1
address_offset : 0x4004 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PORT_INT : Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to deternine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt
bits : 0 - 31 (32 bit)
access : read-only
Interrupt port cause register 2
address_offset : 0x4008 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PORT_INT : Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to deternine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt
bits : 0 - 31 (32 bit)
access : read-only
Interrupt port cause register 3
address_offset : 0x400C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PORT_INT : Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to deternine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt
bits : 0 - 31 (32 bit)
access : read-only
Extern power supply detection register
address_offset : 0x4010 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VDDIO_ACTIVE : Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. '0': Supply is not present '1': Supply is present When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below: 0: vbackup, 1: vddio_0, 2: vddio_1, 3: vddio_a, 4: vddio_r, 5: vddusb'
bits : 0 - 15 (16 bit)
access : read-only
VDDA_ACTIVE : Same as VDDIO_ACTIVE for the analog supply VDDA.
bits : 30 - 60 (31 bit)
access : read-only
VDDD_ACTIVE : This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.)
bits : 31 - 62 (32 bit)
access : read-only
Supply detection interrupt register
address_offset : 0x4014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDDIO_ACTIVE : Supply state change detected. '0': No change to supply detected '1': Change to supply detected
bits : 0 - 15 (16 bit)
access : read-write
VDDA_ACTIVE : Same as VDDIO_ACTIVE for the analog supply VDDA.
bits : 30 - 60 (31 bit)
access : read-write
VDDD_ACTIVE : The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'.
bits : 31 - 62 (32 bit)
access : read-write
Supply detection interrupt mask register
address_offset : 0x4018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDDIO_ACTIVE : Masks supply interrupt on VDDIO. '0': VDDIO interrupt forwarding disabled '1': VDDIO interrupt forwarding enabled
bits : 0 - 15 (16 bit)
access : read-write
VDDA_ACTIVE : Same as VDDIO_ACTIVE for the analog supply VDDA.
bits : 30 - 60 (31 bit)
access : read-write
VDDD_ACTIVE : Same as VDDIO_ACTIVE for the digital supply VDDD.
bits : 31 - 62 (32 bit)
access : read-write
Supply detection interrupt masked register
address_offset : 0x401C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VDDIO_ACTIVE : Supply transistion detected AND masked '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 15 (16 bit)
access : read-only
VDDA_ACTIVE : Same as VDDIO_ACTIVE for the analog supply VDDA.
bits : 30 - 60 (31 bit)
access : read-only
VDDD_ACTIVE : Same as VDDIO_ACTIVE for the digital supply VDDD.
bits : 31 - 62 (32 bit)
access : read-only
Supply detection interrupt set register
address_offset : 0x4020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDDIO_ACTIVE : Sets supply interrupt. '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 15 (16 bit)
access : read-write
VDDA_ACTIVE : Same as VDDIO_ACTIVE for the analog supply VDDA.
bits : 30 - 60 (31 bit)
access : read-write
VDDD_ACTIVE : Same as VDDIO_ACTIVE for the digital supply VDDD.
bits : 31 - 62 (32 bit)
access : read-write
Port output data register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port output data register
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x78C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x79C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0x7A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0x7AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0x7B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0x7BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port output data register
address_offset : 0xA80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0xA88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0xA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0xA94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0xA98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0xA9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0xAA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0xAA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0xAA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0xAAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0xAB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0xAB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0xABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port input buffer configuration register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1'
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO output data for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO output data for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO output data for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO output data for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO output data for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO output data for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO output data for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data set register
address_offset : 0xE04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO clear output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO clear output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO clear output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO clear output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO clear output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO clear output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO clear output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data clear register
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO set output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO set output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO set output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO set output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO set output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO set output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO set output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port output data invert register
address_offset : 0xE0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0 : IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0').
bits : 0 - 0 (1 bit)
access : read-write
OUT1 : IO invert output for pin 1
bits : 1 - 2 (2 bit)
access : read-write
OUT2 : IO invert output for pin 2
bits : 2 - 4 (3 bit)
access : read-write
OUT3 : IO invert output for pin 3
bits : 3 - 6 (4 bit)
access : read-write
OUT4 : IO invert output for pin 4
bits : 4 - 8 (5 bit)
access : read-write
OUT5 : IO invert output for pin 5
bits : 5 - 10 (6 bit)
access : read-write
OUT6 : IO invert output for pin 6
bits : 6 - 12 (7 bit)
access : read-write
OUT7 : IO invert output for pin 7
bits : 7 - 14 (8 bit)
access : read-write
Port input state register
address_offset : 0xE10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IN0 : IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin.
bits : 0 - 0 (1 bit)
access : read-only
IN1 : IO pin state for pin 1
bits : 1 - 2 (2 bit)
access : read-only
IN2 : IO pin state for pin 2
bits : 2 - 4 (3 bit)
access : read-only
IN3 : IO pin state for pin 3
bits : 3 - 6 (4 bit)
access : read-only
IN4 : IO pin state for pin 4
bits : 4 - 8 (5 bit)
access : read-only
IN5 : IO pin state for pin 5
bits : 5 - 10 (6 bit)
access : read-only
IN6 : IO pin state for pin 6
bits : 6 - 12 (7 bit)
access : read-only
IN7 : IO pin state for pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_IN : Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt status register
address_offset : 0xE14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin.
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Edge detect for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Edge detect for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Edge detect for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Edge detect for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Edge detect for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Edge detect for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Edge detect for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Edge detected on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
IN_IN0 : IO pin state for pin 0
bits : 16 - 32 (17 bit)
access : read-only
IN_IN1 : IO pin state for pin 1
bits : 17 - 34 (18 bit)
access : read-only
IN_IN2 : IO pin state for pin 2
bits : 18 - 36 (19 bit)
access : read-only
IN_IN3 : IO pin state for pin 3
bits : 19 - 38 (20 bit)
access : read-only
IN_IN4 : IO pin state for pin 4
bits : 20 - 40 (21 bit)
access : read-only
IN_IN5 : IO pin state for pin 5
bits : 21 - 42 (22 bit)
access : read-only
IN_IN6 : IO pin state for pin 6
bits : 22 - 44 (23 bit)
access : read-only
IN_IN7 : IO pin state for pin 7
bits : 23 - 46 (24 bit)
access : read-only
FLT_IN_IN : Filtered pin state for pin selected by INTR_CFG.FLT_SEL
bits : 24 - 48 (25 bit)
access : read-only
Port interrupt mask register
address_offset : 0xE18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Masks edge interrupt on IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Masks edge interrupt on IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Masks edge interrupt on IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Masks edge interrupt on IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Masks edge interrupt on IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Masks edge interrupt on IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Masks edge interrupt on IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt masked status register
address_offset : 0xE1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU
bits : 0 - 0 (1 bit)
access : read-only
EDGE1 : Edge detected and masked on IO pin 1
bits : 1 - 2 (2 bit)
access : read-only
EDGE2 : Edge detected and masked on IO pin 2
bits : 2 - 4 (3 bit)
access : read-only
EDGE3 : Edge detected and masked on IO pin 3
bits : 3 - 6 (4 bit)
access : read-only
EDGE4 : Edge detected and masked on IO pin 4
bits : 4 - 8 (5 bit)
access : read-only
EDGE5 : Edge detected and masked on IO pin 5
bits : 5 - 10 (6 bit)
access : read-only
EDGE6 : Edge detected and masked on IO pin 6
bits : 6 - 12 (7 bit)
access : read-only
EDGE7 : Edge detected and masked on IO pin 7
bits : 7 - 14 (8 bit)
access : read-only
FLT_EDGE : Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-only
Port interrupt set register
address_offset : 0xE20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0 : Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set
bits : 0 - 0 (1 bit)
access : read-write
EDGE1 : Sets edge detect interrupt for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
EDGE2 : Sets edge detect interrupt for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
EDGE3 : Sets edge detect interrupt for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
EDGE4 : Sets edge detect interrupt for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
EDGE5 : Sets edge detect interrupt for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
EDGE6 : Sets edge detect interrupt for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
EDGE7 : Sets edge detect interrupt for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
FLT_EDGE : Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0xE24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pin 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pin 1
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pin 2
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pin 3
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pin 4
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pin 5
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pin 6
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pin 7
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Port configuration register
address_offset : 0xE28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRIVE_MODE0 : The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : HIGHZ
Output buffer is off creating a high impedance input
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
1 : RSVD
N/A
2 : PULLUP
Resistive pull up
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Weak/resistive pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull up
D_OUT = '1': Weak/resistive pull up
3 : PULLDOWN
Resistive pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull down
4 : OD_DRIVESLOW
Open drain, drives low
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': High Impedance
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
5 : OD_DRIVESHIGH
Open drain, drives high
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': High Impedance
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
6 : STRONG
Strong D_OUTput buffer
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High impedance
D_OUT = '1': High impedance
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': High Impedance
D_OUT = '1': High Impedance
7 : PULLUP_DOWN
Pull up or pull down
For GPIO & UDB/DSI peripherals:
When D_OUT_EN = '0':
GPIO_DSI_OUT = '0': Weak/resistive pull down
GPIO_DSI_OUT = '1': Weak/resistive pull up
where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT & DSI_DATA_OUT.
For peripherals other than GPIO & UDB/DSI:
When D_OUT_EN = 1:
D_OUT = '0': Strong pull down
D_OUT = '1': Strong pull up
When D_OUT_EN = 0:
D_OUT = '0': Weak/resistive pull down
D_OUT = '1': Weak/resistive pull up
End of enumeration elements list.
IN_EN0 : Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled
bits : 3 - 6 (4 bit)
access : read-write
DRIVE_MODE1 : The GPIO drive mode for IO pin 1
bits : 4 - 10 (7 bit)
access : read-write
IN_EN1 : Enables the input buffer for IO pin 1
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_MODE2 : The GPIO drive mode for IO pin 2
bits : 8 - 18 (11 bit)
access : read-write
IN_EN2 : Enables the input buffer for IO pin 2
bits : 11 - 22 (12 bit)
access : read-write
DRIVE_MODE3 : The GPIO drive mode for IO pin 3
bits : 12 - 26 (15 bit)
access : read-write
IN_EN3 : Enables the input buffer for IO pin 3
bits : 15 - 30 (16 bit)
access : read-write
DRIVE_MODE4 : The GPIO drive mode for IO pin4
bits : 16 - 34 (19 bit)
access : read-write
IN_EN4 : Enables the input buffer for IO pin 4
bits : 19 - 38 (20 bit)
access : read-write
DRIVE_MODE5 : The GPIO drive mode for IO pin 5
bits : 20 - 42 (23 bit)
access : read-write
IN_EN5 : Enables the input buffer for IO pin 5
bits : 23 - 46 (24 bit)
access : read-write
DRIVE_MODE6 : The GPIO drive mode for IO pin 6
bits : 24 - 50 (27 bit)
access : read-write
IN_EN6 : Enables the input buffer for IO pin 6
bits : 27 - 54 (28 bit)
access : read-write
DRIVE_MODE7 : The GPIO drive mode for IO pin 7
bits : 28 - 58 (31 bit)
access : read-write
IN_EN7 : Enables the input buffer for IO pin 7
bits : 31 - 62 (32 bit)
access : read-write
Port input buffer configuration register
address_offset : 0xE2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_0 : Configures the pin 0 input buffer mode (trip points and hysteresis)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CMOS
Input buffer compatible with CMOS and I2C interfaces
1 : TTL
Input buffer compatible with TTL and MediaLB interfaces
End of enumeration elements list.
VTRIP_SEL1_0 : Configures the pin 1 input buffer mode (trip points and hysteresis)
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_0 : Configures the pin 2 input buffer mode (trip points and hysteresis)
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_0 : Configures the pin 3 input buffer mode (trip points and hysteresis)
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_0 : Configures the pin 4 input buffer mode (trip points and hysteresis)
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_0 : Configures the pin 5 input buffer mode (trip points and hysteresis)
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_0 : Configures the pin 6 input buffer mode (trip points and hysteresis)
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_0 : Configures the pin 7 input buffer mode (trip points and hysteresis)
bits : 7 - 14 (8 bit)
access : read-write
Port output buffer configuration register
address_offset : 0xE30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW0 : Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate
bits : 0 - 0 (1 bit)
access : read-write
SLOW1 : Enables slow slew rate for IO pin 1
bits : 1 - 2 (2 bit)
access : read-write
SLOW2 : Enables slow slew rate for IO pin 2
bits : 2 - 4 (3 bit)
access : read-write
SLOW3 : Enables slow slew rate for IO pin 3
bits : 3 - 6 (4 bit)
access : read-write
SLOW4 : Enables slow slew rate for IO pin 4
bits : 4 - 8 (5 bit)
access : read-write
SLOW5 : Enables slow slew rate for IO pin 5
bits : 5 - 10 (6 bit)
access : read-write
SLOW6 : Enables slow slew rate for IO pin 6
bits : 6 - 12 (7 bit)
access : read-write
SLOW7 : Enables slow slew rate for IO pin 7
bits : 7 - 14 (8 bit)
access : read-write
DRIVE_SEL0 : Sets the GPIO drive strength for IO pin 0
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : FULL_DRIVE
Full drive strength: GPIO drives current at its max rated spec.
1 : ONE_HALF_DRIVE
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
2 : ONE_QUARTER_DRIVE
1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
3 : ONE_EIGHTH_DRIVE
1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
End of enumeration elements list.
DRIVE_SEL1 : Sets the GPIO drive strength for IO pin 1
bits : 18 - 37 (20 bit)
access : read-write
DRIVE_SEL2 : Sets the GPIO drive strength for IO pin 2
bits : 20 - 41 (22 bit)
access : read-write
DRIVE_SEL3 : Sets the GPIO drive strength for IO pin 3
bits : 22 - 45 (24 bit)
access : read-write
DRIVE_SEL4 : Sets the GPIO drive strength for IO pin 4
bits : 24 - 49 (26 bit)
access : read-write
DRIVE_SEL5 : Sets the GPIO drive strength for IO pin 5
bits : 26 - 53 (28 bit)
access : read-write
DRIVE_SEL6 : Sets the GPIO drive strength for IO pin 6
bits : 28 - 57 (30 bit)
access : read-write
DRIVE_SEL7 : Sets the GPIO drive strength for IO pin 7
bits : 30 - 61 (32 bit)
access : read-write
Port SIO configuration register
address_offset : 0xE34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREG_EN01 : The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.
bits : 0 - 0 (1 bit)
access : read-write
IBUF_SEL01 : N/A
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL01 : N/A
bits : 2 - 4 (3 bit)
access : read-write
VREF_SEL01 : N/A
bits : 3 - 7 (5 bit)
access : read-write
VOH_SEL01 : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1'): VTRIP_SEL=0: a) VREF_SEL=00, VOH_SEL=X -> Trip point=50 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=Vohref (buffered) c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as CMOS input buffer. VTRIP_SEL=1: a) VREF_SEL=00, VOH_SEL=X -> Trip point=40 percent of vddio b) VREF_SEL=01, VOH_SEL=000 -> Trip point=0.5*Vohref c) VREF_SEL=01, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer. d) VREF_SEL=10/11, VOH_SEL=000 -> Trip_point=0.5*Amuxbus_a/b (buffered) e) VREF_SEL=10/11, VOH_SEL=[1-7] -> Input buffer functions as LVTTL input buffer.
bits : 5 - 12 (8 bit)
access : read-write
VREG_EN23 : N/A
bits : 8 - 16 (9 bit)
access : read-write
IBUF_SEL23 : N/A
bits : 9 - 18 (10 bit)
access : read-write
VTRIP_SEL23 : N/A
bits : 10 - 20 (11 bit)
access : read-write
VREF_SEL23 : N/A
bits : 11 - 23 (13 bit)
access : read-write
VOH_SEL23 : N/A
bits : 13 - 28 (16 bit)
access : read-write
VREG_EN45 : N/A
bits : 16 - 32 (17 bit)
access : read-write
IBUF_SEL45 : N/A
bits : 17 - 34 (18 bit)
access : read-write
VTRIP_SEL45 : N/A
bits : 18 - 36 (19 bit)
access : read-write
VREF_SEL45 : N/A
bits : 19 - 39 (21 bit)
access : read-write
VOH_SEL45 : N/A
bits : 21 - 44 (24 bit)
access : read-write
VREG_EN67 : N/A
bits : 24 - 48 (25 bit)
access : read-write
IBUF_SEL67 : N/A
bits : 25 - 50 (26 bit)
access : read-write
VTRIP_SEL67 : N/A
bits : 26 - 52 (27 bit)
access : read-write
VREF_SEL67 : N/A
bits : 27 - 55 (29 bit)
access : read-write
VOH_SEL67 : N/A
bits : 29 - 60 (32 bit)
access : read-write
Port GPIO5V input buffer configuration register
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTRIP_SEL0_1 : Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. 0: input buffer is not compatible with automative. 1: input buffer is compatible with automative. Use CFG_IN.VTRIP_SEL0_0 fieds set as CMOS only when this bit needs to be set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input buffer not compatible with automotive (elevated Vil) interfaces.
1 : AUTO
Input buffer compatible with automotive (elevated Vil) interfaces.
End of enumeration elements list.
VTRIP_SEL1_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 1 - 2 (2 bit)
access : read-write
VTRIP_SEL2_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 2 - 4 (3 bit)
access : read-write
VTRIP_SEL3_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 3 - 6 (4 bit)
access : read-write
VTRIP_SEL4_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 4 - 8 (5 bit)
access : read-write
VTRIP_SEL5_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 5 - 10 (6 bit)
access : read-write
VTRIP_SEL6_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 6 - 12 (7 bit)
access : read-write
VTRIP_SEL7_1 : Input buffer compatible with automotive (elevated Vil) interfaces.
bits : 7 - 14 (8 bit)
access : read-write
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