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CSD0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONFIG

HSCMP

AMBUF

REFGEN

CSDCMP

SW_RES

SENSE_PERIOD

SENSE_DUTY

SW_HS_P_SEL

SW_HS_N_SEL

SW_SHIELD_SEL

SW_AMUXBUF_SEL

SW_BYP_SEL

SW_CMP_P_SEL

SW_CMP_N_SEL

SW_REFGEN_SEL

SW_FW_MOD_SEL

SW_FW_TANK_SEL

SW_DSI_SEL

IO_SEL

SEQ_TIME

SEQ_INIT_CNT

SEQ_NORM_CNT

ADC_CTL

SEQ_START

SPARE

IDACA

IDACB

STATUS

STAT_SEQ

STAT_CNTS

STAT_HCNT

RESULT_VAL1

RESULT_VAL2

ADC_RES

INTR

INTR_SET

INTR_MASK

INTR_MASKED


CONFIG

Configuration and Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IREF_SEL FILTER_DELAY SHIELD_DELAY SENSE_EN FULL_WAVE MUTUAL_CAP CSX_DUAL_CNT DSI_COUNT_SEL DSI_SAMPLE_EN SAMPLE_SYNC DSI_SENSE_EN LP_MODE ENABLE

IREF_SEL : N/A
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : IREF_SRSS

N/A

1 : IREF_PASS

N/A

End of enumeration elements list.

FILTER_DELAY : Enables the digital filtering on the CSD comparator
bits : 4 - 12 (9 bit)
access : read-write

SHIELD_DELAY : Configures the delay between shield clock and sensor clock
bits : 10 - 21 (12 bit)
access : read-write

Enumeration:

0 : OFF

Delay line is off; sensor clock = shield clock

1 : D5NS

shield clock is delayed by 5ns delay w.r.t sensor clock

2 : D10NS

shield clock is delayed by 10ns delay w.r.t sensor clock

3 : D20NS

shield clock is delayed by 20ns delay w.r.t sensor clock

End of enumeration elements list.

SENSE_EN : Enables the sensor and shield clocks, CSD modulator output and turns on the IDAC compensation current as selected by CSD_IDAC.
bits : 12 - 24 (13 bit)
access : read-write

FULL_WAVE : N/A
bits : 17 - 34 (18 bit)
access : read-write

Enumeration:

0 : HALFWAVE

Half Wave mode

1 : FULLWAVE

Full Wave mode

End of enumeration elements list.

MUTUAL_CAP : N/A
bits : 18 - 36 (19 bit)
access : read-write

Enumeration:

0 : SELFCAP

Self-cap mode

1 : MUTUALCAP

Mutual-cap mode

End of enumeration elements list.

CSX_DUAL_CNT : N/A
bits : 19 - 38 (20 bit)
access : read-write

Enumeration:

0 : ONE

N/A

1 : TWO

N/A

End of enumeration elements list.

DSI_COUNT_SEL : N/A
bits : 24 - 48 (25 bit)
access : read-write

Enumeration:

0 : CSD_RESULT

N/A

1 : ADC_RESULT

N/A

End of enumeration elements list.

DSI_SAMPLE_EN : DSI_SAMPLE_EN = 1 -> COUNTER will count the samples generated by DSI DSI_SAMPLE_EN = 0 -> COUNTER will count the samples generated by CSD modulator
bits : 25 - 50 (26 bit)
access : read-write

SAMPLE_SYNC : N/A
bits : 26 - 52 (27 bit)
access : read-write

DSI_SENSE_EN : DSI_SENSE_EN = 1-> sensor clock is driven directly by DSI DSI_SENSE_EN = 0-> sensor clock is driven by PRS/divide-by-2/DIRECT_CLOCK
bits : 27 - 54 (28 bit)
access : read-write

LP_MODE : N/A
bits : 30 - 60 (31 bit)
access : read-write

ENABLE : N/A
bits : 31 - 62 (32 bit)
access : read-write


HSCMP

High Speed Comparator configuration
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSCMP HSCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSCMP_EN HSCMP_INVERT AZ_EN

HSCMP_EN : High Speed Comparator enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : OFF

Disable comparator, output is zero

1 : ON

On, regular operation. Note that CONFIG.LP_MODE determines the power mode level

End of enumeration elements list.

HSCMP_INVERT : Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT
bits : 4 - 8 (5 bit)
access : read-write

AZ_EN : Auto-Zero enable, allow the Sequencer to Auto-Zero this component
bits : 31 - 62 (32 bit)
access : read-write


AMBUF

Reference Generator configuration
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMBUF AMBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWR_MODE

PWR_MODE : Amux buffer power level
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : OFF

Disable buffer

1 : NORM

On, normal or low power level depending on CONFIG.LP_MODE.

2 : HI

On, high or low power level depending on CONFIG.LP_MODE.

End of enumeration elements list.


REFGEN

Reference Generator configuration
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REFGEN REFGEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFGEN_EN BYPASS VDDA_EN RES_EN GAIN VREFLO_SEL VREFLO_INT

REFGEN_EN : Reference Generator Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : OFF

Disable Reference Generator

1 : ON

On, regular operation. Note that CONFIG.LP_MODE determines the power mode level

End of enumeration elements list.

BYPASS : Bypass selected input reference unbuffered to Vrefhi
bits : 4 - 8 (5 bit)
access : read-write

VDDA_EN : Close Vdda switch to top of resistor string (or Vrefhi?)
bits : 5 - 10 (6 bit)
access : read-write

RES_EN : Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa)
bits : 6 - 12 (7 bit)
access : read-write

GAIN : Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -> gain=1 (only works if the resistor string is enabled; RES_EN=1)
bits : 8 - 20 (13 bit)
access : read-write

VREFLO_SEL : Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1)
bits : 16 - 36 (21 bit)
access : read-write

VREFLO_INT : Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1).
bits : 23 - 46 (24 bit)
access : read-write


CSDCMP

CSD Comparator configuration
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSDCMP CSDCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSDCMP_EN POLARITY_SEL CMP_PHASE CMP_MODE FEEDBACK_MODE AZ_EN

CSDCMP_EN : CSD Comparator Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : OFF

Disable comparator, output is zero

1 : ON

On, regular operation. Note that CONFIG.LP_MODE determines the power mode level

End of enumeration elements list.

POLARITY_SEL : Select which IDAC polarity to use to detect CSDCMP triggering
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

0 : IDACA_POL

Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX

1 : IDACB_POL

Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common)

2 : DUAL_POL

Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case

End of enumeration elements list.

CMP_PHASE : Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap).
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

0 : FULL

Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off)

1 : PHI1

Comparator is active during Phi1 only. Currently no known use-case.

2 : PHI2

Comparator is active during Phi2 only. Intended usage: CSD Low EMI.

3 : PHI1_2

Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave.

End of enumeration elements list.

CMP_MODE : Select which signal to output on dsi_sample_out.
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

0 : CSD

CSD mode: output the filtered sample signal on dsi_sample_out

1 : GP

General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped.

End of enumeration elements list.

FEEDBACK_MODE : This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out.
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

0 : FLOP

Use feedback from sampling flip-flop (used in most modes).

1 : COMP

Use feedback from comparator directly (used in single Cmod mutual cap sensing only)

End of enumeration elements list.

AZ_EN : Auto-Zero enable, allow the Sequencer to Auto-Zero this component
bits : 31 - 62 (32 bit)
access : read-write


SW_RES

Switch Resistance configuration
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_RES SW_RES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES_HCAV RES_HCAG RES_HCBV RES_HCBG RES_F1PM RES_F2PT

RES_HCAV : Select resistance or low EMI (slow ramp) for the HCAV switch
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : LOW

Low

1 : MED

Medium

2 : HIGH

High

3 : LOWEMI

Low EMI (slow ramp: 3 switches closed by fixed delay line)

End of enumeration elements list.

RES_HCAG : Select resistance or low EMI for the corresponding switch
bits : 2 - 5 (4 bit)
access : read-write

RES_HCBV : Select resistance or low EMI for the corresponding switch
bits : 4 - 9 (6 bit)
access : read-write

RES_HCBG : Select resistance or low EMI for the corresponding switch
bits : 6 - 13 (8 bit)
access : read-write

RES_F1PM : Select resistance for the corresponding switch
bits : 16 - 33 (18 bit)
access : read-write

Enumeration:

0 : LOW

Low

1 : MED

Medium

2 : HIGH

High

3 : RSVD

N/A

End of enumeration elements list.

RES_F2PT : Select resistance for the corresponding switch
bits : 18 - 37 (20 bit)
access : read-write


SENSE_PERIOD

Sense clock period
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SENSE_PERIOD SENSE_PERIOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SENSE_DIV LFSR_SIZE LFSR_SCALE LFSR_CLEAR SEL_LFSR_MSB LFSR_BITS

SENSE_DIV : The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) . Note this is the base divider, clock dithering may change the actual period length. Note that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be >=3. In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value.
bits : 0 - 11 (12 bit)
access : read-write

LFSR_SIZE : Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set.
bits : 16 - 34 (19 bit)
access : read-write

Enumeration:

0 : OFF

Don't use clock dithering (=spreadspectrum) (LFSR output value is zero)

1 : 6B

6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63)

2 : 7B

7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127)

3 : 9B

9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511)

4 : 10B

10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023)

5 : 8B

8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255)

6 : 12B

12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095)

End of enumeration elements list.

LFSR_SCALE : Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set. The clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT< bits : 20 - 43 (24 bit)
access : read-write

LFSR_CLEAR : When set, forces the LFSR to it's initial state (all ones). This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used. Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states.
bits : 24 - 48 (25 bit)
access : read-write

SEL_LFSR_MSB : Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled.
bits : 25 - 50 (26 bit)
access : read-write

LFSR_BITS : Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period. Caveat make sure that SENSE_DIV > the maximum absolute range (e.g. for 4B SENSE_DIV > 8), otherwise results are undefined.
bits : 26 - 53 (28 bit)
access : read-write

Enumeration:

0 : 2B

use 2 bits: range = [-2,1]

1 : 3B

use 3 bits: range = [-4,3]

2 : 4B

use 4 bits: range = [-8,7]

3 : 5B

use 5 bits: range = [-16,15] (default)

End of enumeration elements list.


SENSE_DUTY

Sense clock duty cycle
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SENSE_DUTY SENSE_DUTY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SENSE_WIDTH SENSE_POL OVERLAP_PHI1 OVERLAP_PHI2

SENSE_WIDTH : Defines the length of the first phase of the sense clock in clk_csd cycles. A value of 0 disables this feature and the duty cycle of csd_sense will be 50 percent, which is equal to SENSE_WIDTH = (SENSE_DIV+1)/2, or when clock dithering is used that becomes [(SENSE_DIV+1) + (LFSR_OUT << LSFR_SCALE)]/2. At all times it must be assured that the phases are at least 2 clk_csd cycles (1 for non overlap, if used), if this rule is violated the result is undefined. Note that this feature is not available when SEL_LFSR_MSB (PRS) is selected.
bits : 0 - 11 (12 bit)
access : read-write

SENSE_POL : Polarity of the sense clock 0 = start with low phase (typical for regular negative transfer CSD) 1 = start with high phase
bits : 16 - 32 (17 bit)
access : read-write

OVERLAP_PHI1 : NonOverlap or not for Phi1 (csd_sense=0). 0 = Non-overlap for Phi1, the Phi1 signal is csd_sense inverted except that the signal goes low 1 clk_sample before csd_sense goes high. Intended usage: new low EMI CSD/CSX with static GPIO. 1 = 'Overlap' (= not non-overlap) for Phi1, the Phi1 signal is csd_sense inverted. Intended usage: legacy CSD with GPIO switching, the GPIO internal circuit ensures that the switches are non-overlapping.
bits : 18 - 36 (19 bit)
access : read-write

OVERLAP_PHI2 : Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1).
bits : 19 - 38 (20 bit)
access : read-write


SW_HS_P_SEL

HSCMP Pos input switch Waveform selection
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_HS_P_SEL SW_HS_P_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_HMPM SW_HMPT SW_HMPS SW_HMMA SW_HMMB SW_HMCA SW_HMCB SW_HMRH

SW_HMPM : Set HMPM switch 0: static open 1: static closed
bits : 0 - 0 (1 bit)
access : read-write

SW_HMPT : Set corresponding switch
bits : 4 - 8 (5 bit)
access : read-write

SW_HMPS : Set corresponding switch
bits : 8 - 16 (9 bit)
access : read-write

SW_HMMA : Set corresponding switch
bits : 12 - 24 (13 bit)
access : read-write

SW_HMMB : Set corresponding switch
bits : 16 - 32 (17 bit)
access : read-write

SW_HMCA : Set corresponding switch
bits : 20 - 40 (21 bit)
access : read-write

SW_HMCB : Set corresponding switch
bits : 24 - 48 (25 bit)
access : read-write

SW_HMRH : Set corresponding switch
bits : 28 - 56 (29 bit)
access : read-write


SW_HS_N_SEL

HSCMP Neg input switch Waveform selection
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_HS_N_SEL SW_HS_N_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_HCCC SW_HCCD SW_HCRH SW_HCRL

SW_HCCC : Set corresponding switch
bits : 16 - 32 (17 bit)
access : read-write

SW_HCCD : Set corresponding switch
bits : 20 - 40 (21 bit)
access : read-write

SW_HCRH : Select waveform for corresponding switch
bits : 24 - 50 (27 bit)
access : read-write

SW_HCRL : Select waveform for corresponding switch
bits : 28 - 58 (31 bit)
access : read-write


SW_SHIELD_SEL

Shielding switches Waveform selection
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_SHIELD_SEL SW_SHIELD_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_HCAV SW_HCAG SW_HCBV SW_HCBG SW_HCCV SW_HCCG

SW_HCAV : N/A
bits : 0 - 2 (3 bit)
access : read-write

SW_HCAG : Select waveform for corresponding switch
bits : 4 - 10 (7 bit)
access : read-write

SW_HCBV : N/A
bits : 8 - 18 (11 bit)
access : read-write

SW_HCBG : Select waveform for corresponding switch, using csd_shield as base
bits : 12 - 26 (15 bit)
access : read-write

SW_HCCV : Set corresponding switch
bits : 16 - 32 (17 bit)
access : read-write

SW_HCCG : Set corresponding switch If the ADC is enabled then this switch is directly controlled by the ADC sequencer.
bits : 20 - 40 (21 bit)
access : read-write


SW_AMUXBUF_SEL

Amuxbuffer switches Waveform selection
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_AMUXBUF_SEL SW_AMUXBUF_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_IRBY SW_IRLB SW_ICA SW_ICB SW_IRLI SW_IRH SW_IRL

SW_IRBY : Set corresponding switch
bits : 4 - 8 (5 bit)
access : read-write

SW_IRLB : Set corresponding switch
bits : 8 - 16 (9 bit)
access : read-write

SW_ICA : Set corresponding switch
bits : 12 - 24 (13 bit)
access : read-write

SW_ICB : Select waveform for corresponding switch
bits : 16 - 34 (19 bit)
access : read-write

SW_IRLI : Set corresponding switch
bits : 20 - 40 (21 bit)
access : read-write

SW_IRH : Set corresponding switch
bits : 24 - 48 (25 bit)
access : read-write

SW_IRL : Set corresponding switch
bits : 28 - 56 (29 bit)
access : read-write


SW_BYP_SEL

AMUXBUS bypass switches Waveform selection
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_BYP_SEL SW_BYP_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_BYA SW_BYB SW_CBCC

SW_BYA : Set corresponding switch
bits : 12 - 24 (13 bit)
access : read-write

SW_BYB : Set corresponding switch
bits : 16 - 32 (17 bit)
access : read-write

SW_CBCC : Set corresponding switch If the ADC is enabled then this switch is directly controlled by the ADC sequencer.
bits : 20 - 40 (21 bit)
access : read-write


SW_CMP_P_SEL

CSDCMP Pos Switch Waveform selection
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_CMP_P_SEL SW_CMP_P_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_SFPM SW_SFPT SW_SFPS SW_SFMA SW_SFMB SW_SFCA SW_SFCB

SW_SFPM : Select waveform for corresponding switch
bits : 0 - 2 (3 bit)
access : read-write

SW_SFPT : Select waveform for corresponding switch
bits : 4 - 10 (7 bit)
access : read-write

SW_SFPS : Select waveform for corresponding switch
bits : 8 - 18 (11 bit)
access : read-write

SW_SFMA : Set corresponding switch
bits : 12 - 24 (13 bit)
access : read-write

SW_SFMB : Set corresponding switch
bits : 16 - 32 (17 bit)
access : read-write

SW_SFCA : Set corresponding switch
bits : 20 - 40 (21 bit)
access : read-write

SW_SFCB : Set corresponding switch
bits : 24 - 48 (25 bit)
access : read-write


SW_CMP_N_SEL

CSDCMP Neg Switch Waveform selection
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_CMP_N_SEL SW_CMP_N_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_SCRH SW_SCRL

SW_SCRH : Select waveform for corresponding switch
bits : 24 - 50 (27 bit)
access : read-write

SW_SCRL : Select waveform for corresponding switch
bits : 28 - 58 (31 bit)
access : read-write


SW_REFGEN_SEL

Reference Generator Switch Waveform selection
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_REFGEN_SEL SW_REFGEN_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_IAIB SW_IBCB SW_SGMB SW_SGRP SW_SGRE SW_SGR

SW_IAIB : Set corresponding switch
bits : 0 - 0 (1 bit)
access : read-write

SW_IBCB : Set corresponding switch
bits : 4 - 8 (5 bit)
access : read-write

SW_SGMB : Set corresponding switch
bits : 16 - 32 (17 bit)
access : read-write

SW_SGRP : Set corresponding switch
bits : 20 - 40 (21 bit)
access : read-write

SW_SGRE : Set corresponding switch
bits : 24 - 48 (25 bit)
access : read-write

SW_SGR : Set corresponding switch
bits : 28 - 56 (29 bit)
access : read-write


SW_FW_MOD_SEL

Full Wave Cmod Switch Waveform selection
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_FW_MOD_SEL SW_FW_MOD_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_F1PM SW_F1MA SW_F1CA SW_C1CC SW_C1CD SW_C1F1

SW_F1PM : Set corresponding switch
bits : 0 - 0 (1 bit)
access : read-write

SW_F1MA : Select waveform for corresponding switch
bits : 8 - 18 (11 bit)
access : read-write

SW_F1CA : Select waveform for corresponding switch
bits : 16 - 34 (19 bit)
access : read-write

SW_C1CC : Set corresponding switch
bits : 20 - 40 (21 bit)
access : read-write

SW_C1CD : Set corresponding switch
bits : 24 - 48 (25 bit)
access : read-write

SW_C1F1 : Set corresponding switch
bits : 28 - 56 (29 bit)
access : read-write


SW_FW_TANK_SEL

Full Wave Csh_tank Switch Waveform selection
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_FW_TANK_SEL SW_FW_TANK_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_F2PT SW_F2MA SW_F2CA SW_F2CB SW_C2CC SW_C2CD SW_C2F2

SW_F2PT : Set corresponding switch
bits : 4 - 8 (5 bit)
access : read-write

SW_F2MA : Select waveform for corresponding switch
bits : 8 - 18 (11 bit)
access : read-write

SW_F2CA : Select waveform for corresponding switch
bits : 12 - 26 (15 bit)
access : read-write

SW_F2CB : Select waveform for corresponding switch
bits : 16 - 34 (19 bit)
access : read-write

SW_C2CC : Set corresponding switch
bits : 20 - 40 (21 bit)
access : read-write

SW_C2CD : Set corresponding switch
bits : 24 - 48 (25 bit)
access : read-write

SW_C2F2 : Set corresponding switch
bits : 28 - 56 (29 bit)
access : read-write


SW_DSI_SEL

DSI output switch control Waveform selection
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_DSI_SEL SW_DSI_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSI_CSH_TANK DSI_CMOD

DSI_CSH_TANK : Select waveform for dsi_csh_tank output signal 0: static open 1: static closed 2: phi1 3: phi2 4: phi1 & HSCMP 5: phi2 & HSCMP 6: HSCMP // ignores phi1/2 7: !sense // = phi1 but ignores OVERLAP_PHI1 8: phi1_delay // phi1 delayed with shield delay 9: phi2_delay // phi2 delayed with shield delay 10: !phi1 11: !phi2 12: !(phi1 & HSCMP) 13: !(phi2 & HSCMP) 14: !HSCMP // ignores phi1/2 15: sense // = phi2 but ignores OVERLAP_PHI2
bits : 0 - 3 (4 bit)
access : read-write

DSI_CMOD : Select waveform for dsi_cmod output signal
bits : 4 - 11 (8 bit)
access : read-write


IO_SEL

IO output control Waveform selection
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IO_SEL IO_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSD_TX_OUT CSD_TX_OUT_EN CSD_TX_AMUXB_EN CSD_TX_N_OUT CSD_TX_N_OUT_EN CSD_TX_N_AMUXA_EN

CSD_TX_OUT : Select waveform for csd_tx_out output signal
bits : 0 - 3 (4 bit)
access : read-write

CSD_TX_OUT_EN : Select waveform for csd_tx_out_en output signal
bits : 4 - 11 (8 bit)
access : read-write

CSD_TX_AMUXB_EN : Select waveform for csd_tx_amuxb_en output signal
bits : 12 - 27 (16 bit)
access : read-write

CSD_TX_N_OUT : Select waveform for csd_tx_n_out output signal
bits : 16 - 35 (20 bit)
access : read-write

CSD_TX_N_OUT_EN : Select waveform for csd_tx_n_out_en output signal
bits : 20 - 43 (24 bit)
access : read-write

CSD_TX_N_AMUXA_EN : Select waveform for csd_tx_n_amuxa_en output signal
bits : 24 - 51 (28 bit)
access : read-write


SEQ_TIME

Sequencer Timing
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ_TIME SEQ_TIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AZ_TIME

AZ_TIME : Define Auto-Zero time in csd_sense cycles -1.
bits : 0 - 7 (8 bit)
access : read-write


SEQ_INIT_CNT

Sequencer Initial conversion and sample counts
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ_INIT_CNT SEQ_INIT_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONV_CNT

CONV_CNT : Number of conversion per Initialization sample, if set to 0 the Sample_init state will be skipped.
bits : 0 - 15 (16 bit)
access : read-write


SEQ_NORM_CNT

Sequencer Normal conversion and sample counts
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ_NORM_CNT SEQ_NORM_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONV_CNT

CONV_CNT : Number of conversion per sample, if set to 0 the Sample_norm state will be skipped. Sample window size = SEQ_NORM_CNT.CONV_CNT * (SENSE_PERIOD.SENSE_DIV+1). Note for CSDv1 Sample window size = PERIOD
bits : 0 - 15 (16 bit)
access : read-write


ADC_CTL

ADC Control
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CTL ADC_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_TIME ADC_MODE

ADC_TIME : ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&2, or as the aperture to capture the input voltage on Cref1&2
bits : 0 - 7 (8 bit)
access : read-write

ADC_MODE : Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state
bits : 16 - 33 (18 bit)
access : read-write

Enumeration:

0 : OFF

No ADC measurement

1 : VREF_CNT

Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB

2 : VREF_BY2_CNT

Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking)

3 : VIN_CNT

Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi.

End of enumeration elements list.


SEQ_START

Sequencer start
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ_START SEQ_START read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START SEQ_MODE ABORT DSI_START_EN AZ0_SKIP AZ1_SKIP

START : Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode).
bits : 0 - 0 (1 bit)
access : read-write

SEQ_MODE : 0 = regular CSD scan + optional ADC 1 = coarse initialization, the Sequencer will go to the INIT_COARSE state.
bits : 1 - 2 (2 bit)
access : read-write

ABORT : When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0.
bits : 3 - 6 (4 bit)
access : read-write

DSI_START_EN : When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer.
bits : 4 - 8 (5 bit)
access : read-write

AZ0_SKIP : When set the AutoZero_0 state will be skipped
bits : 8 - 16 (9 bit)
access : read-write

AZ1_SKIP : When set the AutoZero_1 state will be skipped
bits : 9 - 18 (10 bit)
access : read-write


SPARE

Spare MMIO
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPARE SPARE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPARE

SPARE : Spare MMIO
bits : 0 - 3 (4 bit)
access : read-write


IDACA

IDACA Configuration
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDACA IDACA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL POL_DYN POLARITY BAL_MODE LEG1_MODE LEG2_MODE DSI_CTRL_EN RANGE LEG1_EN LEG2_EN

VAL : N/A
bits : 0 - 6 (7 bit)
access : read-write

POL_DYN : N/A
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : STATIC

N/A

1 : DYNAMIC

N/A

End of enumeration elements list.

POLARITY : N/A
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

0 : VSSA_SRC

Normal: sensor switching between Vssio and Cmod. For non-CSD application, IDAC1 will source current.

1 : VDDA_SNK

Inverted: sensor switch between Vddio and Cmod. For non-CSD application, IDAC1 will sink current.

2 : SENSE

N/A

3 : SENSE_INV

N/A

End of enumeration elements list.

BAL_MODE : N/A
bits : 10 - 21 (12 bit)
access : read-write

Enumeration:

0 : FULL

N/A

1 : PHI1

N/A

2 : PHI2

N/A

3 : PHI1_2

N/A

End of enumeration elements list.

LEG1_MODE : N/A
bits : 16 - 33 (18 bit)
access : read-write

Enumeration:

0 : GP_STATIC

N/A

1 : GP

N/A

2 : CSD_STATIC

N/A

3 : CSD

N/A

End of enumeration elements list.

LEG2_MODE : N/A
bits : 18 - 37 (20 bit)
access : read-write

Enumeration:

0 : GP_STATIC

N/A

1 : GP

N/A

2 : CSD_STATIC

N/A

3 : CSD

N/A

End of enumeration elements list.

DSI_CTRL_EN : N/A
bits : 21 - 42 (22 bit)
access : read-write

RANGE : N/A
bits : 22 - 45 (24 bit)
access : read-write

Enumeration:

0 : IDAC_LO

N/A

1 : IDAC_MED

N/A

2 : IDAC_HI

N/A

End of enumeration elements list.

LEG1_EN : N/A
bits : 24 - 48 (25 bit)
access : read-write

LEG2_EN : N/A
bits : 25 - 50 (26 bit)
access : read-write


IDACB

IDACB Configuration
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDACB IDACB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL POL_DYN POLARITY BAL_MODE LEG1_MODE LEG2_MODE DSI_CTRL_EN RANGE LEG1_EN LEG2_EN LEG3_EN

VAL : N/A
bits : 0 - 6 (7 bit)
access : read-write

POL_DYN : N/A
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : STATIC

N/A

1 : DYNAMIC

N/A

End of enumeration elements list.

POLARITY : N/A
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

0 : VSSA_SRC

Normal: sensor switching between Vssio and Cmod. For non-CSD application, IDAC1 will source current.

1 : VDDA_SNK

Inverted: sensor switch between Vddio and Cmod. For non-CSD application, IDAC1 will sink current.

2 : SENSE

N/A

3 : SENSE_INV

N/A

End of enumeration elements list.

BAL_MODE : N/A
bits : 10 - 21 (12 bit)
access : read-write

Enumeration:

0 : FULL

N/A

1 : PHI1

N/A

2 : PHI2

N/A

3 : PHI1_2

N/A

End of enumeration elements list.

LEG1_MODE : N/A
bits : 16 - 33 (18 bit)
access : read-write

Enumeration:

0 : GP_STATIC

N/A

1 : GP

N/A

2 : CSD_STATIC

N/A

3 : CSD

N/A

End of enumeration elements list.

LEG2_MODE : N/A
bits : 18 - 37 (20 bit)
access : read-write

Enumeration:

0 : GP_STATIC

N/A

1 : GP

N/A

2 : CSD_STATIC

N/A

3 : CSD

N/A

End of enumeration elements list.

DSI_CTRL_EN : N/A
bits : 21 - 42 (22 bit)
access : read-write

RANGE : N/A
bits : 22 - 45 (24 bit)
access : read-write

Enumeration:

0 : IDAC_LO

N/A

1 : IDAC_MED

N/A

2 : IDAC_HI

N/A

End of enumeration elements list.

LEG1_EN : N/A
bits : 24 - 48 (25 bit)
access : read-write

LEG2_EN : N/A
bits : 25 - 50 (26 bit)
access : read-write

LEG3_EN : N/A
bits : 26 - 52 (27 bit)
access : read-write


STATUS

Status Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSD_SENSE HSCMP_OUT CSDCMP_OUT

CSD_SENSE : Only for Debug/test purpose this internal signal (sensor clock) status can be read by CPU
bits : 1 - 2 (2 bit)
access : read-only

HSCMP_OUT : Only for Debug/test purpose the output status of CSD comparator can be read by CPU
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

0 : C_LT_VREF

N/A

1 : C_GT_VREF

N/A

End of enumeration elements list.

CSDCMP_OUT : Only for Debug/test purpose the output status of CSD modulator can be read by CPU
bits : 3 - 6 (4 bit)
access : read-only


STAT_SEQ

Current Sequencer status
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT_SEQ STAT_SEQ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQ_STATE ADC_STATE

SEQ_STATE : CSD sequencer state
bits : 0 - 2 (3 bit)
access : read-only

ADC_STATE : ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started)
bits : 16 - 34 (19 bit)
access : read-only


STAT_CNTS

Current status counts
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT_CNTS STAT_CNTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM_CONV

NUM_CONV : Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles)
bits : 0 - 15 (16 bit)
access : read-only


STAT_HCNT

Current count of the HSCMP counter
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT_HCNT STAT_HCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Current value of HSCMP counter
bits : 0 - 15 (16 bit)
access : read-only


RESULT_VAL1

Result CSD/CSX accumulation counter value 1
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESULT_VAL1 RESULT_VAL1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE BAD_CONVS

VALUE : Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is high.
bits : 0 - 15 (16 bit)
access : read-only

BAD_CONVS : Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window, either because Vref was not crossed at all, or if the Vref was already crossed before the window started. This counter is reset when the sequencer is started and will saturate at 255 when more than 255 conversions are bad.
bits : 16 - 39 (24 bit)
access : read-only


RESULT_VAL2

Result CSX accumulation counter value 2
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESULT_VAL2 RESULT_VAL2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt), this counter counts when csd_sense is low.
bits : 0 - 15 (16 bit)
access : read-only


ADC_RES

ADC measurement
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_RES ADC_RES read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIN_CNT HSCMP_POL ADC_OVERFLOW ADC_ABORT

VIN_CNT : Count to source/sink Cref1 + Cref2 from Vin to Vrefhi.
bits : 0 - 15 (16 bit)
access : read-only

HSCMP_POL : Polarity used for IDACB for this last ADC result, 0= source, 1= sink
bits : 16 - 32 (17 bit)
access : read-only

ADC_OVERFLOW : This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low.
bits : 30 - 60 (31 bit)
access : read-only

ADC_ABORT : This flag is set when the ADC sequencer was aborted before tripping HSCMP.
bits : 31 - 62 (32 bit)
access : read-only


INTR

CSD Interrupt Request Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE INIT ADC_RES

SAMPLE : A normal sample is complete
bits : 1 - 2 (2 bit)
access : read-write

INIT : Coarse initialization complete or Sample initialization complete (the latter is typically ignored)
bits : 2 - 4 (3 bit)
access : read-write

ADC_RES : ADC Result ready
bits : 8 - 16 (9 bit)
access : read-write


INTR_SET

CSD Interrupt set register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR_SET INTR_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE INIT ADC_RES

SAMPLE : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write

INIT : Write with '1' to set corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write

ADC_RES : Write with '1' to set corresponding bit in interrupt request register.
bits : 8 - 16 (9 bit)
access : read-write


INTR_MASK

CSD Interrupt mask register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR_MASK INTR_MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE INIT ADC_RES

SAMPLE : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write

INIT : Mask bit for corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write

ADC_RES : Mask bit for corresponding bit in interrupt request register.
bits : 8 - 16 (9 bit)
access : read-write


INTR_MASKED

CSD Interrupt masked register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTR_MASKED INTR_MASKED read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE INIT ADC_RES

SAMPLE : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only

INIT : Logical and of corresponding request and mask bits.
bits : 2 - 4 (3 bit)
access : read-only

ADC_RES : Logical and of corresponding request and mask bits.
bits : 8 - 16 (9 bit)
access : read-only



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