Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CTRL
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-STATUS
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-COUNTER
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC_BUFF
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD_BUFF
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL0
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL1
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL2
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_SET
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASK
CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASKED
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CTRL
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-STATUS
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-COUNTER
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC_BUFF
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD_BUFF
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL0
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL1
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL2
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_SET
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASK
CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASKED
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CTRL
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-STATUS
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-COUNTER
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC_BUFF
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD_BUFF
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL0
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL1
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL2
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_SET
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASK
CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASKED
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CTRL
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-STATUS
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-COUNTER
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC_BUFF
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD_BUFF
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL0
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL1
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL2
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_SET
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASK
CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASKED
CNT[12]-CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CTRL
CNT[12]-CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-STATUS
CNT[12]-CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC
CNT[12]-CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD
CNT[12]-CNT[11]-CNT[10]-CNT[9]-CNT[8]-CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR
CNT[2]-CNT[1]-CNT[0]-PERIOD_BUFF
CNT[2]-CNT[1]-CNT[0]-INTR_MASK
CNT[2]-CNT[1]-CNT[0]-INTR_MASKED
CNT[3]-CNT[2]-CNT[1]-CNT[0]-CTRL
CNT[3]-CNT[2]-CNT[1]-CNT[0]-STATUS
CNT[3]-CNT[2]-CNT[1]-CNT[0]-COUNTER
CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC
CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC_BUFF
CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD
CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD_BUFF
CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL0
CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL1
CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL2
CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR
CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_SET
CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASK
CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASKED
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CTRL
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-STATUS
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-COUNTER
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC_BUFF
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD_BUFF
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL0
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL1
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL2
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_SET
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASK
CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASKED
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CTRL
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-STATUS
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-COUNTER
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC_BUFF
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD_BUFF
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL0
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL1
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL2
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_SET
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASK
CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASKED
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CTRL
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-STATUS
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-COUNTER
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC_BUFF
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD_BUFF
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL0
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL1
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL2
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_SET
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASK
CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASKED
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CTRL
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-STATUS
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-COUNTER
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-CC_BUFF
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-PERIOD_BUFF
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL0
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL1
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-TR_CTRL2
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_SET
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASK
CNT[7]-CNT[6]-CNT[5]-CNT[4]-CNT[3]-CNT[2]-CNT[1]-CNT[0]-INTR_MASKED
TCPWM control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER_ENABLED : Counter enables for counters 0 up to CNT_NR-1. '0': counter disabled. '1': counter enabled. Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: - the associated counter triggers in the CMD register are set to '0'. - the counter's interrupt cause fields in counter's INTR register. - the counter's status fields in counter's STATUS register.. - the counter's trigger outputs ('tr_overflow', 'tr_underflow' and 'tr_compare_match'). - the counter's line outputs ('line_out' and 'line_compl_out'). In multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register.
bits : 0 - 31 (32 bit)
access : read-write
TCPWM reload command register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER_RELOAD : Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field.
bits : 0 - 31 (32 bit)
access : read-write
Counter control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter control register
address_offset : 0x1200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x1204 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x1208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x120C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x1210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x1214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x1218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x1220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x1224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x1228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x1230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x1234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x1238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x123C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter trigger control register 1
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
TCPWM stop command register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER_STOP : Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field.
bits : 0 - 31 (32 bit)
access : read-write
Counter control register
address_offset : 0x1540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x1544 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x1548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x154C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x1550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x1554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x1558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x1560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x1564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x1568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x1570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x1574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x1578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x157C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
TCPWM start command register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER_START : Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field.
bits : 0 - 31 (32 bit)
access : read-write
Counter control register
address_offset : 0x18C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x18C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x18C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x18CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x18D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x18D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x18D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x18E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x18E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x18E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x18F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x18F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x18F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x18FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
TCPWM Counter interrupt cause register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNTER_INT : Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'.
bits : 0 - 31 (32 bit)
access : read-only
Counter control register
address_offset : 0x1C80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x1C84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x1C88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x1C8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x1C90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x1C94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x1C98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x1CA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x1CA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x1CA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x1CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x1CB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x1CB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x1CBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x2080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x2084 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x2088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x208C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x2090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x2094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x2098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x20A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x20A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x20A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x20B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x20B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x20B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x20BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter control register
address_offset : 0x24C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x24C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x24C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x24CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x24D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x24D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x24D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x24E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x24E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x24E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x24F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x24F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x24F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x24FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter buffered compare/capture register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x2940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x2944 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x2948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x294C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x2950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x2954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x2958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x2960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x2964 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x2968 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x2970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x2974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x2978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x297C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x2E00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x2E04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x2E08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x2E0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x2E10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x2E14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x2E18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x2E20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x2E24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x2E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x2E30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x2E34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x2E38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x2E3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x3300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x3304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x3308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x330C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x3310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x3314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x3318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x3320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x3324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x3328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x3330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x3334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x3338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x333C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x3840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x3844 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x3848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x384C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x3850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x3854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x3858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x3860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x3864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x3868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x3870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x3874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x3878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x387C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter control register
address_offset : 0x3DC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x3DC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x3DC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x3DCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x3DD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x3DD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x3DD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x3DE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x3DE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x3DE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x3DF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x3DF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x3DF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x3DFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter trigger control register 0
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
TCPWM control clear register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER_ENABLED : Alias of CTRL that only allows disabling of counters. A write access: '0': Does nothing. '1': Clears respective COUNTER_ENABLED field. A read access returns CTRL.COUNTER_ENABLED.
bits : 0 - 31 (32 bit)
access : read-write
Counter control register
address_offset : 0x4380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x4384 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x4388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x438C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x4390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x4394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x4398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x43A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x43A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x43A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x43B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x43B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x43B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x43BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x4980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x4984 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x4988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x498C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x4990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x4994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x4998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x49A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x49A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x49A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x49B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x49B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x49B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x49BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x4FC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x4FC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x4FC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x4FCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x4FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x4FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x4FD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x4FE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x4FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x4FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x4FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x4FF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x4FF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x4FFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x5640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x5644 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x5648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x564C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x5650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x5654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x5658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x5660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x5664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x5668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x5670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x5674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x5678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x567C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x5BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x5D00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x5D04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x5D08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x5D0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x5D10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x5D14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x5D18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x5D20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x5D24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x5D28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x5D30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x5D34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x5D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x5D3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x78C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x7A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x7B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x7BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
TCPWM control set register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER_ENABLED : Alias of CTRL that only allows enabling of counters. A write access: '0': Does nothing. '1': Sets respective COUNTER_ENABLED field. A read access returns CTRL.COUNTER_ENABLED.
bits : 0 - 31 (32 bit)
access : read-write
Counter control register
address_offset : 0x9C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0x9C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0x9C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0x9CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0x9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0x9D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0x9D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0x9E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0x9E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0x9E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0x9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0x9F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0x9F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0x9FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
TCPWM capture command register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER_CAPTURE : Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'.
bits : 0 - 31 (32 bit)
access : read-write
Counter control register
address_offset : 0xC40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0xC44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0xC48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0xC4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0xC50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0xC54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0xC58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0xC60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0xC64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0xC68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0xC70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0xC74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0xC78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0xC7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Counter control register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write
AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending switch event.
bits : 1 - 2 (2 bit)
access : read-write
PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write
PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write
GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
0 : DIVBY1
Divide by 1 (other-than-PWM_DT mode)
1 : DIVBY2
Divide by 2 (other-than-PWM_DT mode)
2 : DIVBY4
Divide by 4 (other-than-PWM_DT mode)
3 : DIVBY8
Divide by 8 (other-than-PWM_DT mode)
4 : DIVBY16
Divide by 16 (other-than-PWM_DT mode)
5 : DIVBY32
Divide by 32 (other-than-PWM_DT mode)
6 : DIVBY64
Divide by 64 (other-than-PWM_DT mode)
7 : DIVBY128
Divide by 128 (other-than-PWM_DT mode)
End of enumeration elements list.
UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : COUNT_UP
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
1 : COUNT_DOWN
Count down (to '0'). An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
2 : COUNT_UPDN1
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.
3 : COUNT_UPDN2
Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
End of enumeration elements list.
ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write
QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
0 : X1
X1 encoding (QUAD mode)
1 : X2
X2 encoding (QUAD mode)
2 : X4
X4 encoding (QUAD mode)
End of enumeration elements list.
MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : TIMER
Timer mode
2 : CAPTURE
Capture mode
3 : QUAD
Quadrature encoding mode
4 : PWM
Pulse width modulation (PWM) mode
5 : PWM_DT
PWM with deadtime insertion mode
6 : PWM_PR
Pseudo random pulse width modulation
End of enumeration elements list.
Counter status register
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only
GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only
RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only
Counter count register
address_offset : 0xF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : 16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 31 (32 bit)
access : read-write
Counter compare/capture register
address_offset : 0xF0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered compare/capture register
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Additional buffer for counter CC register.
bits : 0 - 31 (32 bit)
access : read-write
Counter period register
address_offset : 0xF14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 31 (32 bit)
access : read-write
Counter buffered period register
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 31 (32 bit)
access : read-write
Counter trigger control register 0
address_offset : 0xF20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write
COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write
RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).
bits : 8 - 19 (12 bit)
access : read-write
STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write
START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write
Counter trigger control register 1
address_offset : 0xF24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
STOP_EDGE : A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
START_EDGE : A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Any rising edge generates an event.
1 : FALLING_EDGE
Falling edge. Any falling edge generates an event.
2 : BOTH_EDGES
Rising AND falling edge. Any odd amount of edges generates an event.
3 : NO_EDGE_DET
No edge detection, use trigger as is.
End of enumeration elements list.
Counter trigger control register 2
address_offset : 0xF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : SET
Set to '1'
1 : CLEAR
Set to '0'
2 : INVERT
Invert
3 : NO_CHANGE
No Change
End of enumeration elements list.
Interrupt request register
address_offset : 0xF30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt set request register
address_offset : 0xF34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt mask register
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt masked request register
address_offset : 0xF3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.