Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
USBHOST - INTR_USBHOST_CAUSE_HI
USBHOST - INTR_USBHOST_CAUSE_MED
USBHOST - INTR_USBHOST_CAUSE_LO
USBHOST - INTR_HOST_EP_CAUSE_HI
USBHOST - INTR_HOST_EP_CAUSE_MED
USBHOST - INTR_HOST_EP_CAUSE_LO
USB Device - - Control End point EP0 Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE : This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred.
bits : 0 - 7 (8 bit)
access : read-write
USB Device LPM and PHY Test - - Power Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUSPEND : Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). Note: - This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'.
bits : 2 - 4 (3 bit)
access : read-write
DP_UP_EN : Enables the pull up on the DP. '0' : Disable. '1' : Enable.
bits : 16 - 32 (17 bit)
access : read-write
DP_BIG : Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO. '0' : The resister value is from 900 to1575Opull up on the DP. '1' : The resister value is from 1425 to 3090Opull up on the DP
bits : 17 - 34 (18 bit)
access : read-write
DP_DOWN_EN : Enables the ~15k pull down on the DP.
bits : 18 - 36 (19 bit)
access : read-write
DM_UP_EN : Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. '0' : Disable. '1' : Enable.
bits : 19 - 38 (20 bit)
access : read-write
DM_BIG : Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO. '0' : The resister value is from 900 to1575Opull up on the DM. '1' : The resister value is from 1425 to 3090Opull up on the DM
bits : 20 - 40 (21 bit)
access : read-write
DM_DOWN_EN : Enables the ~15k pull down on the DP.
bits : 21 - 42 (22 bit)
access : read-write
ENABLE_DPO : Enables the single ended receiver on D+.
bits : 28 - 56 (29 bit)
access : read-write
ENABLE_DMO : Enables the signle ended receiver on D-.
bits : 29 - 58 (30 bit)
access : read-write
USB Host Controller - - Host Control 0 Register.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOST : This bit selects an operating mode of this IP. '0' : USB Device '1' : USB Host Notes: - The operation mode does not transition to the required one immediately after it was changed using this bit. Read this bit to check that the operation mode has changed. - This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.. - Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'. * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'. * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'. * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE : This bit enables the operation of this IP. '0' : Disable USB Host '1' : Enable USB Host Note: - This bit doesn' affect the USB Device.
bits : 31 - 62 (32 bit)
access : read-write
USB Device LPM and PHY Test - - LPM Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPM_EN : LPM enable 0: Disabled, LPM token will not get a response (backward compatibility mode) 1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK) A STALL will be sent if the bLinkState is not 0001b A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below
bits : 0 - 0 (1 bit)
access : read-write
LPM_ACK_RESP : LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request 0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode 1: a LPM token will get an ACK response and the device will go to the requested low power mode
bits : 1 - 2 (2 bit)
access : read-write
NYET_EN : Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0). 0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token. 1: a LPM token will get a NYET response
bits : 2 - 4 (3 bit)
access : read-write
SUB_RESP : Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs.
bits : 4 - 8 (5 bit)
access : read-write
USB Host Controller - - Host Control 1 Register.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : This bit selects the operating clock of USB Host. '0' : Low-speed clock '1' : Full-speed clock Notes: - This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. - This bit must always be set to '1' in the USB Device mode.
bits : 0 - 0 (1 bit)
access : read-write
USTP : This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit. '0' : Normal mode. '1' : Stops the clock for the USB Host operating unit. Notes: - If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped. - This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.
bits : 1 - 2 (2 bit)
access : read-write
RST : This bit resets this IP. '0' : Releases the reset for USB Host. '1' : Resets USB Host. Notes: - This bit is initialized if ENABLE bit of the Host Control 0 Register changes from '1' to '0'. - If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'.
bits : 7 - 14 (8 bit)
access : read-write
USB Host Controller - - Host Control 2 Register.
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RETRY : If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed during the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER). * : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1' '0' : Doesn't retry token sending. '1' : Retries token sending Note: - This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
CANCEL : When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST). '0' : Continues a token. '1' : Cancels a token.
bits : 1 - 2 (2 bit)
access : read-write
SOFSTEP : If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent. If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'. '0' : An interrupt occurred due to the HOST_HFCOMP setting. '1' : An interrupt occurred. Notes: - If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit.
bits : 2 - 4 (3 bit)
access : read-write
ALIVE : This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is effective when the CLKSEL bit of the Host Conrtol 1 Register (HOST_CTL1) is '0'. If the CLKSEL bit is '1', SOF is output regardless of the setting of the ALIVE bit. '0' : SOF output. '1' : SE0 output (Keep alive)
bits : 3 - 6 (4 bit)
access : read-write
RSVD_4 : N/A
bits : 4 - 8 (5 bit)
access : read-write
RSVD_5 : N/A
bits : 5 - 10 (6 bit)
access : read-write
TTEST : Timer Test. Set this bits to '00'.
bits : 6 - 13 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x100000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x100F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host Error Status Register.
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HS : These flags indicate the status of a handshake packet to be sent or received. These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). These bits are updated when sending or receiving has been ended. HS bits change values '11' under the following condition. However, if HS bits are written except the following conditions, the values are ignored. - HS bits indicate values except '11' and write the value '11' to HS bits. Note: This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ACK
Acknowledge Packet
1 : NAK
Non-Acknowledge Packet
2 : STALL
Stall Packet
3 : NULL
Null Packet
End of enumeration elements list.
STUFF : If this bit is set to '1', it means that a bit stuffing error is detected. When this bit is '0', it means that no stuffing error is detected. If a stuffing error is detected, bit5 (Timeout) of this register is also set to '1'. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : No stuffing error. '1' : Stuffing error occurs. Note: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 2 - 4 (3 bit)
access : read-write
TGERR : If this bit is set to '1', it means that the data of this bit does not match the value of the received toggle data. When this bit is '0', it means that no toggle error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : No toggle error. '1' : Toggle error occurs. Note: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 3 - 6 (4 bit)
access : read-write
CRC : If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no CRC error is detected. If a CRC error is detected, bit5 (Timeout) of this register is also set to '1'. When this bit is '0', it means that no CRC error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : No CRC error. '1' : CRC error occurs. Note: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 4 - 8 (5 bit)
access : read-write
TOUT : If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected. When this bit is '0', it means that no error occurs. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : No timeout. '1' : Timeout occurs. Note: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 5 - 10 (6 bit)
access : read-write
RERR : When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (Timeout) of this register is also set to '1'. When this bit is '0', it means that no error occurs. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : No receive error. '1' : Maximum packet receive error. - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 6 - 12 (7 bit)
access : read-write
LSTSOF : If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that no lost SOF error is detected. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Sends SOF. '1' : SOF sending error. Note: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x105D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Start Of Frame Register
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRAME_NUMBER16 : The frame number (11b)
bits : 0 - 10 (11 bit)
access : read-only
USB Host Controller - - Host Status Register.
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSTAT : When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected. '0' : Device is disconnected. '1' : Device is connected. Notes: - This bit is initialized if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
bits : 0 - 0 (1 bit)
access : read-only
TMODE : If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'. '0' : Low-speed. '1' : Full-speed. Notes: - This bit is initialized if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
bits : 1 - 2 (2 bit)
access : read-only
SUSP : If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, the suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. Set to '1' : Suspend. Set '0' while this bit is '1' : Resume. Others : Holds the status. Notes: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). - If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. - Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running). - If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit.
bits : 2 - 4 (3 bit)
access : read-write
SOFBUSY : When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored. '0' : The SOF timer is stopped. '1' : The SOF timer is active. Notes: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). - The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit.
bits : 3 - 6 (4 bit)
access : read-write
URST : When this bit is set to '1', the USB bus is reset. This bit continues set to '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', no processing is performed.
bits : 4 - 8 (5 bit)
access : read-write
RSVD_5 : N/A
bits : 5 - 10 (6 bit)
access : read-only
RSTBUSY : This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'. '0' : USB Host isn't being reset. '1' : USB Host is being reset. Notes: - If this bit is '1', the token must't be executed. - This bit isn't set to '0' or '1' immediately evne if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'.
bits : 6 - 12 (7 bit)
access : read-only
CLKSEL_ST : This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. '0' : Low speed '1' : Full speed Note: - If this bit is different from the CLKSEL bit, The execution of the token and bus reset must be waited until the match. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
bits : 7 - 14 (8 bit)
access : read-only
HOST_ST : This bit shows whether it is USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'. '0' : USB Device '1' : USB Host Notes: - If this bit is different from the CLKSEL bit, The execution of the token must be waited until the match. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
bits : 8 - 16 (9 bit)
access : read-only
USB Device - - Oscillator lock data register
address_offset : 0x1080 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDER16 : These bits return the oscillator locking circuits adder output.
bits : 0 - 14 (15 bit)
access : read-only
USB Device - - DATA
address_offset : 0x10ABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host SOF Interrupt Frame Compare Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAMECOMP : These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token. If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'. Note: - This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x10FA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host Retry Timer Setup Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTIMER : These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing is ended. If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped.
bits : 0 - 17 (18 bit)
access : read-write
USB Host Controller - - Host Address Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : These bits are used to specify a token address. Note: - This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 0 - 6 (7 bit)
access : read-write
USB Device - - DATA
address_offset : 0x11498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host EOF Setup Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOF : These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time. Setting example: MAXPKT = 64 bytes, full-speed mode (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit Therefore, set 0x2C9. Note: - This bit is not initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 0 - 13 (14 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1198C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host Frame Setup Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAME : These bits are used to specify a frame number of SOF. Notes: - This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). - This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process.
bits : 0 - 10 (11 bit)
access : read-write
USB Device - - DATA
address_offset : 0x11E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host Token Endpoint Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDPT : These bits are used to specify an endpoint to send or receive data to or from the device. Note: - This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 0 - 3 (4 bit)
access : read-write
TKNEN : These bits send a token according to the settings. After operation has been ended, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. The settings of the TGGL and ENDPT bits are ignored when sending a SOF token. Notes: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - The PRE packet isn't supported. - Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' - Change the USB to the USB Host before writing data to this bit. - When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit. - Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt. - Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token. 1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. 2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. 3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : NONE
Sends no data.
1 : SETUP
Sends SETUP token.
2 : IN
Sends IN token.
3 : OUT
Sends OUT token.
4 : SOF
Sends SOF token.
5 : ISO_IN
Sends Isochronous IN.
6 : ISO_OUT
Sends Isochronous OUT.
7 : RSV
N/A
End of enumeration elements list.
TGGL : This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs. '0' : DATA0 '1' : DATA1 Notes: - This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'.
bits : 8 - 16 (9 bit)
access : read-write
USB Device - - Endpoint Write Address value
address_offset : 0x1210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA16 : Write Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Read Address value
address_offset : 0x1218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA16 : Read Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x1220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR16 : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 15 (16 bit)
access : read-write
USB Device - - DATA
address_offset : 0x12380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value
address_offset : 0x1250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA16 : Write Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Read Address value
address_offset : 0x1258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA16 : Read Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x1260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR16 : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 15 (16 bit)
access : read-write
USB Device - - DATA
address_offset : 0x12880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value
address_offset : 0x1290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA16 : Write Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Read Address value
address_offset : 0x1298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA16 : Read Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x12A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR16 : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 15 (16 bit)
access : read-write
USB Device - - Common Area Write Address
address_offset : 0x12B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CWA16 : Write Address for Common Area
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Write Address value
address_offset : 0x12D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA16 : Write Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Read Address value
address_offset : 0x12D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA16 : Read Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - DATA
address_offset : 0x12D84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR16 : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 15 (16 bit)
access : read-write
USB Device - - DMA Burst / Threshold Configuration
address_offset : 0x12F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_THS16 : DMA Threshold count
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT_MSB : These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.
bits : 0 - 2 (3 bit)
access : read-write
DATA_VALID : This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : DATA_ERROR
No ACK'd transactions since bit was last cleared.
1 : DATA_VALID
Indicates a transaction ended with an ACK.
End of enumeration elements list.
DATA_TOGGLE : This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value
address_offset : 0x1310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA16 : Write Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Read Address value
address_offset : 0x1318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA16 : Read Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x1320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR16 : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 15 (16 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1328C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT : These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value
address_offset : 0x1350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA16 : Write Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Read Address value
address_offset : 0x1358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA16 : Read Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x1360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR16 : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 15 (16 bit)
access : read-write
USB Device - - DATA
address_offset : 0x13798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint's control Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DISABLE
Ignore all USB traffic to this endpoint
1 : NAK_INOUT
SETUP: Accept
IN: NAK
OUT: NAK
2 : STATUS_OUT_ONLY
SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others
3 : STALL_INOUT
SETUP: Accept
IN: STALL
OUT: STALL
5 : ISO_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token
6 : STATUS_IN_ONLY
SETUP: Accept
IN: Respond with 0B data
OUT: Stall
7 : ISO_IN
SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore
8 : NAK_OUT
SETUP: Ignore
IN: Ignore
OUT: NAK
9 : ACK_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.
11 : ACK_OUT_STATUS_IN
SETUP: Accept
IN: Respond with 0B data
OUT: Accept data
12 : NAK_IN
SETUP: Ignore
IN: NAK
OUT: Ignore
13 : ACK_IN
SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore
15 : ACK_IN_STATUS_OUT
SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others
End of enumeration elements list.
ACKED_TXN : The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : ACKED_NO
No ACK'd transactions since bit was last cleared.
1 : ACKED_YES
Indicates a transaction ended with an ACK.
End of enumeration elements list.
NAK_INT_EN : When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.
bits : 5 - 10 (6 bit)
access : read-write
ERR_IN_TXN : The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.
bits : 6 - 12 (7 bit)
access : read-write
STALL : When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value
address_offset : 0x1390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA16 : Write Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Read Address value
address_offset : 0x1398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA16 : Read Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x13A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR16 : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 15 (16 bit)
access : read-write
USB Device - - DATA
address_offset : 0x13CA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value
address_offset : 0x13D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA16 : Write Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Read Address value
address_offset : 0x13D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA16 : Read Address for EP
bits : 0 - 8 (9 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x13E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR16 : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 15 (16 bit)
access : read-write
USB Device LPM and PHY Test - - LPM Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LPM_BESL : Best Effort Service Latency This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor.
bits : 0 - 3 (4 bit)
access : read-only
LPM_REMOTEWAKE : 0: Device is prohibited from initiating a remote wake 1: Device is allow to wake the host
bits : 4 - 8 (5 bit)
access : read-only
USB Device - - DATA
address_offset : 0x1418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x141BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x146D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x14BF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x15110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x15634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x15B5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x16088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x165B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x16AEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT_MSB : These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.
bits : 0 - 2 (3 bit)
access : read-write
DATA_VALID : This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : DATA_ERROR
No ACK'd transactions since bit was last cleared.
1 : DATA_VALID
Indicates a transaction ended with an ACK.
End of enumeration elements list.
DATA_TOGGLE : This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x17024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT : These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x17560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint's control Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DISABLE
Ignore all USB traffic to this endpoint
1 : NAK_INOUT
SETUP: Accept
IN: NAK
OUT: NAK
2 : STATUS_OUT_ONLY
SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others
3 : STALL_INOUT
SETUP: Accept
IN: STALL
OUT: STALL
5 : ISO_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token
6 : STATUS_IN_ONLY
SETUP: Accept
IN: Respond with 0B data
OUT: Stall
7 : ISO_IN
SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore
8 : NAK_OUT
SETUP: Ignore
IN: Ignore
OUT: NAK
9 : ACK_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.
11 : ACK_OUT_STATUS_IN
SETUP: Accept
IN: Respond with 0B data
OUT: Accept data
12 : NAK_IN
SETUP: Ignore
IN: NAK
OUT: Ignore
13 : ACK_IN
SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore
15 : ACK_IN_STATUS_OUT
SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others
End of enumeration elements list.
ACKED_TXN : The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : ACKED_NO
No ACK'd transactions since bit was last cleared.
1 : ACKED_YES
Indicates a transaction ended with an ACK.
End of enumeration elements list.
NAK_INT_EN : When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.
bits : 5 - 10 (6 bit)
access : read-write
ERR_IN_TXN : The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.
bits : 6 - 12 (7 bit)
access : read-write
STALL : When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x17AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x17FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Control End point EP0 Data Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE : This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1852C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x18A78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x18FC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1951C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x19A74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x19FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1A530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1AA94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1AFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT_MSB : These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.
bits : 0 - 2 (3 bit)
access : read-write
DATA_VALID : This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : DATA_ERROR
No ACK'd transactions since bit was last cleared.
1 : DATA_VALID
Indicates a transaction ended with an ACK.
End of enumeration elements list.
DATA_TOGGLE : This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT : These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1B568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint's control Register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DISABLE
Ignore all USB traffic to this endpoint
1 : NAK_INOUT
SETUP: Accept
IN: NAK
OUT: NAK
2 : STATUS_OUT_ONLY
SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others
3 : STALL_INOUT
SETUP: Accept
IN: STALL
OUT: STALL
5 : ISO_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token
6 : STATUS_IN_ONLY
SETUP: Accept
IN: Respond with 0B data
OUT: Stall
7 : ISO_IN
SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore
8 : NAK_OUT
SETUP: Ignore
IN: Ignore
OUT: NAK
9 : ACK_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.
11 : ACK_OUT_STATUS_IN
SETUP: Accept
IN: Respond with 0B data
OUT: Accept data
12 : NAK_IN
SETUP: Ignore
IN: NAK
OUT: Ignore
13 : ACK_IN
SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore
15 : ACK_IN_STATUS_OUT
SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others
End of enumeration elements list.
ACKED_TXN : The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : ACKED_NO
No ACK'd transactions since bit was last cleared.
1 : ACKED_YES
Indicates a transaction ended with an ACK.
End of enumeration elements list.
NAK_INT_EN : When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.
bits : 5 - 10 (6 bit)
access : read-write
ERR_IN_TXN : The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.
bits : 6 - 12 (7 bit)
access : read-write
STALL : When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1BAD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1C04C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1C3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1C5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1CB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1D0C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1D644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1DBCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1E158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1E6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1EC7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT_MSB : These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.
bits : 0 - 2 (3 bit)
access : read-write
DATA_VALID : This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : DATA_ERROR
No ACK'd transactions since bit was last cleared.
1 : DATA_VALID
Indicates a transaction ended with an ACK.
End of enumeration elements list.
DATA_TOGGLE : This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1F214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT : These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1F7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint's control Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DISABLE
Ignore all USB traffic to this endpoint
1 : NAK_INOUT
SETUP: Accept
IN: NAK
OUT: NAK
2 : STATUS_OUT_ONLY
SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others
3 : STALL_INOUT
SETUP: Accept
IN: STALL
OUT: STALL
5 : ISO_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token
6 : STATUS_IN_ONLY
SETUP: Accept
IN: Respond with 0B data
OUT: Stall
7 : ISO_IN
SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore
8 : NAK_OUT
SETUP: Ignore
IN: Ignore
OUT: NAK
9 : ACK_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.
11 : ACK_OUT_STATUS_IN
SETUP: Accept
IN: Respond with 0B data
OUT: Accept data
12 : NAK_IN
SETUP: Ignore
IN: NAK
OUT: Ignore
13 : ACK_IN
SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore
15 : ACK_IN_STATUS_OUT
SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others
End of enumeration elements list.
ACKED_TXN : The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : ACKED_NO
No ACK'd transactions since bit was last cleared.
1 : ACKED_YES
Indicates a transaction ended with an ACK.
End of enumeration elements list.
NAK_INT_EN : When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.
bits : 5 - 10 (6 bit)
access : read-write
ERR_IN_TXN : The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.
bits : 6 - 12 (7 bit)
access : read-write
STALL : When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x1FD50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - USB control 0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEVICE_ADDRESS : These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware. If USB bus reset is detected, these bits are initialized. Refer to CDT#293217.
bits : 0 - 6 (7 bit)
access : read-write
USB_ENABLE : This bit enables the device to respond to USB traffic. If USB bus reset is detected, this bit is cleared. Note: When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps. Refer to CDT#293217.
bits : 7 - 14 (8 bit)
access : read-write
USB Device LPM and PHY Test - - USB SOF, BUS RESET and EP0 Interrupt Status
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOF_INTR : Interrupt status for USB SOF
bits : 0 - 0 (1 bit)
access : read-write
BUS_RESET_INTR : Interrupt status for BUS RESET
bits : 1 - 2 (2 bit)
access : read-write
EP0_INTR : Interrupt status for EP0
bits : 2 - 4 (3 bit)
access : read-write
LPM_INTR : Interrupt status for LPM (Link Power Management, L1 entry)
bits : 3 - 6 (4 bit)
access : read-write
RESUME_INTR : Interrupt status for Resume
bits : 4 - 8 (5 bit)
access : read-write
USB Device - - Endpoint Configuration Register *1
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_DATA_RDY : Indication that Endpoint Packet Data is Ready in Main memory
bits : 0 - 0 (1 bit)
access : read-write
DMA_REQ : Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.
bits : 1 - 2 (2 bit)
access : read-write
CRC_BYPASS : Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : CRC_NORMAL
No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s
1 : CRC_BYPASS
CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s
End of enumeration elements list.
RESET_PTR : Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : RESET_KRYPTON
Do not Reset Pointer; Krypton Backward compatibility mode
1 : RESET_NORMAL
Reset Pointer; recommended value for reduction of CPU Configuration Writes.
End of enumeration elements list.
USB Device - - DATA
address_offset : 0x202F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL_EN : IN Endpoint Local Buffer Full Enable
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT_EN : Endpoint DMA Grant Enable
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER_EN : Endpoint Buffer Overflow Enable
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER_EN : Endpoint Buffer Underflow Enable
bits : 3 - 6 (4 bit)
access : read-write
ERR_INT_EN : Endpoint Error in Transaction Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write
DMA_TERMIN_EN : Endpoint DMA Terminated Enable
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL : IN Endpoint Local Buffer Full Interrupt
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT : Endpoint DMA Grant Interrupt
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER : Endpoint Buffer Overflow Interrupt
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER : Endpoint Buffer Underflow Interrupt
bits : 3 - 6 (4 bit)
access : read-write
DMA_TERMIN : Endpoint DMA Terminated Interrupt
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2089C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x20E48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA : Write Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x213F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA_MSB : Write Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Read Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x219AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA_MSB : Read Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x21F64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x22520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x22AE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Dedicated Endpoint Buffer Size Register *1
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF : Buffer size for IN Endpoints.
bits : 0 - 3 (4 bit)
access : read-write
OUT_BUF : Buffer size for OUT Endpoints.
bits : 4 - 11 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x230A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2366C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Active Indication Register *1
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP1_ACT : Indicates that Endpoint is currently active.
bits : 0 - 0 (1 bit)
access : read-write
EP2_ACT : Indicates that Endpoint is currently active.
bits : 1 - 2 (2 bit)
access : read-write
EP3_ACT : Indicates that Endpoint is currently active.
bits : 2 - 4 (3 bit)
access : read-write
EP4_ACT : Indicates that Endpoint is currently active.
bits : 3 - 6 (4 bit)
access : read-write
EP5_ACT : Indicates that Endpoint is currently active.
bits : 4 - 8 (5 bit)
access : read-write
EP6_ACT : Indicates that Endpoint is currently active.
bits : 5 - 10 (6 bit)
access : read-write
EP7_ACT : Indicates that Endpoint is currently active.
bits : 6 - 12 (7 bit)
access : read-write
EP8_ACT : Indicates that Endpoint is currently active.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - Endpoint Type (IN/OUT) Indication *1
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP1_TYP : Endpoint Type Indication.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EP_IN
IN outpoint
1 : EP_OUT
OUT outpoint
End of enumeration elements list.
EP2_TYP : Endpoint Type Indication.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : EP_IN
IN outpoint
1 : EP_OUT
OUT outpoint
End of enumeration elements list.
EP3_TYP : Endpoint Type Indication.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : EP_IN
IN outpoint
1 : EP_OUT
OUT outpoint
End of enumeration elements list.
EP4_TYP : Endpoint Type Indication.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : EP_IN
IN outpoint
1 : EP_OUT
OUT outpoint
End of enumeration elements list.
EP5_TYP : Endpoint Type Indication.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : EP_IN
IN outpoint
1 : EP_OUT
OUT outpoint
End of enumeration elements list.
EP6_TYP : Endpoint Type Indication.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : EP_IN
IN outpoint
1 : EP_OUT
OUT outpoint
End of enumeration elements list.
EP7_TYP : Endpoint Type Indication.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : EP_IN
IN outpoint
1 : EP_OUT
OUT outpoint
End of enumeration elements list.
EP8_TYP : Endpoint Type Indication.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : EP_IN
IN outpoint
1 : EP_OUT
OUT outpoint
End of enumeration elements list.
USB Device - - DATA
address_offset : 0x23C38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - USB control 1 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG_ENABLE : This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_LOCK : This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation.
bits : 1 - 2 (2 bit)
access : read-write
BUS_ACTIVITY : The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it.
bits : 2 - 4 (3 bit)
access : read-write
RSVD_3 : N/A
bits : 3 - 6 (4 bit)
access : read-write
USB Device LPM and PHY Test - - USB SOF, BUS RESET and EP0 Interrupt Set
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOF_INTR_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
BUS_RESET_INTR_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
EP0_INTR_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write
LPM_INTR_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 3 - 6 (4 bit)
access : read-write
RESUME_INTR_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 4 - 8 (5 bit)
access : read-write
USB Device - - Endpoint Configuration Register *1
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_DATA_RDY : Indication that Endpoint Packet Data is Ready in Main memory
bits : 0 - 0 (1 bit)
access : read-write
DMA_REQ : Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.
bits : 1 - 2 (2 bit)
access : read-write
CRC_BYPASS : Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : CRC_NORMAL
No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s
1 : CRC_BYPASS
CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s
End of enumeration elements list.
RESET_PTR : Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : RESET_KRYPTON
Do not Reset Pointer; Krypton Backward compatibility mode
1 : RESET_NORMAL
Reset Pointer; recommended value for reduction of CPU Configuration Writes.
End of enumeration elements list.
USB Device - - DATA
address_offset : 0x24208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL_EN : IN Endpoint Local Buffer Full Enable
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT_EN : Endpoint DMA Grant Enable
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER_EN : Endpoint Buffer Overflow Enable
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER_EN : Endpoint Buffer Underflow Enable
bits : 3 - 6 (4 bit)
access : read-write
ERR_INT_EN : Endpoint Error in Transaction Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write
DMA_TERMIN_EN : Endpoint DMA Terminated Enable
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x247DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL : IN Endpoint Local Buffer Full Interrupt
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT : Endpoint DMA Grant Interrupt
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER : Endpoint Buffer Overflow Interrupt
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER : Endpoint Buffer Underflow Interrupt
bits : 3 - 6 (4 bit)
access : read-write
DMA_TERMIN : Endpoint DMA Terminated Interrupt
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x24DB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA : Write Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x25390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA_MSB : Write Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Read Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x25970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA_MSB : Read Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x25F54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2653C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x26B28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Arbiter Configuration Register *1
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTO_MEM : Enables Auto Memory Configuration. Manual memory configuration by default.
bits : 4 - 8 (5 bit)
access : read-write
DMA_CFG : DMA Access Configuration.
bits : 5 - 11 (7 bit)
access : read-write
Enumeration:
0 : DMA_NONE
No DMA
1 : DMA_MANUAL
Manual DMA
2 : DMA_AUTO
Auto DMA
End of enumeration elements list.
CFG_CMP : Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x27118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - USB Block Clock Enable Register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSR_CLK_EN : Clock Enable for Core Logic clocked by AHB bus clock
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2770C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Arbiter Interrupt Enable *1
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP1_INTR_EN : Enables interrupt for EP1
bits : 0 - 0 (1 bit)
access : read-write
EP2_INTR_EN : Enables interrupt for EP2
bits : 1 - 2 (2 bit)
access : read-write
EP3_INTR_EN : Enables interrupt for EP3
bits : 2 - 4 (3 bit)
access : read-write
EP4_INTR_EN : Enables interrupt for EP4
bits : 3 - 6 (4 bit)
access : read-write
EP5_INTR_EN : Enables interrupt for EP5
bits : 4 - 8 (5 bit)
access : read-write
EP6_INTR_EN : Enables interrupt for EP6
bits : 5 - 10 (6 bit)
access : read-write
EP7_INTR_EN : Enables interrupt for EP7
bits : 6 - 12 (7 bit)
access : read-write
EP8_INTR_EN : Enables interrupt for EP8
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - Arbiter Interrupt Status *1
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EP1_INTR : Interrupt status for EP1
bits : 0 - 0 (1 bit)
access : read-only
EP2_INTR : Interrupt status for EP2
bits : 1 - 2 (2 bit)
access : read-only
EP3_INTR : Interrupt status for EP3
bits : 2 - 4 (3 bit)
access : read-only
EP4_INTR : Interrupt status for EP4
bits : 3 - 6 (4 bit)
access : read-only
EP5_INTR : Interrupt status for EP5
bits : 4 - 8 (5 bit)
access : read-only
EP6_INTR : Interrupt status for EP6
bits : 5 - 10 (6 bit)
access : read-only
EP7_INTR : Interrupt status for EP7
bits : 6 - 12 (7 bit)
access : read-only
EP8_INTR : Interrupt status for EP8
bits : 7 - 14 (8 bit)
access : read-only
USB Device - - DATA
address_offset : 0x27D04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Control End point EP0 Data Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE : This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - USB SIE Data Endpoints Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP1_INTR_EN : Enables interrupt for EP1
bits : 0 - 0 (1 bit)
access : read-write
EP2_INTR_EN : Enables interrupt for EP2
bits : 1 - 2 (2 bit)
access : read-write
EP3_INTR_EN : Enables interrupt for EP3
bits : 2 - 4 (3 bit)
access : read-write
EP4_INTR_EN : Enables interrupt for EP4
bits : 3 - 6 (4 bit)
access : read-write
EP5_INTR_EN : Enables interrupt for EP5
bits : 4 - 8 (5 bit)
access : read-write
EP6_INTR_EN : Enables interrupt for EP6
bits : 5 - 10 (6 bit)
access : read-write
EP7_INTR_EN : Enables interrupt for EP7
bits : 6 - 12 (7 bit)
access : read-write
EP8_INTR_EN : Enables interrupt for EP8
bits : 7 - 14 (8 bit)
access : read-write
USB Device LPM and PHY Test - - USB SOF, BUS RESET and EP0 Interrupt Mask
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOF_INTR_MASK : Set to 1 to enable interrupt corresponding to interrupt request register
bits : 0 - 0 (1 bit)
access : read-write
BUS_RESET_INTR_MASK : Set to 1 to enable interrupt corresponding to interrupt request register
bits : 1 - 2 (2 bit)
access : read-write
EP0_INTR_MASK : Set to 1 to enable interrupt corresponding to interrupt request register
bits : 2 - 4 (3 bit)
access : read-write
LPM_INTR_MASK : Set to 1 to enable interrupt corresponding to interrupt request register
bits : 3 - 6 (4 bit)
access : read-write
RESUME_INTR_MASK : Set to 1 to enable interrupt corresponding to interrupt request register
bits : 4 - 8 (5 bit)
access : read-write
USB Device - - Endpoint Configuration Register *1
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_DATA_RDY : Indication that Endpoint Packet Data is Ready in Main memory
bits : 0 - 0 (1 bit)
access : read-write
DMA_REQ : Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.
bits : 1 - 2 (2 bit)
access : read-write
CRC_BYPASS : Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : CRC_NORMAL
No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s
1 : CRC_BYPASS
CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s
End of enumeration elements list.
RESET_PTR : Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : RESET_KRYPTON
Do not Reset Pointer; Krypton Backward compatibility mode
1 : RESET_NORMAL
Reset Pointer; recommended value for reduction of CPU Configuration Writes.
End of enumeration elements list.
USB Device - - DATA
address_offset : 0x28300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL_EN : IN Endpoint Local Buffer Full Enable
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT_EN : Endpoint DMA Grant Enable
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER_EN : Endpoint Buffer Overflow Enable
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER_EN : Endpoint Buffer Underflow Enable
bits : 3 - 6 (4 bit)
access : read-write
ERR_INT_EN : Endpoint Error in Transaction Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write
DMA_TERMIN_EN : Endpoint DMA Terminated Enable
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL : IN Endpoint Local Buffer Full Interrupt
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT : Endpoint DMA Grant Interrupt
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER : Endpoint Buffer Overflow Interrupt
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER : Endpoint Buffer Underflow Interrupt
bits : 3 - 6 (4 bit)
access : read-write
DMA_TERMIN : Endpoint DMA Terminated Interrupt
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x28900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x28F04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA : Write Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA_MSB : Write Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2950C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Read Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x29B18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA_MSB : Read Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2A128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2A73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2AD54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Common Area Write Address *1
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CWA : Write Address for Common Area
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2B370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CWA_MSB : Write Address for Common Area
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2B990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2BFB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - USB SIE Data Endpoint Interrupt Status
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP1_INTR : Interrupt status for EP1
bits : 0 - 0 (1 bit)
access : read-write
EP2_INTR : Interrupt status for EP2
bits : 1 - 2 (2 bit)
access : read-write
EP3_INTR : Interrupt status for EP3
bits : 2 - 4 (3 bit)
access : read-write
EP4_INTR : Interrupt status for EP4
bits : 3 - 6 (4 bit)
access : read-write
EP5_INTR : Interrupt status for EP5
bits : 4 - 8 (5 bit)
access : read-write
EP6_INTR : Interrupt status for EP6
bits : 5 - 10 (6 bit)
access : read-write
EP7_INTR : Interrupt status for EP7
bits : 6 - 12 (7 bit)
access : read-write
EP8_INTR : Interrupt status for EP8
bits : 7 - 14 (8 bit)
access : read-write
USB Device LPM and PHY Test - - USB SOF, BUS RESET and EP0 Interrupt Masked
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOF_INTR_MASKED : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
BUS_RESET_INTR_MASKED : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
EP0_INTR_MASKED : Logical and of corresponding request and mask bits.
bits : 2 - 4 (3 bit)
access : read-only
LPM_INTR_MASKED : Logical and of corresponding request and mask bits.
bits : 3 - 6 (4 bit)
access : read-only
RESUME_INTR_MASKED : Logical and of corresponding request and mask bits.
bits : 4 - 8 (5 bit)
access : read-only
USB Device - - Endpoint Configuration Register *1
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_DATA_RDY : Indication that Endpoint Packet Data is Ready in Main memory
bits : 0 - 0 (1 bit)
access : read-write
DMA_REQ : Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.
bits : 1 - 2 (2 bit)
access : read-write
CRC_BYPASS : Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : CRC_NORMAL
No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s
1 : CRC_BYPASS
CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s
End of enumeration elements list.
RESET_PTR : Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : RESET_KRYPTON
Do not Reset Pointer; Krypton Backward compatibility mode
1 : RESET_NORMAL
Reset Pointer; recommended value for reduction of CPU Configuration Writes.
End of enumeration elements list.
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL_EN : IN Endpoint Local Buffer Full Enable
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT_EN : Endpoint DMA Grant Enable
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER_EN : Endpoint Buffer Overflow Enable
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER_EN : Endpoint Buffer Underflow Enable
bits : 3 - 6 (4 bit)
access : read-write
ERR_INT_EN : Endpoint Error in Transaction Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write
DMA_TERMIN_EN : Endpoint DMA Terminated Enable
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2C5DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL : IN Endpoint Local Buffer Full Interrupt
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT : Endpoint DMA Grant Interrupt
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER : Endpoint Buffer Overflow Interrupt
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER : Endpoint Buffer Underflow Interrupt
bits : 3 - 6 (4 bit)
access : read-write
DMA_TERMIN : Endpoint DMA Terminated Interrupt
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2CB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2CC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA : Write Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2D238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA_MSB : Write Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Read Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2D86C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA_MSB : Read Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2DEA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2E4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2EB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DMA Burst / Threshold Configuration
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_THS : DMA Threshold count
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2F164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DMA Burst / Threshold Configuration
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_THS_MSB : DMA Threshold count
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2F7AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x2FDF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT_MSB : These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.
bits : 0 - 2 (3 bit)
access : read-write
DATA_VALID : This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : DATA_ERROR
No ACK'd transactions since bit was last cleared.
1 : DATA_VALID
Indicates a transaction ended with an ACK.
End of enumeration elements list.
DATA_TOGGLE : This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.
bits : 7 - 14 (8 bit)
access : read-write
USB Device LPM and PHY Test - - Select interrupt level for each interrupt source
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOF_LVL_SEL : USB SOF Interrupt level select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : HI
High priority interrupt
1 : MED
Medium priority interrupt
2 : LO
Low priority interrupt
3 : RSVD
illegal
End of enumeration elements list.
BUS_RESET_LVL_SEL : BUS RESET Interrupt level select
bits : 2 - 5 (4 bit)
access : read-write
EP0_LVL_SEL : EP0 Interrupt level select
bits : 4 - 9 (6 bit)
access : read-write
LPM_LVL_SEL : LPM Interrupt level select
bits : 6 - 13 (8 bit)
access : read-write
RESUME_LVL_SEL : Resume Interrupt level select
bits : 8 - 17 (10 bit)
access : read-write
ARB_EP_LVL_SEL : Arbiter Endpoint Interrupt level select
bits : 14 - 29 (16 bit)
access : read-write
EP1_LVL_SEL : EP1 Interrupt level select
bits : 16 - 33 (18 bit)
access : read-write
EP2_LVL_SEL : EP2 Interrupt level select
bits : 18 - 37 (20 bit)
access : read-write
EP3_LVL_SEL : EP3 Interrupt level select
bits : 20 - 41 (22 bit)
access : read-write
EP4_LVL_SEL : EP4 Interrupt level select
bits : 22 - 45 (24 bit)
access : read-write
EP5_LVL_SEL : EP5 Interrupt level select
bits : 24 - 49 (26 bit)
access : read-write
EP6_LVL_SEL : EP6 Interrupt level select
bits : 26 - 53 (28 bit)
access : read-write
EP7_LVL_SEL : EP7 Interrupt level select
bits : 28 - 57 (30 bit)
access : read-write
EP8_LVL_SEL : EP8 Interrupt level select
bits : 30 - 61 (32 bit)
access : read-write
USB Device - - Endpoint Configuration Register *1
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_DATA_RDY : Indication that Endpoint Packet Data is Ready in Main memory
bits : 0 - 0 (1 bit)
access : read-write
DMA_REQ : Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.
bits : 1 - 2 (2 bit)
access : read-write
CRC_BYPASS : Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : CRC_NORMAL
No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s
1 : CRC_BYPASS
CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s
End of enumeration elements list.
RESET_PTR : Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : RESET_KRYPTON
Do not Reset Pointer; Krypton Backward compatibility mode
1 : RESET_NORMAL
Reset Pointer; recommended value for reduction of CPU Configuration Writes.
End of enumeration elements list.
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL_EN : IN Endpoint Local Buffer Full Enable
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT_EN : Endpoint DMA Grant Enable
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER_EN : Endpoint Buffer Overflow Enable
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER_EN : Endpoint Buffer Underflow Enable
bits : 3 - 6 (4 bit)
access : read-write
ERR_INT_EN : Endpoint Error in Transaction Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write
DMA_TERMIN_EN : Endpoint DMA Terminated Enable
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x30448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL : IN Endpoint Local Buffer Full Interrupt
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT : Endpoint DMA Grant Interrupt
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER : Endpoint Buffer Overflow Interrupt
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER : Endpoint Buffer Underflow Interrupt
bits : 3 - 6 (4 bit)
access : read-write
DMA_TERMIN : Endpoint DMA Terminated Interrupt
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x30A9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x30DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA : Write Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x310F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA_MSB : Write Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x31750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Read Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA_MSB : Read Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x31DB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x32414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x32A7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Bus Reset Count Register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUS_RST_CNT : Bus Reset Count Length
bits : 0 - 3 (4 bit)
access : read-write
USB Device - - DATA
address_offset : 0x330E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x33758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x33DCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT : These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.
bits : 0 - 7 (8 bit)
access : read-write
USB Device LPM and PHY Test - - High priority interrupt Cause register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOF_INTR : USB SOF Interrupt
bits : 0 - 0 (1 bit)
access : read-only
BUS_RESET_INTR : BUS RESET Interrupt
bits : 1 - 2 (2 bit)
access : read-only
EP0_INTR : EP0 Interrupt
bits : 2 - 4 (3 bit)
access : read-only
LPM_INTR : LPM Interrupt
bits : 3 - 6 (4 bit)
access : read-only
RESUME_INTR : Resume Interrupt
bits : 4 - 8 (5 bit)
access : read-only
ARB_EP_INTR : Arbiter Endpoint Interrupt
bits : 7 - 14 (8 bit)
access : read-only
EP1_INTR : EP1 Interrupt
bits : 8 - 16 (9 bit)
access : read-only
EP2_INTR : EP2 Interrupt
bits : 9 - 18 (10 bit)
access : read-only
EP3_INTR : EP3 Interrupt
bits : 10 - 20 (11 bit)
access : read-only
EP4_INTR : EP4 Interrupt
bits : 11 - 22 (12 bit)
access : read-only
EP5_INTR : EP5 Interrupt
bits : 12 - 24 (13 bit)
access : read-only
EP6_INTR : EP6 Interrupt
bits : 13 - 26 (14 bit)
access : read-only
EP7_INTR : EP7 Interrupt
bits : 14 - 28 (15 bit)
access : read-only
EP8_INTR : EP8 Interrupt
bits : 15 - 30 (16 bit)
access : read-only
USB Device - - Endpoint Configuration Register *1
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_DATA_RDY : Indication that Endpoint Packet Data is Ready in Main memory
bits : 0 - 0 (1 bit)
access : read-write
DMA_REQ : Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.
bits : 1 - 2 (2 bit)
access : read-write
CRC_BYPASS : Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : CRC_NORMAL
No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s
1 : CRC_BYPASS
CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s
End of enumeration elements list.
RESET_PTR : Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : RESET_KRYPTON
Do not Reset Pointer; Krypton Backward compatibility mode
1 : RESET_NORMAL
Reset Pointer; recommended value for reduction of CPU Configuration Writes.
End of enumeration elements list.
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL_EN : IN Endpoint Local Buffer Full Enable
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT_EN : Endpoint DMA Grant Enable
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER_EN : Endpoint Buffer Overflow Enable
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER_EN : Endpoint Buffer Underflow Enable
bits : 3 - 6 (4 bit)
access : read-write
ERR_INT_EN : Endpoint Error in Transaction Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write
DMA_TERMIN_EN : Endpoint DMA Terminated Enable
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x34444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL : IN Endpoint Local Buffer Full Interrupt
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT : Endpoint DMA Grant Interrupt
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER : Endpoint Buffer Overflow Interrupt
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER : Endpoint Buffer Underflow Interrupt
bits : 3 - 6 (4 bit)
access : read-write
DMA_TERMIN : Endpoint DMA Terminated Interrupt
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x34AC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA : Write Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x35140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA_MSB : Write Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x357C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Read Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA_MSB : Read Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x35E4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x364D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x36B68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x371FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x37894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x37F30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint's control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DISABLE
Ignore all USB traffic to this endpoint
1 : NAK_INOUT
SETUP: Accept
IN: NAK
OUT: NAK
2 : STATUS_OUT_ONLY
SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others
3 : STALL_INOUT
SETUP: Accept
IN: STALL
OUT: STALL
5 : ISO_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token
6 : STATUS_IN_ONLY
SETUP: Accept
IN: Respond with 0B data
OUT: Stall
7 : ISO_IN
SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore
8 : NAK_OUT
SETUP: Ignore
IN: Ignore
OUT: NAK
9 : ACK_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.
11 : ACK_OUT_STATUS_IN
SETUP: Accept
IN: Respond with 0B data
OUT: Accept data
12 : NAK_IN
SETUP: Ignore
IN: NAK
OUT: Ignore
13 : ACK_IN
SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore
15 : ACK_IN_STATUS_OUT
SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others
End of enumeration elements list.
ACKED_TXN : The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : ACKED_NO
No ACK'd transactions since bit was last cleared.
1 : ACKED_YES
Indicates a transaction ended with an ACK.
End of enumeration elements list.
NAK_INT_EN : When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.
bits : 5 - 10 (6 bit)
access : read-write
ERR_IN_TXN : The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.
bits : 6 - 12 (7 bit)
access : read-write
STALL : When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.
bits : 7 - 14 (8 bit)
access : read-write
USB Device LPM and PHY Test - - Medium priority interrupt Cause register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOF_INTR : USB SOF Interrupt
bits : 0 - 0 (1 bit)
access : read-only
BUS_RESET_INTR : BUS RESET Interrupt
bits : 1 - 2 (2 bit)
access : read-only
EP0_INTR : EP0 Interrupt
bits : 2 - 4 (3 bit)
access : read-only
LPM_INTR : LPM Interrupt
bits : 3 - 6 (4 bit)
access : read-only
RESUME_INTR : Resume Interrupt
bits : 4 - 8 (5 bit)
access : read-only
ARB_EP_INTR : Arbiter Endpoint Interrupt
bits : 7 - 14 (8 bit)
access : read-only
EP1_INTR : EP1 Interrupt
bits : 8 - 16 (9 bit)
access : read-only
EP2_INTR : EP2 Interrupt
bits : 9 - 18 (10 bit)
access : read-only
EP3_INTR : EP3 Interrupt
bits : 10 - 20 (11 bit)
access : read-only
EP4_INTR : EP4 Interrupt
bits : 11 - 22 (12 bit)
access : read-only
EP5_INTR : EP5 Interrupt
bits : 12 - 24 (13 bit)
access : read-only
EP6_INTR : EP6 Interrupt
bits : 13 - 26 (14 bit)
access : read-only
EP7_INTR : EP7 Interrupt
bits : 14 - 28 (15 bit)
access : read-only
EP8_INTR : EP8 Interrupt
bits : 15 - 30 (16 bit)
access : read-only
USB Device - - Endpoint Configuration Register *1
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_DATA_RDY : Indication that Endpoint Packet Data is Ready in Main memory
bits : 0 - 0 (1 bit)
access : read-write
DMA_REQ : Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.
bits : 1 - 2 (2 bit)
access : read-write
CRC_BYPASS : Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : CRC_NORMAL
No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s
1 : CRC_BYPASS
CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s
End of enumeration elements list.
RESET_PTR : Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : RESET_KRYPTON
Do not Reset Pointer; Krypton Backward compatibility mode
1 : RESET_NORMAL
Reset Pointer; recommended value for reduction of CPU Configuration Writes.
End of enumeration elements list.
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL_EN : IN Endpoint Local Buffer Full Enable
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT_EN : Endpoint DMA Grant Enable
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER_EN : Endpoint Buffer Overflow Enable
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER_EN : Endpoint Buffer Underflow Enable
bits : 3 - 6 (4 bit)
access : read-write
ERR_INT_EN : Endpoint Error in Transaction Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write
DMA_TERMIN_EN : Endpoint DMA Terminated Enable
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x385D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL : IN Endpoint Local Buffer Full Interrupt
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT : Endpoint DMA Grant Interrupt
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER : Endpoint Buffer Overflow Interrupt
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER : Endpoint Buffer Underflow Interrupt
bits : 3 - 6 (4 bit)
access : read-write
DMA_TERMIN : Endpoint DMA Terminated Interrupt
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x38C74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA : Write Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3931C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA_MSB : Write Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Read Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x399C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA_MSB : Read Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3A078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3A72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3ADE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3B4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3BB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Control End point EP0 Data Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE : This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred.
bits : 0 - 7 (8 bit)
access : read-write
USB Device LPM and PHY Test - - Low priority interrupt Cause register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOF_INTR : USB SOF Interrupt
bits : 0 - 0 (1 bit)
access : read-only
BUS_RESET_INTR : BUS RESET Interrupt
bits : 1 - 2 (2 bit)
access : read-only
EP0_INTR : EP0 Interrupt
bits : 2 - 4 (3 bit)
access : read-only
LPM_INTR : LPM Interrupt
bits : 3 - 6 (4 bit)
access : read-only
RESUME_INTR : Resume Interrupt
bits : 4 - 8 (5 bit)
access : read-only
ARB_EP_INTR : Arbiter Endpoint Interrupt
bits : 7 - 14 (8 bit)
access : read-only
EP1_INTR : EP1 Interrupt
bits : 8 - 16 (9 bit)
access : read-only
EP2_INTR : EP2 Interrupt
bits : 9 - 18 (10 bit)
access : read-only
EP3_INTR : EP3 Interrupt
bits : 10 - 20 (11 bit)
access : read-only
EP4_INTR : EP4 Interrupt
bits : 11 - 22 (12 bit)
access : read-only
EP5_INTR : EP5 Interrupt
bits : 12 - 24 (13 bit)
access : read-only
EP6_INTR : EP6 Interrupt
bits : 13 - 26 (14 bit)
access : read-only
EP7_INTR : EP7 Interrupt
bits : 14 - 28 (15 bit)
access : read-only
EP8_INTR : EP8 Interrupt
bits : 15 - 30 (16 bit)
access : read-only
USB Device - - Endpoint Configuration Register *1
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_DATA_RDY : Indication that Endpoint Packet Data is Ready in Main memory
bits : 0 - 0 (1 bit)
access : read-write
DMA_REQ : Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.
bits : 1 - 2 (2 bit)
access : read-write
CRC_BYPASS : Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : CRC_NORMAL
No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s
1 : CRC_BYPASS
CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s
End of enumeration elements list.
RESET_PTR : Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : RESET_KRYPTON
Do not Reset Pointer; Krypton Backward compatibility mode
1 : RESET_NORMAL
Reset Pointer; recommended value for reduction of CPU Configuration Writes.
End of enumeration elements list.
USB Device - - DATA
address_offset : 0x3C224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL_EN : IN Endpoint Local Buffer Full Enable
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT_EN : Endpoint DMA Grant Enable
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER_EN : Endpoint Buffer Overflow Enable
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER_EN : Endpoint Buffer Underflow Enable
bits : 3 - 6 (4 bit)
access : read-write
ERR_INT_EN : Endpoint Error in Transaction Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write
DMA_TERMIN_EN : Endpoint DMA Terminated Enable
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - Endpoint Interrupt Enable Register *1
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IN_BUF_FULL : IN Endpoint Local Buffer Full Interrupt
bits : 0 - 0 (1 bit)
access : read-write
DMA_GNT : Endpoint DMA Grant Interrupt
bits : 1 - 2 (2 bit)
access : read-write
BUF_OVER : Endpoint Buffer Overflow Interrupt
bits : 2 - 4 (3 bit)
access : read-write
BUF_UNDER : Endpoint Buffer Underflow Interrupt
bits : 3 - 6 (4 bit)
access : read-write
DMA_TERMIN : Endpoint DMA Terminated Interrupt
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3C8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3CFB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA : Write Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Write Address value *1
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WA_MSB : Write Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3D688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3D6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Read Address for EP
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Read Address value *1
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA_MSB : Read Address for EP
bits : 0 - 0 (1 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3DD5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint Data Register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3E434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3EB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3F1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3F8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x3FFBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Control End point EP0 Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE : This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - USBIO Control 0 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD : Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0' and USB doesn't transmit. This bit is valid if USB Device. If D+=D- (SE0), this value is undefined.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : DIFF_LOW
D+ < D- (K state)
1 : DIFF_HIGH
D+ > D- (J state)
End of enumeration elements list.
TD : Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1.
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : DIFF_K
Force USB K state (D+ is low D- is high).
1 : DIFF_J
Force USB J state (D+ is high D- is low).
End of enumeration elements list.
TSE0 : Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0.
bits : 6 - 12 (7 bit)
access : read-write
TEN : USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus.
bits : 7 - 14 (8 bit)
access : read-write
USB Host Controller - - Host Endpoint 1 Control Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKS1 : This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100. - If automatic buffer transfer mode (DMEA='1') is used, this Endpoint must not set from 0 to 2.
bits : 0 - 8 (9 bit)
access : read-write
NULLE : When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. '0' : Releases the NULL automatic transfer mode. '1' : Sets the NULL automatic transfer mode. Note : - For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication.
bits : 10 - 20 (11 bit)
access : read-write
DMAE : This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. '0' : Releases the automatic buffer transfer mode. '1' : Sets the automatic buffer transfer mode. Note : - The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR).
bits : 11 - 22 (12 bit)
access : read-write
DIR : This bit specifies the transfer direction the Endpoint support. '0' : IN Endpoint. '1' : OUT Endpoint Note: - This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'.
bits : 12 - 24 (13 bit)
access : read-write
BFINI : This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. '0' : Clears the initialization. '1' : Initializes the send/receive buffer Note : - The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits.
bits : 15 - 30 (16 bit)
access : read-write
USB Host Controller - - Host Endpoint 1 Status Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SIZE1 : These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished. The indication range is from 0x000 to 0x100. Note : - These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect.
bits : 0 - 8 (9 bit)
access : read-only
VAL_DATA : This bit shows that there is valid data in the EP1 buffer. '0' : Invalid data in the buffer '1' : Valid data in the buffer
bits : 16 - 32 (17 bit)
access : read-only
INI_ST : This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'. '0' : Release of the initialization '1' : Initialization Note: - This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'.
bits : 17 - 34 (18 bit)
access : read-only
RSVD_18 : N/A
bits : 18 - 36 (19 bit)
access : read-only
USB Device - - DATA
address_offset : 0x406A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host Endpoint 1 Data 1-Byte Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BFDT8 : Data Register for EP1. The 1-Byte data is valid.
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host Endpoint 1 Data 2-Byte Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BFDT16 : Data Register for EP1. The 2-Byte data is valid.
bits : 0 - 15 (16 bit)
access : read-write
USB Device - - DATA
address_offset : 0x40D98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4148C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x41A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x41B84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x42280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x42980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x43084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4378C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x43E98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - USBIO control 2 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD_5_0 : N/A
bits : 0 - 5 (6 bit)
access : read-only
TEST_PKT : This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated.
bits : 6 - 12 (7 bit)
access : read-write
RSVD_7 : N/A
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x445A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x44CBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x453D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x45AF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x45E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x46210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x46934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4705C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x47788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x47EB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - USBIO control 1 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMO : This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit. This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0. This bit is valid if USB Device.
bits : 0 - 0 (1 bit)
access : read-only
DPO : This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit. This bit displays the output value of D+ pin when USB transmits SE0 or data. This bit is valid if USB Device.
bits : 1 - 2 (2 bit)
access : read-only
RSVD_2 : N/A
bits : 2 - 4 (3 bit)
access : read-write
IOMODE : This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins.
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0x485EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x48D24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x49460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x49BA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4A2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4AA2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4B178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4B8C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4C01C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4C774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4CED0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4D630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4DD94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4E4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4E64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4EC68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4F3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x4FB4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - USB Dynamic reconfiguration register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DYN_CONFIG_EN : This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. Use 0 for EP1, 1 for EP2, etc.
bits : 0 - 0 (1 bit)
access : read-write
DYN_RECONFIG_EPNO : These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1.
bits : 1 - 4 (4 bit)
access : read-write
DYN_RECONFIG_RDY_STS : This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration.
bits : 4 - 8 (5 bit)
access : read-only
USB Host Controller - - Host Endpoint 2 Control Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKS2 : This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40. - If automatic buffer transfer mode (DMEA='1') is used, this Endpoint must not set from 0 to 2.
bits : 0 - 6 (7 bit)
access : read-write
NULLE : When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. '0' : Releases the NULL automatic transfer mode. '1' : Sets the NULL automatic transfer mode. Note : - For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication.
bits : 10 - 20 (11 bit)
access : read-write
DMAE : This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. '0' : Releases the automatic buffer transfer mode. '1' : Sets the automatic buffer transfer mode. Note : - The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR).
bits : 11 - 22 (12 bit)
access : read-write
DIR : This bit specifies the transfer direction the Endpoint support. '0' : IN Endpoint. '1' : OUT Endpoint Note: - This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'.
bits : 12 - 24 (13 bit)
access : read-write
BFINI : This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. '0' : Clears the initialization. '1' : Initializes the send/receive buffer Note : - The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits.
bits : 15 - 30 (16 bit)
access : read-write
USB Device - - DATA
address_offset : 0x502C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host Endpoint 2 Status Register
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SIZE2 : These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished. The indication range is from 0x000 to 0x40. Note : - These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect.
bits : 0 - 6 (7 bit)
access : read-only
VAL_DATA : This bit shows that there is valid data in the EP2 buffer. '0' : Invalid data in the buffer '1' : Valid data in the buffer
bits : 16 - 32 (17 bit)
access : read-only
INI_ST : This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'. '0' : Release of the initialization '1' : Initialization Note: - This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'.
bits : 17 - 34 (18 bit)
access : read-only
RSVD_18 : N/A
bits : 18 - 36 (19 bit)
access : read-only
USB Host Controller - - Host Endpoint 2 Data 1-Byte Register
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BFDT8 : Data Register for EP2. The 1-Byte data is valid.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x50A40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host Endpoint 2 Data 2-Byte Register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BFDT16 : Data Register for EP2. The 2-Byte data is valid.
bits : 0 - 15 (16 bit)
access : read-write
USB Device - - DATA
address_offset : 0x511C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x51944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x520CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x52858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x52AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x52FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5377C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x53F14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Control End point EP0 Data Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE : This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x546B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x54E50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x555F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x55D9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x56548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x56CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x56F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x574AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x57C64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x58420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x58BE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x593A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x59B6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5A338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5AB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5B2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5B48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5BAB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5C290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5CA70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5D254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5DA3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5E228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5EA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5F20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5F9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x5FA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Start Of Frame Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRAME_NUMBER : It has the lower 8 bits [7:0] of the SOF frame number.
bits : 0 - 7 (8 bit)
access : read-only
USB Device - - DATA
address_offset : 0x60200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x60A00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x61204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x61A0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x62218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x62A28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6323C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x63A54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x63F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Start Of Frame Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRAME_NUMBER_MSB : It has the upper 3 bits [10:8] of the SOF frame number.
bits : 0 - 2 (3 bit)
access : read-only
USB Device - - DATA
address_offset : 0x64270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x64A90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x652B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x65ADC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x66308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x66B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6736C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x67BA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x683E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x68C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x69464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x69CAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6A4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6AD48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6B59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6BDF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6C650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6CEB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6D714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6DF7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6E7E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6F058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x6F8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Control End point EP0 Data Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE : This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT_MSB : These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.
bits : 0 - 2 (3 bit)
access : read-write
DATA_VALID : This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : DATA_ERROR
No ACK'd transactions since bit was last cleared.
1 : DATA_VALID
Indicates a transaction ended with an ACK.
End of enumeration elements list.
DATA_TOGGLE : This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.
bits : 7 - 14 (8 bit)
access : read-write
USB Device LPM and PHY Test - - DFT control
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDFT_OUT_SEL : DDFT output select signal
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : OFF
Nothing connected, output 0
1 : DP_SE
Single Ended output of DP
2 : DM_SE
Single Ended output of DM
3 : TXOE
Output Enable
4 : RCV_DF
Differential Receiver output
5 : GPIO_DP_OUT
GPIO output of DP
6 : GPIO_DM_OUT
GPIO output of DM
End of enumeration elements list.
DDFT_IN_SEL : DDFT input select signal
bits : 3 - 7 (5 bit)
access : read-write
Enumeration:
0 : OFF
Nothing connected, output 0
1 : GPIO_DP_IN
GPIO input of DP
2 : GPIO_DM_IN
GPIO input of DM
End of enumeration elements list.
USB Device - - DATA
address_offset : 0x70144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x709C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x71240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x71AC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7234C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x72BD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x73468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x73CFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT : These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x74594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x74E30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x756D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x757C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x75F74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7681C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x770C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x77978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint's control Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DISABLE
Ignore all USB traffic to this endpoint
1 : NAK_INOUT
SETUP: Accept
IN: NAK
OUT: NAK
2 : STATUS_OUT_ONLY
SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others
3 : STALL_INOUT
SETUP: Accept
IN: STALL
OUT: STALL
5 : ISO_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token
6 : STATUS_IN_ONLY
SETUP: Accept
IN: Respond with 0B data
OUT: Stall
7 : ISO_IN
SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore
8 : NAK_OUT
SETUP: Ignore
IN: Ignore
OUT: NAK
9 : ACK_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.
11 : ACK_OUT_STATUS_IN
SETUP: Accept
IN: Respond with 0B data
OUT: Accept data
12 : NAK_IN
SETUP: Ignore
IN: NAK
OUT: Ignore
13 : ACK_IN
SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore
15 : ACK_IN_STATUS_OUT
SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others
End of enumeration elements list.
ACKED_TXN : The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : ACKED_NO
No ACK'd transactions since bit was last cleared.
1 : ACKED_YES
Indicates a transaction ended with an ACK.
End of enumeration elements list.
NAK_INT_EN : When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.
bits : 5 - 10 (6 bit)
access : read-write
ERR_IN_TXN : The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.
bits : 6 - 12 (7 bit)
access : read-write
STALL : When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7822C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x78AE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x793A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x79C60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x79E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7A524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7ADEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7B6B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7BF88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7C85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7D134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7DA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7E2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7E58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7EBD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7F4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x7FDA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device LPM and PHY Test - - USB IO Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DM_P : The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : OFF
Mode 0: Output buffer off (high Z). Input buffer off.
1 : INPUT
Mode 1: Output buffer off (high Z). Input buffer on.
Other values, not supported.
End of enumeration elements list.
DM_M : The GPIO Drive Mode for DM IO pad.
bits : 3 - 8 (6 bit)
access : read-write
USB Device - - Oscillator lock data register 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDER : These bits return the lower 8 bits of the oscillator locking circuits adder output.
bits : 0 - 7 (8 bit)
access : read-only
USB Device - - DATA
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host Interrupt Level 1 Selection Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFIRQ_SEL : These bits assign SOFIRQ interrupt flag to any interrupt signals.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : HI
High priority interrupt
1 : MED
Medium priority interrupt
2 : LO
Low priority interrupt
3 : RSVD
illegal
End of enumeration elements list.
DIRQ_SEL : These bits assign DIRQ interrupt flag to any interrupt signals.
bits : 2 - 5 (4 bit)
access : read-write
CNNIRQ_SEL : These bits assign CNNIRQ interrupt flag to any interrupt signals.
bits : 4 - 9 (6 bit)
access : read-write
CMPIRQ_SEL : These bits assign URIRQ interrupt flag to any interrupt signals.
bits : 6 - 13 (8 bit)
access : read-write
URIRQ_SEL : These bits assign URIRQ interrupt flag to any interrupt signals.
bits : 8 - 17 (10 bit)
access : read-write
RWKIRQ_SEL : These bits assign RWKIRQ interrupt flag to any interrupt signals.
bits : 10 - 21 (12 bit)
access : read-write
RSVD_13_12 : N/A
bits : 12 - 25 (14 bit)
access : read-write
TCAN_SEL : These bits assign TCAN interrupt flag to any interrupt signals.
bits : 14 - 29 (16 bit)
access : read-write
USB Host Controller - - Host Interrupt Level 2 Selection Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP1_DRQ_SEL : These bits assign EP1_DRQ interrupt flag to any interrupt signals.
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
0 : HI
High priority interrupt
1 : MED
Medium priority interrupt
2 : LO
Low priority interrupt
3 : RSVD
illegal
End of enumeration elements list.
EP1_SPK_SEL : These bits assign EP1_SPK interrupt flag to any interrupt signals.
bits : 6 - 13 (8 bit)
access : read-write
EP2_DRQ_SEL : These bits assign EP2_DRQ interrupt flag to any interrupt signals.
bits : 8 - 17 (10 bit)
access : read-write
EP2_SPK_SEL : These bits assign EP2_SPK interrupt flag to any interrupt signals.
bits : 10 - 21 (12 bit)
access : read-write
USB Device - - DATA
address_offset : 0x80698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x80F8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x81884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x82180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x82A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x82CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x83384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x83C8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Oscillator lock data register 1
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDER_MSB : These bits return the upper 7 bits of the oscillator locking circuits adder output.
bits : 0 - 6 (7 bit)
access : read-only
USB Device - - DATA
address_offset : 0x84598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x84EA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x857BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x860D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x869F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x87310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x87C34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8855C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x88E88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x897B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8A0EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8AA24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8B360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8BC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8BCA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8C5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8CF2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8D878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8E1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8EB1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8F474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x8FDD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Cause High Register
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOFIRQ_INT : SOFIRQ interrupt
bits : 0 - 0 (1 bit)
access : read-only
DIRQ_INT : DIRQ interrupt
bits : 1 - 2 (2 bit)
access : read-only
CNNIRQ_INT : CNNIRQ interrupt
bits : 2 - 4 (3 bit)
access : read-only
CMPIRQ_INT : CMPIRQ interrupt
bits : 3 - 6 (4 bit)
access : read-only
URIRQ_INT : URIRQ interrupt
bits : 4 - 8 (5 bit)
access : read-only
RWKIRQ_INT : RWKIRQ interrupt
bits : 5 - 10 (6 bit)
access : read-only
RSVD_6 : N/A
bits : 6 - 12 (7 bit)
access : read-only
TCAN_INT : TCAN interrupt
bits : 7 - 14 (8 bit)
access : read-only
USB Host Controller - - Interrupt USB Host Cause Medium Register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOFIRQ_INT : SOFIRQ interrupt
bits : 0 - 0 (1 bit)
access : read-only
DIRQ_INT : DIRQ interrupt
bits : 1 - 2 (2 bit)
access : read-only
CNNIRQ_INT : CNNIRQ interrupt
bits : 2 - 4 (3 bit)
access : read-only
CMPIRQ_INT : CMPIRQ interrupt
bits : 3 - 6 (4 bit)
access : read-only
URIRQ_INT : URIRQ interrupt
bits : 4 - 8 (5 bit)
access : read-only
RWKIRQ_INT : RWKIRQ interrupt
bits : 5 - 10 (6 bit)
access : read-only
RSVD_6 : N/A
bits : 6 - 12 (7 bit)
access : read-only
TCAN_INT : TCAN interrupt
bits : 7 - 14 (8 bit)
access : read-only
USB Device - - DATA
address_offset : 0x9040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x90730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Cause Low Register
address_offset : 0x908 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOFIRQ_INT : SOFIRQ interrupt
bits : 0 - 0 (1 bit)
access : read-only
DIRQ_INT : DIRQ interrupt
bits : 1 - 2 (2 bit)
access : read-only
CNNIRQ_INT : CNNIRQ interrupt
bits : 2 - 4 (3 bit)
access : read-only
CMPIRQ_INT : CMPIRQ interrupt
bits : 3 - 6 (4 bit)
access : read-only
URIRQ_INT : URIRQ interrupt
bits : 4 - 8 (5 bit)
access : read-only
RWKIRQ_INT : RWKIRQ interrupt
bits : 5 - 10 (6 bit)
access : read-only
RSVD_6 : N/A
bits : 6 - 12 (7 bit)
access : read-only
TCAN_INT : TCAN interrupt
bits : 7 - 14 (8 bit)
access : read-only
USB Device - - DATA
address_offset : 0x91094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x919FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Endpoint Cause High Register
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EP1DRQ_INT : EP1DRQ interrupt
bits : 2 - 4 (3 bit)
access : read-only
EP1SPK_INT : EP1SPK interrupt
bits : 3 - 6 (4 bit)
access : read-only
EP2DRQ_INT : EP2DRQ interrupt
bits : 4 - 8 (5 bit)
access : read-only
EP2SPK_INT : EP2SPK interrupt
bits : 5 - 10 (6 bit)
access : read-only
USB Device - - DATA
address_offset : 0x92368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Endpoint Cause Medium Register
address_offset : 0x924 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EP1DRQ_INT : EP1DRQ interrupt
bits : 2 - 4 (3 bit)
access : read-only
EP1SPK_INT : EP1SPK interrupt
bits : 3 - 6 (4 bit)
access : read-only
EP2DRQ_INT : EP2DRQ interrupt
bits : 4 - 8 (5 bit)
access : read-only
EP2SPK_INT : EP2SPK interrupt
bits : 5 - 10 (6 bit)
access : read-only
USB Host Controller - - Interrupt USB Host Endpoint Cause Low Register
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EP1DRQ_INT : EP1DRQ interrupt
bits : 2 - 4 (3 bit)
access : read-only
EP1SPK_INT : EP1SPK interrupt
bits : 3 - 6 (4 bit)
access : read-only
EP2DRQ_INT : EP2DRQ interrupt
bits : 4 - 8 (5 bit)
access : read-only
EP2SPK_INT : EP2SPK interrupt
bits : 5 - 10 (6 bit)
access : read-only
USB Device - - DATA
address_offset : 0x92CD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9364C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x93FC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Register
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFIRQ : If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Does not issue an interrupt request by starting a SOF token. '1' : Issues an interrupt request by starting a SOF token. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
DIRQ : If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by detecting a device disconnection. '1' : Issues an interrupt request by detecting a device disconnection. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 1 - 2 (2 bit)
access : read-write
CNNIRQ : If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by detecting a device connection. '1' : Issues an interrupt request by detecting a device connection. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 2 - 4 (3 bit)
access : read-write
CMPIRQ : If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by token completion. '1' : Issues an interrupt request by token completion. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'. - Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token. 1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. 2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. 3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'.
bits : 3 - 6 (4 bit)
access : read-write
URIRQ : If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by USB bus resetting. '1' : Issues an interrupt request by USB bus resetting. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 4 - 8 (5 bit)
access : read-write
RWKIRQ : If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by restart. '1' : Issues an interrupt request by restart. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 5 - 10 (6 bit)
access : read-write
RSVD_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
TCAN : If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Does not cancel token sending. '1' : Cancels token sending. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
bits : 7 - 14 (8 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Set Register
address_offset : 0x944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFIRQS : This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
bits : 0 - 0 (1 bit)
access : read-write
DIRQS : This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
bits : 1 - 2 (2 bit)
access : read-write
CNNIRQS : This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
bits : 2 - 4 (3 bit)
access : read-write
CMPIRQS : This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
bits : 3 - 6 (4 bit)
access : read-write
URIRQS : This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
bits : 4 - 8 (5 bit)
access : read-write
RWKIRQS : This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
bits : 5 - 10 (6 bit)
access : read-write
RSVD_6 : BCNFTEST interrupt. This bit is test bit
bits : 6 - 12 (7 bit)
access : read-write
TCANS : This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored.
bits : 7 - 14 (8 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Mask Register
address_offset : 0x948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFIRQM : This bit masks the interrupt by SOF flag. '0' : Disables '1' : Enables
bits : 0 - 0 (1 bit)
access : read-write
DIRQM : This bit masks the interrupt by DIRQ flag. '0' : Disables '1' : Enables
bits : 1 - 2 (2 bit)
access : read-write
CNNIRQM : This bit masks the interrupt by CNNIRQ flag. '0' : Disables '1' : Enables
bits : 2 - 4 (3 bit)
access : read-write
CMPIRQM : This bit masks the interrupt by CMPIRQ flag. '0' : Disables '1' : Enables
bits : 3 - 6 (4 bit)
access : read-write
URIRQM : This bit masks the interrupt by URIRQ flag. '0' : Disables '1' : Enables
bits : 4 - 8 (5 bit)
access : read-write
RWKIRQM : This bit masks the interrupt by RWKIRQ flag. '0' : Disables '1' : Enables
bits : 5 - 10 (6 bit)
access : read-write
RSVD_6 : N/A
bits : 6 - 12 (7 bit)
access : read-write
TCANM : This bit masks the interrupt by TCAN flag. '0' : Disables '1' : Enables
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x94940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Masked Register
address_offset : 0x94C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOFIRQED : This bit indicates the interrupt by SOF flag. '0' : Doesn't request the interrupt by SOF '1' : Request the interrupt by SOF
bits : 0 - 0 (1 bit)
access : read-only
DIRQED : This bit indicates the interrupt by DIRQ flag. '0' : Doesn't request the interrupt by DIRQ '1' : Request the interrupt by DIRQ
bits : 1 - 2 (2 bit)
access : read-only
CNNIRQED : This bit indicates the interrupt by CNNIRQ flag. '0' : Doesn't request the interrupt by CNNIRQ '1' : Request the interrupt by CNNIRQ
bits : 2 - 4 (3 bit)
access : read-only
CMPIRQED : This bit indicates the interrupt by CMPIRQ flag. '0' : Doesn't request the interrupt by CMPIRQ '1' : Request the interrupt by CMPIRQ
bits : 3 - 6 (4 bit)
access : read-only
URIRQED : This bit indicates the interrupt by URIRQ flag. '0' : Doesn't request the interrupt by URIRQ '1' : Request the interrupt by URIRQ
bits : 4 - 8 (5 bit)
access : read-only
RWKIRQED : This bit indicates the interrupt by RWKIRQ flag. '0' : Doesn't request the interrupt by RWKIRQ '1' : Request the interrupt by RWKIRQ
bits : 5 - 10 (6 bit)
access : read-only
RSVD_6 : N/A
bits : 6 - 12 (7 bit)
access : read-only
TCANED : This bit indicates the interrupt by TCAN flag. '0' : Doesn't request the interrupt by TCAN '1' : Request the interrupt by TCAN
bits : 7 - 14 (8 bit)
access : read-only
USB Device - - DATA
address_offset : 0x94C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x952C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x95C44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x965CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x96F58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x978E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9827C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x98C14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x994C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x995B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x99F50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9A8F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9B29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9BC48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9C5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9CFAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9D964 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9DD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9E320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9ECE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0x9F6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint0 control Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DISABLE
Ignore all USB traffic to this endpoint
1 : NAK_INOUT
SETUP: Accept
IN: NAK
OUT: NAK
2 : STATUS_OUT_ONLY
SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others
3 : STALL_INOUT
SETUP: Accept
IN: STALL
OUT: STALL
5 : ISO_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token
6 : STATUS_IN_ONLY
SETUP: Accept
IN: Respond with 0B data
OUT: Stall
7 : ISO_IN
SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore
8 : NAK_OUT
SETUP: Ignore
IN: Ignore
OUT: NAK
9 : ACK_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.
11 : ACK_OUT_STATUS_IN
SETUP: Accept
IN: Respond with 0B data
OUT: Accept data
12 : NAK_IN
SETUP: Ignore
IN: NAK
OUT: Ignore
13 : ACK_IN
SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore
15 : ACK_IN_STATUS_OUT
SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others
End of enumeration elements list.
ACKED_TXN : The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : ACKED_NO
No ACK'd transactions since bit was last cleared.
1 : ACKED_YES
Indicates a transaction ended with an ACK.
End of enumeration elements list.
OUT_RCVD : When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register.
bits : 5 - 10 (6 bit)
access : read-write
IN_RCVD : When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register.
bits : 6 - 12 (7 bit)
access : read-write
SETUP_RCVD : When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register.
bits : 7 - 14 (8 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Endpoint Register
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP1DRQ : This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. '0' : Clears the interrupt cause '1' : Packet transfer normally ended Note : - If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written.
bits : 2 - 4 (3 bit)
access : read-write
EP1SPK : This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. '0' : Received data size satisfies the maximum packet size '1' : Received data size does not satisfy the maximum packet size Note : - The SPK bit is not set during data transfer in the OUT direction.
bits : 3 - 6 (4 bit)
access : read-write
EP2DRQ : This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. '0' : Clears the interrupt cause '1' : Packet transfer normally ended Note : - If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written.
bits : 4 - 8 (5 bit)
access : read-write
EP2SPK : This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. '0' : Received data size satisfies the maximum packet size '1' : Received data size does not satisfy the maximum packet size Note : - The SPK bit is not set during data transfer in the OUT direction.
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA006C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Endpoint Set Register
address_offset : 0xA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP1DRQS : This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'.
bits : 2 - 4 (3 bit)
access : read-write
EP1SPKS : This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'.
bits : 3 - 6 (4 bit)
access : read-write
EP2DRQS : This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'.
bits : 4 - 8 (5 bit)
access : read-write
EP2SPKS : This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'.
bits : 5 - 10 (6 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Endpoint Mask Register
address_offset : 0xA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP1DRQM : This bit masks the interrupt by EP1DRQ flag. '0' : Disables '1' : Enables
bits : 2 - 4 (3 bit)
access : read-write
EP1SPKM : This bit masks the interrupt by EP1SPK flag. '0' : Disables '1' : Enables
bits : 3 - 6 (4 bit)
access : read-write
EP2DRQM : This bit masks the interrupt by EP2DRQ flag. '0' : Disables '1' : Enables
bits : 4 - 8 (5 bit)
access : read-write
EP2SPKM : This bit masks the interrupt by EP2SPK flag. '0' : Disables '1' : Enables
bits : 5 - 10 (6 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA0A38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Interrupt USB Host Endpoint Masked Register
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EP1DRQED : This bit indicates the interrupt by EP1DRQ flag. '0' : Doesn't request the interrupt by EP1DRQ '1' : Request the interrupt by EP1DRQ
bits : 2 - 4 (3 bit)
access : read-only
EP1SPKED : This bit indicates the interrupt by EP1SPK flag. '0' : Doesn't request the interrupt by EP1SPK '1' : Request the interrupt by EP1SPK
bits : 3 - 6 (4 bit)
access : read-only
EP2DRQED : This bit indicates the interrupt by EP2DRQ flag. '0' : Doesn't request the interrupt by EP2DRQ '1' : Request the interrupt by EP2DRQ
bits : 4 - 8 (5 bit)
access : read-only
EP2SPKED : This bit indicates the interrupt by EP2SPK flag. '0' : Doesn't request the interrupt by EP2SPK '1' : Request the interrupt by EP2SPK
bits : 5 - 10 (6 bit)
access : read-only
USB Device - - DATA
address_offset : 0xA1408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA1DDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA27B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA3190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA3B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Endpoint0 count Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYTE_COUNT : These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10.
bits : 0 - 3 (4 bit)
access : read-write
DATA_VALID : This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : DATA_ERROR
No ACK'd transactions since bit was last cleared.
1 : DATA_VALID
Indicates a transaction ended with an ACK.
End of enumeration elements list.
DATA_TOGGLE : This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA4554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA4F3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA5928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA6318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA6D0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA6FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA7704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA8100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA8B00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA9504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xA9F0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xAA918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xAB328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xAB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xABD3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xAC754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xAD170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xADB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xAE5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xAEFDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xAFA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT_MSB : These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.
bits : 0 - 2 (3 bit)
access : read-write
DATA_VALID : This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : DATA_ERROR
No ACK'd transactions since bit was last cleared.
1 : DATA_VALID
Indicates a transaction ended with an ACK.
End of enumeration elements list.
DATA_TOGGLE : This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.
bits : 7 - 14 (8 bit)
access : read-write
USB Host Controller - - Host DMA Enable Register
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DM_EP1DRQE : This bit enables DMA Request by EP1DRQ. '0' : Disable '1' : Enable
bits : 2 - 4 (3 bit)
access : read-write
DM_EP2DRQE : This bit enables DMA Request by EP2DRQ. '0' : Disable '1' : Enable
bits : 3 - 6 (4 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB0438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB0E6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB18A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host Endpoint 1 Block Register
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLK_NUM : Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decrement when DMAE='1'. - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1')
bits : 16 - 47 (32 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB22E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB2D20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Host Controller - - Host Endpoint 2 Block Register
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLK_NUM : Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decrement when DMAE='1'. - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1')
bits : 16 - 47 (32 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB3764 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT : These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB41AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB4BF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB5648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB609C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB6AF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB7550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB7FB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint's control Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DISABLE
Ignore all USB traffic to this endpoint
1 : NAK_INOUT
SETUP: Accept
IN: NAK
OUT: NAK
2 : STATUS_OUT_ONLY
SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others
3 : STALL_INOUT
SETUP: Accept
IN: STALL
OUT: STALL
5 : ISO_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token
6 : STATUS_IN_ONLY
SETUP: Accept
IN: Respond with 0B data
OUT: Stall
7 : ISO_IN
SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore
8 : NAK_OUT
SETUP: Ignore
IN: Ignore
OUT: NAK
9 : ACK_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.
11 : ACK_OUT_STATUS_IN
SETUP: Accept
IN: Respond with 0B data
OUT: Accept data
12 : NAK_IN
SETUP: Ignore
IN: NAK
OUT: Ignore
13 : ACK_IN
SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore
15 : ACK_IN_STATUS_OUT
SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others
End of enumeration elements list.
ACKED_TXN : The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : ACKED_NO
No ACK'd transactions since bit was last cleared.
1 : ACKED_YES
Indicates a transaction ended with an ACK.
End of enumeration elements list.
NAK_INT_EN : When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.
bits : 5 - 10 (6 bit)
access : read-write
ERR_IN_TXN : The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.
bits : 6 - 12 (7 bit)
access : read-write
STALL : When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB8A14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB947C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xB9EE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xBA958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xBB3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xBBE44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xBC8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xBD340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xBDDC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xBE1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xBE84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xBF2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xBFD68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Control End point EP0 Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_BYTE : This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred.
bits : 0 - 7 (8 bit)
access : read-write
USB Device LPM and PHY Test - - Flow Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP1_ERR_RESP : End Point 1 error response 0: do nothing (backward compatibility mode) 1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK
bits : 0 - 0 (1 bit)
access : read-write
EP2_ERR_RESP : End Point 2 error response
bits : 1 - 2 (2 bit)
access : read-write
EP3_ERR_RESP : End Point 3 error response
bits : 2 - 4 (3 bit)
access : read-write
EP4_ERR_RESP : End Point 4 error response
bits : 3 - 6 (4 bit)
access : read-write
EP5_ERR_RESP : End Point 5 error response
bits : 4 - 8 (5 bit)
access : read-write
EP6_ERR_RESP : End Point 6 error response
bits : 5 - 10 (6 bit)
access : read-write
EP7_ERR_RESP : End Point 7 error response
bits : 6 - 12 (7 bit)
access : read-write
EP8_ERR_RESP : End Point 8 error response
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC07FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC1294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC1D30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC27D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC3274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC3D1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC47C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC5278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC5D2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC67E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC72A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC7D60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC8824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC92EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xC9DB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xCA888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xCB35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xCBE34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xCC2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xCC910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xCD3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xCDED4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xCE9BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xCF4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xCFF98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD0A8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD1584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD2080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD2B80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD3684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD418C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD4C98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD57A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD62BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD6DD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD78F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD8410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD8F34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xD9A5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xDA588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xDA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xDB0B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xDBBEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xDC724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xDD260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xDDDA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xDE8E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xDF24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xDF42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xDFF78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE0AC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE161C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE2174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE2CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE3830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE4394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE4EFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE5A68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE65D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE714C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE7CC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE8840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE93C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xE9F44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xEAACC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xEB658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xEC1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xECD7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xED88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xED914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xEE4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xEF050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xEFBF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT_MSB : These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.
bits : 0 - 2 (3 bit)
access : read-write
DATA_VALID : This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : DATA_ERROR
No ACK'd transactions since bit was last cleared.
1 : DATA_VALID
Indicates a transaction ended with an ACK.
End of enumeration elements list.
DATA_TOGGLE : This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF079C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF1348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF1EF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF2AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF3664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint count register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_COUNT : These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF4220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF4DE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF59A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF656C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF7138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF7D08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - Non-control endpoint's control Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DISABLE
Ignore all USB traffic to this endpoint
1 : NAK_INOUT
SETUP: Accept
IN: NAK
OUT: NAK
2 : STATUS_OUT_ONLY
SETUP: Accept
IN: STALL
OUT: ACK 0B tokens, NAK others
3 : STALL_INOUT
SETUP: Accept
IN: STALL
OUT: STALL
5 : ISO_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept Isochronous OUT token
6 : STATUS_IN_ONLY
SETUP: Accept
IN: Respond with 0B data
OUT: Stall
7 : ISO_IN
SETUP: Ignore
IN: Accept Isochronous IN token
OUT: Ignore
8 : NAK_OUT
SETUP: Ignore
IN: Ignore
OUT: NAK
9 : ACK_OUT
SETUP: Ignore
IN: Ignore
OUT: Accept data and ACK if STALL=0, STALL otherwise.
Change to MODE=8 after one succesfull OUT token.
11 : ACK_OUT_STATUS_IN
SETUP: Accept
IN: Respond with 0B data
OUT: Accept data
12 : NAK_IN
SETUP: Ignore
IN: NAK
OUT: Ignore
13 : ACK_IN
SETUP: Ignore
IN: Respond to IN with data if STALL=0, STALL otherwise
OUT: Ignore
15 : ACK_IN_STATUS_OUT
SETUP: Accept
IN: Respond to IN with data
OUT: ACK 0B tokens, NAK others
End of enumeration elements list.
ACKED_TXN : The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : ACKED_NO
No ACK'd transactions since bit was last cleared.
1 : ACKED_YES
Indicates a transaction ended with an ACK.
End of enumeration elements list.
NAK_INT_EN : When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.
bits : 5 - 10 (6 bit)
access : read-write
ERR_IN_TXN : The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.
bits : 6 - 12 (7 bit)
access : read-write
STALL : When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.
bits : 7 - 14 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF88DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xF94B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xFA090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xFAC70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xFB854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xFC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xFC43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xFD028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xFDC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xFE80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
USB Device - - DATA
address_offset : 0xFF404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data Register for EP ; This register is linked to the memory, hence reset value is undefined
bits : 0 - 7 (8 bit)
access : read-write
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