Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
DEVICE[1]-DEVICE[0]-RD_CMD_CTL
DEVICE[1]-DEVICE[0]-RD_ADDR_CTL
DEVICE[1]-DEVICE[0]-RD_MODE_CTL
DEVICE[1]-DEVICE[0]-RD_DUMMY_CTL
DEVICE[1]-DEVICE[0]-RD_DATA_CTL
DEVICE[1]-DEVICE[0]-WR_CMD_CTL
DEVICE[1]-DEVICE[0]-WR_ADDR_CTL
DEVICE[1]-DEVICE[0]-WR_MODE_CTL
DEVICE[1]-DEVICE[0]-WR_DUMMY_CTL
DEVICE[1]-DEVICE[0]-WR_DATA_CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-ADDR
DEVICE[2]-DEVICE[1]-DEVICE[0]-MASK
DEVICE[2]-DEVICE[1]-DEVICE[0]-ADDR_CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-RD_CMD_CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-RD_ADDR_CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-RD_MODE_CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-RD_DUMMY_CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-RD_DATA_CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-WR_CMD_CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-WR_ADDR_CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-WR_MODE_CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-WR_DUMMY_CTL
DEVICE[2]-DEVICE[1]-DEVICE[0]-WR_DATA_CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-ADDR
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-MASK
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-ADDR_CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-RD_CMD_CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-RD_ADDR_CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-RD_MODE_CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-RD_DUMMY_CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-RD_DATA_CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-WR_CMD_CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-WR_ADDR_CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-WR_MODE_CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-WR_DUMMY_CTL
DEVICE[3]-DEVICE[2]-DEVICE[1]-DEVICE[0]-WR_DATA_CTL
Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XIP_MODE : Mode of operation. Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MMIO_MODE
'0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated.
1 : XIP_MODE
1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE.
End of enumeration elements list.
CLOCK_IF_RX_SEL : Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'. '0': 'spi_clk_out' (internal clock) '1': !'spi_clk_out' (internal clock) '2': 'spi_clk_in' (feedback clock) '3': !'spi_clk_in' (feedback clock) Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'.
bits : 12 - 25 (14 bit)
access : read-write
DESELECT_DELAY : Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers: '0': 1 interface clock cycle. '1': 2 interface clock cycles. '2': 3 interface clock cycles. '3': 4 interface clock cycles. '4': 5 interface clock cycles. '5': 6 interface clock cycles. '6': 7 interface clock cycles. '7': 8 interface clock cycles. During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive.
bits : 16 - 34 (19 bit)
access : read-write
BLOCK : Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE. This field is not used for test controller accesses.
bits : 24 - 48 (25 bit)
access : read-write
Enumeration:
0 : BUS_ERROR
0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency).
1 : WAIT_STATES
1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency).
End of enumeration elements list.
ENABLED : IP enable: '0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors. '1': Enabled. Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur.
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
0 : DISABLED
N/A
1 : ENABLED
N/A
End of enumeration elements list.
Slow cache control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAY : this is for debug purpose only, and should be hidden to customers in technical document
bits : 16 - 33 (18 bit)
access : read-write
SET_ADDR : this is for debug purpose only, and should be hidden to customers in technical document
bits : 24 - 49 (26 bit)
access : read-write
PREF_EN : N/A
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : N/A
bits : 31 - 62 (32 bit)
access : read-write
Slow cache command
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : Cache invalidation. SW writes a '1' to clear the cache. The cache's LRU structure is also reset to its default state.
bits : 0 - 0 (1 bit)
access : read-write
Control
address_offset : 0x1080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_EN : Write enable: '0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. '1': write transfers are allowed to this device.
bits : 0 - 0 (1 bit)
access : read-write
CRYPTO_EN : Cryptography on read/write accesses: '0': disabled. '1': enabled.
bits : 8 - 16 (9 bit)
access : read-write
DATA_SEL : Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): '0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. '1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. '2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. '3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes.
bits : 16 - 33 (18 bit)
access : read-write
ENABLED : Device enable: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Device region base address
address_offset : 0x1088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24].
bits : 8 - 39 (32 bit)
access : read-write
Device region mask
address_offset : 0x108C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. Note: a transfer request that is not in any device region results in an AHB-Lite bus error.
bits : 8 - 39 (32 bit)
access : read-write
Address control
address_offset : 0x10A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE2 : Specifies the size of the XIP device address in Bytes: '0': 1 Byte address. '1': 2 Byte address. '2': 3 Byte address. '3': 4 Byte address. The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.
bits : 0 - 1 (2 bit)
access : read-write
DIV2 : Specifies if the AHB-Lite bus transfer address is divided by 2 or not: '0': No divide by 2. '1': Divide by 2. This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.
bits : 8 - 16 (9 bit)
access : read-write
Read command control
address_offset : 0x10C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Command byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of data transfer: '0': 1 bit/cycle (single data transfer). '1': 2 bits/cycle (dual data transfer). '2': 4 bits/cycle (quad data transfer). '3': 8 bits/cycle (octal data transfer).
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of command field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read address control
address_offset : 0x10C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Read mode control
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Mode byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of mode field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read dummy control
address_offset : 0x10CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE5 : Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes!
bits : 0 - 4 (5 bit)
access : read-write
PRESENT : Presence of dummy cycles: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read data control
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Write command control
address_offset : 0x10E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Command byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of command field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write address control
address_offset : 0x10E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Write mode control
address_offset : 0x10E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Mode byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of mode field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write dummy control
address_offset : 0x10EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE5 : Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles.
bits : 0 - 4 (5 bit)
access : read-write
PRESENT : Presence of dummy cycles: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write data control
address_offset : 0x10F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Fast cache control
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAY : this is for debug purpose only, and should be hidden to customers in technical document
bits : 16 - 33 (18 bit)
access : read-write
SET_ADDR : this is for debug purpose only, and should be hidden to customers in technical document
bits : 24 - 49 (26 bit)
access : read-write
PREF_EN : N/A
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : N/A
bits : 31 - 62 (32 bit)
access : read-write
Fast cache command
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : See SLOW_CA_CMD.INV.
bits : 0 - 0 (1 bit)
access : read-write
Control
address_offset : 0x1980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_EN : Write enable: '0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. '1': write transfers are allowed to this device.
bits : 0 - 0 (1 bit)
access : read-write
CRYPTO_EN : Cryptography on read/write accesses: '0': disabled. '1': enabled.
bits : 8 - 16 (9 bit)
access : read-write
DATA_SEL : Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): '0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. '1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. '2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. '3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes.
bits : 16 - 33 (18 bit)
access : read-write
ENABLED : Device enable: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Device region base address
address_offset : 0x1988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24].
bits : 8 - 39 (32 bit)
access : read-write
Device region mask
address_offset : 0x198C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. Note: a transfer request that is not in any device region results in an AHB-Lite bus error.
bits : 8 - 39 (32 bit)
access : read-write
Address control
address_offset : 0x19A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE2 : Specifies the size of the XIP device address in Bytes: '0': 1 Byte address. '1': 2 Byte address. '2': 3 Byte address. '3': 4 Byte address. The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.
bits : 0 - 1 (2 bit)
access : read-write
DIV2 : Specifies if the AHB-Lite bus transfer address is divided by 2 or not: '0': No divide by 2. '1': Divide by 2. This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.
bits : 8 - 16 (9 bit)
access : read-write
Read command control
address_offset : 0x19C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Command byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of data transfer: '0': 1 bit/cycle (single data transfer). '1': 2 bits/cycle (dual data transfer). '2': 4 bits/cycle (quad data transfer). '3': 8 bits/cycle (octal data transfer).
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of command field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read address control
address_offset : 0x19C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Read mode control
address_offset : 0x19C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Mode byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of mode field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read dummy control
address_offset : 0x19CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE5 : Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes!
bits : 0 - 4 (5 bit)
access : read-write
PRESENT : Presence of dummy cycles: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read data control
address_offset : 0x19D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Write command control
address_offset : 0x19E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Command byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of command field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write address control
address_offset : 0x19E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Write mode control
address_offset : 0x19E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Mode byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of mode field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write dummy control
address_offset : 0x19EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE5 : Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles.
bits : 0 - 4 (5 bit)
access : read-write
PRESENT : Presence of dummy cycles: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write data control
address_offset : 0x19F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Cryptography Command
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3. The operation takes roughly 13 clk_hf clock cycles. Note: An operation can only be started in MMIO_MODE.
bits : 0 - 0 (1 bit)
access : read-write
Cryptography input 0
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT : Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0].
bits : 0 - 31 (32 bit)
access : read-write
Cryptography input 1
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT : Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0].
bits : 0 - 31 (32 bit)
access : read-write
Cryptography input 2
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT : Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0].
bits : 0 - 31 (32 bit)
access : read-write
Cryptography input 3
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT : Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0].
bits : 0 - 31 (32 bit)
access : read-write
Control
address_offset : 0x2300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_EN : Write enable: '0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. '1': write transfers are allowed to this device.
bits : 0 - 0 (1 bit)
access : read-write
CRYPTO_EN : Cryptography on read/write accesses: '0': disabled. '1': enabled.
bits : 8 - 16 (9 bit)
access : read-write
DATA_SEL : Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): '0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. '1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. '2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. '3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes.
bits : 16 - 33 (18 bit)
access : read-write
ENABLED : Device enable: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Device region base address
address_offset : 0x2308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24].
bits : 8 - 39 (32 bit)
access : read-write
Device region mask
address_offset : 0x230C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. Note: a transfer request that is not in any device region results in an AHB-Lite bus error.
bits : 8 - 39 (32 bit)
access : read-write
Address control
address_offset : 0x2320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE2 : Specifies the size of the XIP device address in Bytes: '0': 1 Byte address. '1': 2 Byte address. '2': 3 Byte address. '3': 4 Byte address. The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.
bits : 0 - 1 (2 bit)
access : read-write
DIV2 : Specifies if the AHB-Lite bus transfer address is divided by 2 or not: '0': No divide by 2. '1': Divide by 2. This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.
bits : 8 - 16 (9 bit)
access : read-write
Read command control
address_offset : 0x2340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Command byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of data transfer: '0': 1 bit/cycle (single data transfer). '1': 2 bits/cycle (dual data transfer). '2': 4 bits/cycle (quad data transfer). '3': 8 bits/cycle (octal data transfer).
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of command field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read address control
address_offset : 0x2344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Read mode control
address_offset : 0x2348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Mode byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of mode field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read dummy control
address_offset : 0x234C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE5 : Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes!
bits : 0 - 4 (5 bit)
access : read-write
PRESENT : Presence of dummy cycles: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read data control
address_offset : 0x2350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Write command control
address_offset : 0x2360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Command byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of command field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write address control
address_offset : 0x2364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Write mode control
address_offset : 0x2368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Mode byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of mode field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write dummy control
address_offset : 0x236C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE5 : Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles.
bits : 0 - 4 (5 bit)
access : read-write
PRESENT : Presence of dummy cycles: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write data control
address_offset : 0x2370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Cryptography key 0
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0].
bits : 0 - 31 (32 bit)
access : write-only
Cryptography key 1
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0].
bits : 0 - 31 (32 bit)
access : write-only
Cryptography key 2
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0].
bits : 0 - 31 (32 bit)
access : write-only
Cryptography key 3
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0].
bits : 0 - 31 (32 bit)
access : write-only
Cryptography output 0
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTPUT : Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0].
bits : 0 - 31 (32 bit)
access : read-write
Cryptography output 1
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTPUT : Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0].
bits : 0 - 31 (32 bit)
access : read-write
Cryptography output 2
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTPUT : Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0].
bits : 0 - 31 (32 bit)
access : read-write
Cryptography output 3
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTPUT : Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0].
bits : 0 - 31 (32 bit)
access : read-write
Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : Cache, cryptography, XIP, device interface or any other logic busy in the IP: '0': not busy '1': busy When BUSY is '0', the IP can be safely disabled without: - the potential loss of transient write data. - the potential risk of aborting an inflight SPI device interface transfer. When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed.
bits : 31 - 62 (32 bit)
access : read-only
Transmitter command FIFO status
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USED3 : Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4].
bits : 0 - 2 (3 bit)
access : read-only
Transmitter command FIFO write
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA20 : Command data. The higher two bits DATA[19:18] specify the specific command '0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format. - DATA[17:16] specifies the width of the data transfer: - '0': 1 bit/cycle (single data transfer). - '1': 2 bits/cycle (dual data transfer). - '2': 4 bits/cycle (quad data transfer). - '3': 8 bits/cycle (octal data transfer). - DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer. - DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode. - '0': device deselected - '1': device selected - DATA[7:0] specifies the transmitted Byte. '1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. - DATA[17:16] specifies the width of the transfer. - DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO. '2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers. - DATA[17:16] specifies the width of the transfer. - DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO. '3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command. - DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven.
bits : 0 - 19 (20 bit)
access : write-only
Interrupt register
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_TX_REQ : Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated.
bits : 0 - 0 (1 bit)
access : read-write
TR_RX_REQ : Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated.
bits : 1 - 2 (2 bit)
access : read-write
XIP_ALIGNMENT_ERROR : Activated in XIP mode, if: - The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2. - The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes. Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2.
bits : 2 - 4 (3 bit)
access : read-write
TX_CMD_FIFO_OVERFLOW : Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available.
bits : 3 - 6 (4 bit)
access : read-write
TX_DATA_FIFO_OVERFLOW : Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available.
bits : 4 - 8 (5 bit)
access : read-write
RX_DATA_FIFO_UNDERFLOW : Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers.
bits : 5 - 10 (6 bit)
access : read-write
Interrupt set register
address_offset : 0x7C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_TX_REQ : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
TR_RX_REQ : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
XIP_ALIGNMENT_ERROR : Write with '1' to set corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write
TX_CMD_FIFO_OVERFLOW : Write with '1' to set corresponding bit in interrupt request register.
bits : 3 - 6 (4 bit)
access : read-write
TX_DATA_FIFO_OVERFLOW : Write with '1' to set corresponding bit in interrupt request register.
bits : 4 - 8 (5 bit)
access : read-write
RX_DATA_FIFO_UNDERFLOW : Write with '1' to set corresponding bit in interrupt request register.
bits : 5 - 10 (6 bit)
access : read-write
Interrupt mask register
address_offset : 0x7C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR_TX_REQ : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
TR_RX_REQ : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
XIP_ALIGNMENT_ERROR : Mask bit for corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write
TX_CMD_FIFO_OVERFLOW : Mask bit for corresponding bit in interrupt request register.
bits : 3 - 6 (4 bit)
access : read-write
TX_DATA_FIFO_OVERFLOW : Mask bit for corresponding bit in interrupt request register.
bits : 4 - 8 (5 bit)
access : read-write
RX_DATA_FIFO_UNDERFLOW : Mask bit for corresponding bit in interrupt request register.
bits : 5 - 10 (6 bit)
access : read-write
Interrupt masked register
address_offset : 0x7CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TR_TX_REQ : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
TR_RX_REQ : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
XIP_ALIGNMENT_ERROR : Logical and of corresponding request and mask bits.
bits : 2 - 4 (3 bit)
access : read-only
TX_CMD_FIFO_OVERFLOW : Logical and of corresponding request and mask bits.
bits : 3 - 6 (4 bit)
access : read-only
TX_DATA_FIFO_OVERFLOW : Logical and of corresponding request and mask bits.
bits : 4 - 8 (5 bit)
access : read-only
RX_DATA_FIFO_UNDERFLOW : Logical and of corresponding request and mask bits.
bits : 5 - 10 (6 bit)
access : read-only
Transmitter data FIFO control
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGGER_LEVEL : Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): - Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL.
bits : 0 - 2 (3 bit)
access : read-write
Control
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_EN : Write enable: '0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. '1': write transfers are allowed to this device.
bits : 0 - 0 (1 bit)
access : read-write
CRYPTO_EN : Cryptography on read/write accesses: '0': disabled. '1': enabled.
bits : 8 - 16 (9 bit)
access : read-write
DATA_SEL : Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): '0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. '1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. '2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. '3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes.
bits : 16 - 33 (18 bit)
access : read-write
ENABLED : Device enable: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Device region base address
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24].
bits : 8 - 39 (32 bit)
access : read-write
Device region mask
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. Note: a transfer request that is not in any device region results in an AHB-Lite bus error.
bits : 8 - 39 (32 bit)
access : read-write
Address control
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE2 : Specifies the size of the XIP device address in Bytes: '0': 1 Byte address. '1': 2 Byte address. '2': 3 Byte address. '3': 4 Byte address. The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.
bits : 0 - 1 (2 bit)
access : read-write
DIV2 : Specifies if the AHB-Lite bus transfer address is divided by 2 or not: '0': No divide by 2. '1': Divide by 2. This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.
bits : 8 - 16 (9 bit)
access : read-write
Transmitter data FIFO status
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USED4 : Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8].
bits : 0 - 3 (4 bit)
access : read-only
Read command control
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Command byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of data transfer: '0': 1 bit/cycle (single data transfer). '1': 2 bits/cycle (dual data transfer). '2': 4 bits/cycle (quad data transfer). '3': 8 bits/cycle (octal data transfer).
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of command field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read address control
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Read mode control
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Mode byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of mode field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read dummy control
address_offset : 0x84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE5 : Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes!
bits : 0 - 4 (5 bit)
access : read-write
PRESENT : Presence of dummy cycles: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Read data control
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Write command control
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Command byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of command field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write address control
address_offset : 0x864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Write mode control
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CODE : Mode byte code.
bits : 0 - 7 (8 bit)
access : read-write
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
PRESENT : Presence of mode field: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write dummy control
address_offset : 0x86C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIZE5 : Number of dummy cycles (minus 1): '0': 1 cycles ... '31': 32 cycles.
bits : 0 - 4 (5 bit)
access : read-write
PRESENT : Presence of dummy cycles: '0': not present '1': present
bits : 31 - 62 (32 bit)
access : read-write
Write data control
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of transfer.
bits : 16 - 33 (18 bit)
access : read-write
Transmitter data FIFO write
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : TX data (written to TX data FIFO).
bits : 0 - 7 (8 bit)
access : write-only
Transmitter data FIFO write
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : TX data (written to TX data FIFO, first byte).
bits : 0 - 7 (8 bit)
access : write-only
DATA1 : TX data (written to TX data FIFO, second byte).
bits : 8 - 23 (16 bit)
access : write-only
Transmitter data FIFO write
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : TX data (written to TX data FIFO, first byte).
bits : 0 - 7 (8 bit)
access : write-only
DATA1 : TX data (written to TX data FIFO, second byte).
bits : 8 - 23 (16 bit)
access : write-only
DATA2 : TX data (written to TX data FIFO, third byte).
bits : 16 - 39 (24 bit)
access : write-only
DATA3 : TX data (written to TX data FIFO, fourth byte).
bits : 24 - 55 (32 bit)
access : write-only
Receiver data FIFO control
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGGER_LEVEL : Determines when RX data FIFI 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): - Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL.
bits : 0 - 2 (3 bit)
access : read-write
Receiver data FIFO status
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USED4 : Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8].
bits : 0 - 3 (4 bit)
access : read-only
Receiver data FIFO read
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : RX data (read from RX data FIFO).
bits : 0 - 7 (8 bit)
access : read-only
Receiver data FIFO read
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : RX data (read from RX data FIFO, first byte).
bits : 0 - 7 (8 bit)
access : read-only
DATA1 : RX data (read from RX data FIFO, second byte).
bits : 8 - 23 (16 bit)
access : read-only
Receiver data FIFO read
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : RX data (read from RX data FIFO, first byte).
bits : 0 - 7 (8 bit)
access : read-only
DATA1 : RX data (read from RX data FIFO, second byte).
bits : 8 - 23 (16 bit)
access : read-only
DATA2 : RX data (read from RX data FIFO, third byte).
bits : 16 - 39 (24 bit)
access : read-only
DATA3 : RX data (read from RX data FIFO, fourth byte).
bits : 24 - 55 (32 bit)
access : read-only
Receiver data FIFO silent read
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : RX data (read from RX data FIFO).
bits : 0 - 7 (8 bit)
access : read-only
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