CTRL

DDFT_CTRL

SPI_CTRL

TX_CTRL

TX_FIFO_CTRL

TX_FIFO_STATUS

SPI_STATUS

TX_FIFO_WR

RX_CTRL

RX_FIFO_CTRL

RX_FIFO_STATUS

RX_MATCH

RX_FIFO_RD

RX_FIFO_RD_SILENT

STATUS

UART_CTRL

UART_TX_CTRL

UART_RX_CTRL

UART_RX_STATUS

UART_FLOW_CTRL

I2C_CTRL

I2C_STATUS

I2C_M_CMD

I2C_S_CMD

I2C_CFG

CMD_RESP_CTRL

CMD_RESP_STATUS

INTR_CAUSE

INTR_I2C_EC

INTR_I2C_EC_MASK

INTR_I2C_EC_MASKED

INTR_SPI_EC

INTR_SPI_EC_MASK

INTR_SPI_EC_MASKED

INTR_M

INTR_M_SET

INTR_M_MASK

INTR_M_MASKED

INTR_S

INTR_S_SET

INTR_S_MASK

INTR_S_MASKED

INTR_TX

INTR_TX_SET

INTR_TX_MASK

INTR_TX_MASKED

INTR_RX

INTR_RX_SET

INTR_RX_MASK

INTR_RX_MASKED

OVS : N/A
bits : 0 - 3 (4 bit)
access : read-write

EC_AM_MODE : This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI) '0': Internally clocked mode '1': Externally clocked mode In internally clocked mode, the serial interface protocols run off the SCB clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. The clocking for the rest of the logic is determined by CTRL.EC_OP_MODE. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. In UART mode this field should be '0'.
bits : 8 - 16 (9 bit)
access : read-write

EC_OP_MODE : This field specifies the clocking for the SCB block '0': Internally clocked mode '1': externally clocked mode In internally clocked mode, the serial interface protocols run off the SCB clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate). In UART mode this field should be '0'.
bits : 9 - 18 (10 bit)
access : read-write

EZ_MODE : Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames not seperated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of 32 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. In UART mode this field should be '0'.
bits : 10 - 20 (11 bit)
access : read-write

BYTE_MODE : N/A
bits : 11 - 22 (12 bit)
access : read-write

CMD_RESP_MODE : N/A
bits : 12 - 24 (13 bit)
access : read-write

ADDR_ACCEPT : Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0'). In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when this bit is '1' for both I2C read and write transfers. In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO.
bits : 16 - 32 (17 bit)
access : read-write

BLOCK : Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide, this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, CPU read operations return 0xffff:ffff and CPU write operations are ignored. Colliding accesses are registered as interrupt causes: INTR_TX.BLOCKED and INTR_RX.BLOCKED.
bits : 17 - 34 (18 bit)
access : read-write

MODE : N/A
bits : 24 - 49 (26 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENABLED : SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows: - Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL registers. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. - Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. - Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. - Program CTRL register to enable SCB, select the specific operation mode and oversampling factor. When this block is enabled, no control information should be changed. Changes should be made AFTER disabling this block, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the block is re-enabled. Note that disabling the block will cause re-initialization of the design and associated state is lost (e.g. FIFO content).
bits : 31 - 62 (32 bit)
access : read-write

DDFT_IN0_SEL : Specifies signal that is connected to 'ddft_in[0]' (digital DfT input signal 0): '0': not used '1': used as 'i2c_scl_in' in I2C mode, as 'spi_clk_in' in SPI mode
bits : 0 - 0 (1 bit)
access : read-write

DDFT_IN1_SEL : Specifies signal that is connected to 'ddft_in[1]' (digital DfT input signal 0): '0': not used '1': used as 'i2c_sda_in' in I2C mode, as 'spi_mosi_in' in SPI mode
bits : 4 - 8 (5 bit)
access : read-write

DDFT_OUT0_SEL : Specifies signal that is connected to 'ddft_out[0]' (digital DfT output signal 0): In I2C mode (CTRL.MODE=0), '0': Constant '0'. '1': 'ec_busy_pp'. '2': 'rst_i2c_start_stop_n'. '3': 'rst_i2c_start_stop_n'. '4': 'i2c_scl_in_qual'. '5': 'i2c_sda_out_prel'. '6'-'7': Undefined. in SPI mode (CTRL.MODE=1), '0': Constant '0'. '1': 'rst_spi_n' '2': 'rst_spi_stop_n' '3'-'7': Undefined.
bits : 16 - 34 (19 bit)
access : read-write

DDFT_OUT1_SEL : Specifies signal that is connected to 'ddft_out[1]' (digital DfT output signal 1): In I2C mode (CTRL.MODE=0), '0': Constant '0'. '1': 'clk_ff_sram'. '2': 'rst_i2c_n'. '3': 'rst_i2c_stop_n'. '4': 'i2c_sda_in_qual'. '5': 'i2c_sda_out'. '6': 'event_i2c_ec_wake_up_ddft' from I2CS_IC '7': Undefined. In SPI mode (CTRL.MODE=1), '0': Constant '0'. '1': 'spi_start_detect' '2': 'spi_stop_detect' '3'-'7': Undefined.
bits : 20 - 42 (23 bit)
access : read-write

SSEL_CONTINUOUS : Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. When continuous transfers are enabled individual data frame transfers are not necessarily seperated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection. When continuous transfers are not enabled individual data frame transfers are always seperated by slave deselection: independent of the availability of TX FIFO data frames, data frames are sent out with slave deselection.
bits : 0 - 0 (1 bit)
access : read-write

SELECT_PRECEDE : Only used in SPI Texas Instruments' submode. When '1', the data frame start indication is a pulse on the Slave SELECT line that precedes the transfer of the first data frame bit. When '0', the data frame start indication is a pulse on the Slave SELECT line that coincides with the transfer of the first data frame bit.
bits : 1 - 2 (2 bit)
access : read-write

CPHA : N/A
bits : 2 - 4 (3 bit)
access : read-write

CPOL : N/A
bits : 3 - 6 (4 bit)
access : read-write

LATE_MISO_SAMPLE : Changes the SCLK edge on which MISO is captured. Only used in master mode. When '0', the default applies ( for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK). When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master.
bits : 4 - 8 (5 bit)
access : read-write

SCLK_CONTINUOUS : N/A
bits : 5 - 10 (6 bit)
access : read-write

SSEL_POLARITY0 : N/A
bits : 8 - 16 (9 bit)
access : read-write

SSEL_POLARITY1 : N/A
bits : 9 - 18 (10 bit)
access : read-write

SSEL_POLARITY2 : N/A
bits : 10 - 20 (11 bit)
access : read-write

SSEL_POLARITY3 : N/A
bits : 11 - 22 (12 bit)
access : read-write

LOOPBACK : Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. '0': No local loopback '1': the SPI master MISO line is connected to the SPI master MOSI line. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI.
bits : 16 - 32 (17 bit)
access : read-write

MODE : N/A
bits : 24 - 49 (26 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSEL : Selects one of the four incoming/outgoing SPI slave select signals: - 0: Slave 0, SSEL[0]. - 1: Slave 1, SSEL[1]. - 2: Slave 2, SSEL[2]. - 3: Slave 3, SSEL[3]. SCB block should be disabled when changes are made to this field.
bits : 26 - 53 (28 bit)
access : read-write

MASTER_MODE : N/A
bits : 31 - 62 (32 bit)
access : read-write

DATA_WIDTH : Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7.
bits : 0 - 3 (4 bit)
access : read-write

MSB_FIRST : Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.
bits : 8 - 16 (9 bit)
access : read-write

OPEN_DRAIN : Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'. '0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'. '1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1'). The open drain mode is supported for: - I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. - UART mode, 'uart_tx' IO cell (SPI slave). - SPI mode, 'spi_miso' IO cell.
bits : 16 - 32 (17 bit)
access : read-write

TRIGGER_LEVEL : Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event is generated.
bits : 0 - 7 (8 bit)
access : read-write

CLEAR : When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.
bits : 16 - 32 (17 bit)
access : read-write

FREEZE : When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer.
bits : 17 - 34 (18 bit)
access : read-write

USED : Amount of enties in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR.
bits : 0 - 8 (9 bit)
access : read-only

SR_VALID : Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is tranmitted next (when the protocol state machine is not transmitting a data frame).
bits : 15 - 30 (16 bit)
access : read-only

RD_PTR : FIFO read pointer: FIFO location from which a data frame is read by the hardware.
bits : 16 - 39 (24 bit)
access : read-only

WR_PTR : FIFO write pointer: FIFO location at which a new data frame is written.
bits : 24 - 55 (32 bit)
access : read-only

BUS_BUSY : SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted.
bits : 0 - 0 (1 bit)
access : read-only

SPI_EC_BUSY : Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable.
bits : 1 - 2 (2 bit)
access : read-only

CURR_EZ_ADDR : SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design.
bits : 8 - 23 (16 bit)
access : read-only

BASE_EZ_ADDR : SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design.
bits : 16 - 39 (24 bit)
access : read-only

DATA : Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'.
bits : 0 - 15 (16 bit)
access : write-only

DATA_WIDTH : Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7.
bits : 0 - 3 (4 bit)
access : read-write

MSB_FIRST : Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.
bits : 8 - 16 (9 bit)
access : read-write

MEDIAN : Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptability to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'.
bits : 9 - 18 (10 bit)
access : read-write

TRIGGER_LEVEL : Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event is generated.
bits : 0 - 7 (8 bit)
access : read-write

CLEAR : When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.
bits : 16 - 32 (17 bit)
access : read-write

FREEZE : When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer.
bits : 17 - 34 (18 bit)
access : read-write

USED : Amount of enties in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR.
bits : 0 - 8 (9 bit)
access : read-only

SR_VALID : Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame).
bits : 15 - 30 (16 bit)
access : read-only

RD_PTR : FIFO read pointer: FIFO location from which a data frame is read.
bits : 16 - 39 (24 bit)
access : read-only

WR_PTR : FIFO write pointer: FIFO location at which a new data frame is written by the hardware.
bits : 24 - 55 (32 bit)
access : read-only

ADDR : N/A
bits : 0 - 7 (8 bit)
access : read-write

MASK : Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK)).
bits : 16 - 39 (24 bit)
access : read-write

DATA : Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. When this register is read through the debugger, the data frame will not be removed from the FIFO. Similar in operation to RX_FIFO_RD_SILENT
bits : 0 - 15 (16 bit)
access : read-only

DATA : Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.
bits : 0 - 15 (16 bit)
access : read-only

EC_BUSY : Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic.
bits : 0 - 0 (1 bit)
access : read-only

LOOPBACK : Local loopback control (does NOT affect the information on the pins). 0: Loopback is not enabled 1: UART_TX is connected to UART_RX. UART_RTS is connected to UART_CTS. This allows a SCB UART transmitter to communicate with its receiver counterpart.
bits : 16 - 32 (17 bit)
access : read-write

MODE : N/A
bits : 24 - 49 (26 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP_BITS : Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period.
bits : 0 - 2 (3 bit)
access : read-write

PARITY : Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes.
bits : 4 - 8 (5 bit)
access : read-write

PARITY_ENABLED : Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware
bits : 5 - 10 (6 bit)
access : read-write

RETRY_ON_NACK : When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode.
bits : 8 - 16 (9 bit)
access : read-write

STOP_BITS : N/A
bits : 0 - 2 (3 bit)
access : read-write

PARITY : N/A
bits : 4 - 8 (5 bit)
access : read-write

PARITY_ENABLED : N/A
bits : 5 - 10 (6 bit)
access : read-write

POLARITY : Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality.
bits : 6 - 12 (7 bit)
access : read-write

DROP_ON_PARITY_ERROR : Behaviour when a parity check fails. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field).
bits : 8 - 16 (9 bit)
access : read-write

DROP_ON_FRAME_ERROR : Behaviour when an error is detected in a start or stop period. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost.
bits : 9 - 18 (10 bit)
access : read-write

MP_MODE : N/A
bits : 10 - 20 (11 bit)
access : read-write

LIN_MODE : Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte.
bits : 12 - 24 (13 bit)
access : read-write

SKIP_START : N/A
bits : 13 - 26 (14 bit)
access : read-write

BREAK_WIDTH : N/A
bits : 16 - 35 (20 bit)
access : read-write

BR_COUNTER : Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'.
bits : 0 - 11 (12 bit)
access : read-only

TRIGGER_LEVEL : Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to '0', flow control is effectively disabled (may be useful for debug purposes).
bits : 0 - 7 (8 bit)
access : read-write

RTS_POLARITY : Polarity of the RTS output signal: '0': RTS is active low; '1': RTS is active high; During SCB reset (Hibernate system power mode), RTS output signal is '1'. This represents an inactive state assuming an active low polarity.
bits : 16 - 32 (17 bit)
access : read-write

CTS_POLARITY : Polarity of the CTS input signal '0': CTS is active low ; '1': CTS is active high;
bits : 24 - 48 (25 bit)
access : read-write

CTS_ENABLED : Enable use of CTS input signal by the UART transmitter: '0': Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. '1': Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register. If UART_CTRL.LOOPBACK is '1', the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes are indicated by RTS_POLARITY and CTS_POLARITY).
bits : 25 - 50 (26 bit)
access : read-write

HIGH_PHASE_OVS : Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the SCB clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 SCB clock cycles and <= 16 SCB clock cycles. Without input signal median filtering, the IF high time should be >= 5 SCB clock cycles and <= 16 SCB clock cycles.
bits : 0 - 3 (4 bit)
access : read-write

LOW_PHASE_OVS : Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the SCB clock wrt. the regular (no stretching) interface (IF) low time to guarantee functionally correct behavior. With input signal median filtering, the IF low time should be >= 8 SCB clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 SCB clock cycles and <= 16 SCB clock cycles.
bits : 4 - 11 (8 bit)
access : read-write

M_READY_DATA_ACK : N/A
bits : 8 - 16 (9 bit)
access : read-write

M_NOT_READY_DATA_NACK : N/A
bits : 9 - 18 (10 bit)
access : read-write

S_GENERAL_IGNORE : N/A
bits : 11 - 22 (12 bit)
access : read-write

S_READY_ADDR_ACK : N/A
bits : 12 - 24 (13 bit)
access : read-write

S_READY_DATA_ACK : N/A
bits : 13 - 26 (14 bit)
access : read-write

S_NOT_READY_ADDR_NACK : This field is used during an address match or general call address in internally clocked mode Only used when: - EC_AM_MODE is '0', EC_OP_MODE is '0', S_GENERAL_IGNORE is '0] and non EZ mode. Functionality is as follows: - 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode): - EC_AM is '1' and EC_OP is '0'. - EC_AM is '1' and general call address match. - EC_AM is '1' and non EZ mode. Functionality is as follows: - 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the SCB clock is available (in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2).SCB clock is not present (in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode). - 0: clock stretching is performed (till the SCB clock is available). The logic will handle the ongoing transfer as soon as the clock is enabled.
bits : 14 - 28 (15 bit)
access : read-write

S_NOT_READY_DATA_NACK : Only used when: - non EZ mode Functionality is as follows: - 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full).
bits : 15 - 30 (16 bit)
access : read-write

LOOPBACK : Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', no loopback When '1', loopback is enabled internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself.
bits : 16 - 32 (17 bit)
access : read-write

SLAVE_MODE : N/A
bits : 30 - 60 (31 bit)
access : read-write

MASTER_MODE : N/A
bits : 31 - 62 (32 bit)
access : read-write

BUS_BUSY : I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If SCB block is disabled, BUS_BUSY is '0'. After enabling the block, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions).
bits : 0 - 0 (1 bit)
access : read-only

I2C_EC_BUSY : N/A
bits : 1 - 2 (2 bit)
access : read-only

S_READ : N/A
bits : 4 - 8 (5 bit)
access : read-only

M_READ : N/A
bits : 5 - 10 (6 bit)
access : read-only

CURR_EZ_ADDR : N/A
bits : 8 - 23 (16 bit)
access : read-only

BASE_EZ_ADDR : N/A
bits : 16 - 39 (24 bit)
access : read-only

M_START : When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'.
bits : 0 - 0 (1 bit)
access : read-write

M_START_ON_IDLE : When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'.
bits : 1 - 2 (2 bit)
access : read-write

M_ACK : When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'.
bits : 2 - 4 (3 bit)
access : read-write

M_NACK : When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'.
bits : 3 - 6 (4 bit)
access : read-write

M_STOP : When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP.
bits : 4 - 8 (5 bit)
access : read-write

S_ACK : When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode).
bits : 0 - 0 (1 bit)
access : read-write

S_NACK : When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK.
bits : 1 - 2 (2 bit)
access : read-write

SDA_IN_FILT_TRIM : Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required
bits : 0 - 1 (2 bit)
access : read-write

SDA_IN_FILT_SEL : Enable for 50ns glitch filter on SDA input '0': 0 ns. '1: 50 ns (filter enabled).
bits : 4 - 8 (5 bit)
access : read-write

SCL_IN_FILT_TRIM : Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required
bits : 8 - 17 (10 bit)
access : read-write

SCL_IN_FILT_SEL : Enable for 50ns glitch filter on SCL input '0': 0 ns. '1: 50 ns (filter enabled).
bits : 12 - 24 (13 bit)
access : read-write

SDA_OUT_FILT0_TRIM : Trim settings for the 50ns delay filter on SDA output used to gurantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required
bits : 16 - 33 (18 bit)
access : read-write

SDA_OUT_FILT1_TRIM : Trim settings for the 50ns delay filter on SDA output used to gurantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required
bits : 18 - 37 (20 bit)
access : read-write

SDA_OUT_FILT2_TRIM : Trim settings for the 50ns delay filter on SDA output used to gurantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required
bits : 20 - 41 (22 bit)
access : read-write

SDA_OUT_FILT_SEL : Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter '0': 0 ns. '1': 50 ns (filter 0 enabled). '2': 100 ns (filters 0 and 1 enabled). '3': 150 ns (filters 0, 1 and 2 enabled).
bits : 28 - 57 (30 bit)
access : read-write

BASE_RD_ADDR : I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers.
bits : 0 - 8 (9 bit)
access : read-write

BASE_WR_ADDR : I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers.
bits : 16 - 40 (25 bit)
access : read-write

CURR_RD_ADDR : I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address). The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR). This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e. when CMD_RESP_EC_BUSY is '0', the field is reliable.
bits : 0 - 8 (9 bit)
access : read-only

CURR_WR_ADDR : I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address). The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e when CMD_RESP_EC_BUSY is '0', the field is reliable.
bits : 16 - 40 (25 bit)
access : read-only

CMD_RESP_EC_BUS_BUSY : Indicates whether there is an ongoing bus transfer to the IP. '0': no ongoing bus transfer. '1': ongoing bus transfer. For SPI, the field is '1' when slave mode is selected. For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match.
bits : 30 - 60 (31 bit)
access : read-only

CMD_RESP_EC_BUSY : N/A
bits : 31 - 62 (32 bit)
access : read-only

M : Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0.
bits : 0 - 0 (1 bit)
access : read-only

S : Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0.
bits : 1 - 2 (2 bit)
access : read-only

TX : Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0.
bits : 2 - 4 (3 bit)
access : read-only

RX : Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0.
bits : 3 - 6 (4 bit)
access : read-only

I2C_EC : Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0.
bits : 4 - 8 (5 bit)
access : read-only

SPI_EC : Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0.
bits : 5 - 10 (6 bit)
access : read-only

WAKE_UP : Wake up request. Active on incoming slave request (with address match). Only used when CTRL.EC_AM_MODE is '1'.
bits : 0 - 0 (1 bit)
access : read-write

EZ_STOP : STOP detection. Activated on the end of a every transfer (I2C STOP). Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'.
bits : 1 - 2 (2 bit)
access : read-write

EZ_WRITE_STOP : STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'.
bits : 2 - 4 (3 bit)
access : read-write

EZ_READ_STOP : STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. Only available for a slave request with an address match, in EZ and CMD_RESP modes, when CTRL.EC_OP_MODE is '1'.
bits : 3 - 6 (4 bit)
access : read-write

WAKE_UP : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write

EZ_STOP : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write

EZ_WRITE_STOP : Mask bit for corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write

EZ_READ_STOP : Mask bit for corresponding bit in interrupt request register.
bits : 3 - 6 (4 bit)
access : read-write

WAKE_UP : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only

EZ_STOP : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only

EZ_WRITE_STOP : Logical and of corresponding request and mask bits.
bits : 2 - 4 (3 bit)
access : read-only

EZ_READ_STOP : Logical and of corresponding request and mask bits.
bits : 3 - 6 (4 bit)
access : read-only

WAKE_UP : Wake up request. Active on incoming slave request when externally clocked selection is '1'. Only used when CTRL.EC_AM_MODE is '1'.
bits : 0 - 0 (1 bit)
access : read-write

EZ_STOP : STOP detection. Activated on the end of a every transfer (SPI deselection). Only available in EZ and CMD_RESP mode and when CTRL.EC_OP_MODE is '1'.
bits : 1 - 2 (2 bit)
access : read-write

EZ_WRITE_STOP : STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only used in EZ and CMD_RESP modes and when CTRL.EC_OP_MODE is '1'.
bits : 2 - 4 (3 bit)
access : read-write

EZ_READ_STOP : STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. Only used in EZ and CMD_RESP modes and when CTRL.EC_OP_MODE is '1'.
bits : 3 - 6 (4 bit)
access : read-write

WAKE_UP : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write

EZ_STOP : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write

EZ_WRITE_STOP : Mask bit for corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write

EZ_READ_STOP : Mask bit for corresponding bit in interrupt request register.
bits : 3 - 6 (4 bit)
access : read-write

WAKE_UP : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only

EZ_STOP : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only

EZ_WRITE_STOP : Logical and of corresponding request and mask bits.
bits : 2 - 4 (3 bit)
access : read-only

EZ_READ_STOP : Logical and of corresponding request and mask bits.
bits : 3 - 6 (4 bit)
access : read-only

I2C_ARB_LOST : I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line.
bits : 0 - 0 (1 bit)
access : read-write

I2C_NACK : I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data).
bits : 1 - 2 (2 bit)
access : read-write

I2C_ACK : I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data).
bits : 2 - 4 (3 bit)
access : read-write

I2C_STOP : I2C master STOP. Set to '1', when the master has transmitted a STOP.
bits : 4 - 8 (5 bit)
access : read-write

I2C_BUS_ERROR : I2C master bus error (unexpected detection of START or STOP condition).
bits : 8 - 16 (9 bit)
access : read-write

SPI_DONE : SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected.
bits : 9 - 18 (10 bit)
access : read-write

I2C_ARB_LOST : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write

I2C_NACK : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write

I2C_ACK : Write with '1' to set corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write

I2C_STOP : Write with '1' to set corresponding bit in interrupt request register.
bits : 4 - 8 (5 bit)
access : read-write

I2C_BUS_ERROR : Write with '1' to set corresponding bit in interrupt request register.
bits : 8 - 16 (9 bit)
access : read-write

SPI_DONE : Write with '1' to set corresponding bit in interrupt request register.
bits : 9 - 18 (10 bit)
access : read-write

I2C_ARB_LOST : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write

I2C_NACK : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write

I2C_ACK : Mask bit for corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write

I2C_STOP : Mask bit for corresponding bit in interrupt request register.
bits : 4 - 8 (5 bit)
access : read-write

I2C_BUS_ERROR : Mask bit for corresponding bit in interrupt request register.
bits : 8 - 16 (9 bit)
access : read-write

SPI_DONE : Mask bit for corresponding bit in interrupt request register.
bits : 9 - 18 (10 bit)
access : read-write

I2C_ARB_LOST : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only

I2C_NACK : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only

I2C_ACK : Logical and of corresponding request and mask bits.
bits : 2 - 4 (3 bit)
access : read-only

I2C_STOP : Logical and of corresponding request and mask bits.
bits : 4 - 8 (5 bit)
access : read-only

I2C_BUS_ERROR : Logical and of corresponding request and mask bits.
bits : 8 - 16 (9 bit)
access : read-only

SPI_DONE : Logical and of corresponding request and mask bits.
bits : 9 - 18 (10 bit)
access : read-only

I2C_ARB_LOST : I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine aborts the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.
bits : 0 - 0 (1 bit)
access : read-write

I2C_NACK : N/A
bits : 1 - 2 (2 bit)
access : read-write

I2C_ACK : N/A
bits : 2 - 4 (3 bit)
access : read-write

I2C_WRITE_STOP : N/A
bits : 3 - 6 (4 bit)
access : read-write

I2C_STOP : N/A
bits : 4 - 8 (5 bit)
access : read-write

I2C_START : I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL.
bits : 5 - 10 (6 bit)
access : read-write

I2C_ADDR_MATCH : N/A
bits : 6 - 12 (7 bit)
access : read-write

I2C_GENERAL : N/A
bits : 7 - 14 (8 bit)
access : read-write

I2C_BUS_ERROR : N/A
bits : 8 - 16 (9 bit)
access : read-write

SPI_EZ_WRITE_STOP : N/A
bits : 9 - 18 (10 bit)
access : read-write

SPI_EZ_STOP : N/A
bits : 10 - 20 (11 bit)
access : read-write

SPI_BUS_ERROR : N/A
bits : 11 - 22 (12 bit)
access : read-write

I2C_ARB_LOST : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write

I2C_NACK : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write

I2C_ACK : Write with '1' to set corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write

I2C_WRITE_STOP : Write with '1' to set corresponding bit in interrupt request register.
bits : 3 - 6 (4 bit)
access : read-write

I2C_STOP : Write with '1' to set corresponding bit in interrupt request register.
bits : 4 - 8 (5 bit)
access : read-write

I2C_START : Write with '1' to set corresponding bit in interrupt request register.
bits : 5 - 10 (6 bit)
access : read-write

I2C_ADDR_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 6 - 12 (7 bit)
access : read-write

I2C_GENERAL : Write with '1' to set corresponding bit in interrupt request register.
bits : 7 - 14 (8 bit)
access : read-write

I2C_BUS_ERROR : Write with '1' to set corresponding bit in interrupt request register.
bits : 8 - 16 (9 bit)
access : read-write

SPI_EZ_WRITE_STOP : Write with '1' to set corresponding bit in interrupt request register.
bits : 9 - 18 (10 bit)
access : read-write

SPI_EZ_STOP : Write with '1' to set corresponding bit in interrupt request register.
bits : 10 - 20 (11 bit)
access : read-write

SPI_BUS_ERROR : Write with '1' to set corresponding bit in interrupt request register.
bits : 11 - 22 (12 bit)
access : read-write

I2C_ARB_LOST : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write

I2C_NACK : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write

I2C_ACK : Mask bit for corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write

I2C_WRITE_STOP : Mask bit for corresponding bit in interrupt request register.
bits : 3 - 6 (4 bit)
access : read-write

I2C_STOP : Mask bit for corresponding bit in interrupt request register.
bits : 4 - 8 (5 bit)
access : read-write

I2C_START : Mask bit for corresponding bit in interrupt request register.
bits : 5 - 10 (6 bit)
access : read-write

I2C_ADDR_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 6 - 12 (7 bit)
access : read-write

I2C_GENERAL : Mask bit for corresponding bit in interrupt request register.
bits : 7 - 14 (8 bit)
access : read-write

I2C_BUS_ERROR : Mask bit for corresponding bit in interrupt request register.
bits : 8 - 16 (9 bit)
access : read-write

SPI_EZ_WRITE_STOP : Mask bit for corresponding bit in interrupt request register.
bits : 9 - 18 (10 bit)
access : read-write

SPI_EZ_STOP : Mask bit for corresponding bit in interrupt request register.
bits : 10 - 20 (11 bit)
access : read-write

SPI_BUS_ERROR : Mask bit for corresponding bit in interrupt request register.
bits : 11 - 22 (12 bit)
access : read-write