\n
address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
global CTB and power control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEEPSLEEP_ON : - 0: CTB IP disabled off during DeepSleep power mode - 1: CTB IP remains enabled during DeepSleep power mode (if ENABLED=1)
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : - 0: CTB IP disabled (put analog in power down, open all switches) - 1: CTB IP enabled
bits : 31 - 62 (32 bit)
access : read-write
Interrupt request register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
COMP1 : Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt request set register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
COMP1_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt request mask
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
COMP1_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
Interrupt request masked
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMP0_MASKED : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
COMP1_MASKED : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
Opamp0 and resistor0 control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA0_PWR_MODE : Opamp0 power level, assumes Cload=15pF for the (internal only) 1x driver or 50pF for the (external) 10x driver
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : OFF
Off
1 : LOW
Low power mode (IDD: 350uA, GBW: 1MHz for both 1x/10x)
2 : MEDIUM
Medium power mode (IDD: 600uA, GBW: 3MHz for 1x & 2.5MHz for 10x)
3 : HIGH
High power mode for highest GBW (IDD: 1500uA, GBW: 8MHz for 1x & 6MHz for 10x)
4 : RSVD
N/A
5 : PS_LOW
Power Saver Low power mode (IDD: ~20uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is disabled)
6 : PS_MEDIUM
Power Saver Medium power mode (IDD: ~40uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is enabled)
7 : PS_HIGH
Power Saver Medium power mode (IDD: ~60uA with 1uA bias from AREF, GBW: ~200kHz for 1x/10x, offset correcting IDAC is enabled)
End of enumeration elements list.
OA0_DRIVE_STR_SEL : Opamp0 output strength select 0=1x, 1=10x This setting sets specific requirements for OA0_BOOST_EN and OA0_COMP_TRIM
bits : 3 - 6 (4 bit)
access : read-write
OA0_COMP_EN : Opamp0 comparator enable
bits : 4 - 8 (5 bit)
access : read-write
OA0_HYST_EN : Opamp0 hysteresis enable (10mV)
bits : 5 - 10 (6 bit)
access : read-write
OA0_BYPASS_DSI_SYNC : Opamp0 bypass comparator output synchronization for DSI (trigger) output: 0=synchronize (level or pulse), 1=bypass (output async)
bits : 6 - 12 (7 bit)
access : read-write
OA0_DSI_LEVEL : Opamp0 comparator DSI (trigger) out level : 0=pulse, each time an edge is detected (see OA0_COMPINT) a pulse is sent out on DSI 1=level, DSI output is a synchronized version of the comparator output
bits : 7 - 14 (8 bit)
access : read-write
OA0_COMPINT : Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger)
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled, no interrupts will be detected
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
OA0_PUMP_EN : Opamp0 pump enable
bits : 11 - 22 (12 bit)
access : read-write
OA0_BOOST_EN : Opamp0 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0
bits : 12 - 24 (13 bit)
access : read-write
Opamp1 and resistor1 control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA1_PWR_MODE : Opamp1 power level: see description of OA0_PWR_MODE
bits : 0 - 2 (3 bit)
access : read-write
OA1_DRIVE_STR_SEL : Opamp1 output strength select 0=1x, 1=10x This setting sets specific requirements for OA1_BOOST_EN and OA1_COMP_TRIM
bits : 3 - 6 (4 bit)
access : read-write
OA1_COMP_EN : Opamp1 comparator enable
bits : 4 - 8 (5 bit)
access : read-write
OA1_HYST_EN : Opamp1 hysteresis enable (10mV)
bits : 5 - 10 (6 bit)
access : read-write
OA1_BYPASS_DSI_SYNC : Opamp1 bypass comparator output synchronization for DSI output: 0=synchronize, 1=bypass
bits : 6 - 12 (7 bit)
access : read-write
OA1_DSI_LEVEL : Opamp1 comparator DSI (trigger) out level : 0=pulse, each time an edge is detected (see OA1_COMPINT) a pulse is sent out on DSI 1=level, DSI output is a synchronized version of the comparator output
bits : 7 - 14 (8 bit)
access : read-write
OA1_COMPINT : Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger)
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled, no interrupts will be detected
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
OA1_PUMP_EN : Opamp1 pump enable
bits : 11 - 22 (12 bit)
access : read-write
OA1_BOOST_EN : Opamp1 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0
bits : 12 - 24 (13 bit)
access : read-write
Opamp0 switch control
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA0P_A00 : Opamp0 positive terminal amuxbusa
bits : 0 - 0 (1 bit)
access : read-write
OA0P_A20 : Opamp0 positive terminal P0
bits : 2 - 4 (3 bit)
access : read-write
OA0P_A30 : Opamp0 positive terminal ctbbus0
bits : 3 - 6 (4 bit)
access : read-write
OA0M_A11 : Opamp0 negative terminal P1
bits : 8 - 16 (9 bit)
access : read-write
OA0M_A81 : Opamp0 negative terminal Opamp0 output
bits : 14 - 28 (15 bit)
access : read-write
OA0O_D51 : Opamp0 output sarbus0 (ctbbus2 in CTB)
bits : 18 - 36 (19 bit)
access : read-write
OA0O_D81 : Opamp0 output switch to short 1x with 10x drive
bits : 21 - 42 (22 bit)
access : read-write
Opamp0 switch control clear
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA0P_A00 : see corresponding bit in OA0_SW
bits : 0 - 0 (1 bit)
access : read-write
OA0P_A20 : see corresponding bit in OA0_SW
bits : 2 - 4 (3 bit)
access : read-write
OA0P_A30 : see corresponding bit in OA0_SW
bits : 3 - 6 (4 bit)
access : read-write
OA0M_A11 : see corresponding bit in OA0_SW
bits : 8 - 16 (9 bit)
access : read-write
OA0M_A81 : see corresponding bit in OA0_SW
bits : 14 - 28 (15 bit)
access : read-write
OA0O_D51 : see corresponding bit in OA0_SW
bits : 18 - 36 (19 bit)
access : read-write
OA0O_D81 : see corresponding bit in OA0_SW
bits : 21 - 42 (22 bit)
access : read-write
Opamp1 switch control
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA1P_A03 : Opamp1 positive terminal amuxbusb
bits : 0 - 0 (1 bit)
access : read-write
OA1P_A13 : Opamp1 positive terminal P5
bits : 1 - 2 (2 bit)
access : read-write
OA1P_A43 : Opamp1 positive terminal ctbbus1
bits : 4 - 8 (5 bit)
access : read-write
OA1P_A73 : Opamp1 positive terminal to vref1
bits : 7 - 14 (8 bit)
access : read-write
OA1M_A22 : Opamp1 negative terminal P4
bits : 8 - 16 (9 bit)
access : read-write
OA1M_A82 : Opamp1 negative terminal Opamp1 output
bits : 14 - 28 (15 bit)
access : read-write
OA1O_D52 : Opamp1 output sarbus0 (ctbbus2 in CTB)
bits : 18 - 36 (19 bit)
access : read-write
OA1O_D62 : Opamp1 output sarbus1 (ctbbus3 in CTB)
bits : 19 - 38 (20 bit)
access : read-write
OA1O_D82 : Opamp1 output switch to short 1x with 10x drive
bits : 21 - 42 (22 bit)
access : read-write
Opamp1 switch control clear
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA1P_A03 : see corresponding bit in OA1_SW
bits : 0 - 0 (1 bit)
access : read-write
OA1P_A13 : see corresponding bit in OA1_SW
bits : 1 - 2 (2 bit)
access : read-write
OA1P_A43 : see corresponding bit in OA1_SW
bits : 4 - 8 (5 bit)
access : read-write
OA1P_A73 : see corresponding bit in OA1_SW
bits : 7 - 14 (8 bit)
access : read-write
OA1M_A22 : see corresponding bit in OA1_SW
bits : 8 - 16 (9 bit)
access : read-write
OA1M_A82 : see corresponding bit in OA1_SW
bits : 14 - 28 (15 bit)
access : read-write
OA1O_D52 : see corresponding bit in OA1_SW
bits : 18 - 36 (19 bit)
access : read-write
OA1O_D62 : see corresponding bit in OA1_SW
bits : 19 - 38 (20 bit)
access : read-write
OA1O_D82 : see corresponding bit in OA1_SW
bits : 21 - 42 (22 bit)
access : read-write
CTDAC connection switch control
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTDD_CRD : CTDAC Reference opamp output to ctdrefdrive
bits : 1 - 2 (2 bit)
access : read-write
CTDS_CRS : ctdrefsense to opamp input
bits : 4 - 8 (5 bit)
access : read-write
CTDS_COR : ctdvout to opamp input
bits : 5 - 10 (6 bit)
access : read-write
CTDO_C6H : P6 pin to Hold capacitor
bits : 8 - 16 (9 bit)
access : read-write
CTDO_COS : ctdvout to Hold capacitor (Sample switch). Note this switch will temporarily be opened for deglitching if CTDAC.DEGLITCH_COS is set
bits : 9 - 18 (10 bit)
access : read-write
CTDH_COB : Drive the CTDAC output with CTBM 1x output during hold mode in Sample and Hold operation
bits : 10 - 20 (11 bit)
access : read-write
CTDH_CHD : Hold capacitor connect
bits : 12 - 24 (13 bit)
access : read-write
CTDH_CA0 : Hold capacitor to opamp input
bits : 13 - 26 (14 bit)
access : read-write
CTDH_CIS : Hold capacitor isolation (from all the other switches)
bits : 14 - 28 (15 bit)
access : read-write
CTDH_ILR : Hold capacitor leakage reduction (drive other side of CIS to capacitor voltage)
bits : 15 - 30 (16 bit)
access : read-write
CTDAC connection switch control clear
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTDD_CRD : see corresponding bit in CTD_SW
bits : 1 - 2 (2 bit)
access : read-write
CTDS_CRS : see corresponding bit in CTD_SW
bits : 4 - 8 (5 bit)
access : read-write
CTDS_COR : see corresponding bit in CTD_SW
bits : 5 - 10 (6 bit)
access : read-write
CTDO_C6H : see corresponding bit in CTD_SW
bits : 8 - 16 (9 bit)
access : read-write
CTDO_COS : see corresponding bit in CTD_SW
bits : 9 - 18 (10 bit)
access : read-write
CTDH_COB : see corresponding bit in CTD_SW
bits : 10 - 20 (11 bit)
access : read-write
CTDH_CHD : see corresponding bit in CTD_SW
bits : 12 - 24 (13 bit)
access : read-write
CTDH_CA0 : see corresponding bit in CTD_SW
bits : 13 - 26 (14 bit)
access : read-write
CTDH_CIS : see corresponding bit in CTD_SW
bits : 14 - 28 (15 bit)
access : read-write
CTDH_ILR : see corresponding bit in CTD_SW
bits : 15 - 30 (16 bit)
access : read-write
Comparator status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OA0_COMP : Opamp0 current comparator status
bits : 0 - 0 (1 bit)
access : read-only
OA1_COMP : Opamp1 current comparator status
bits : 16 - 32 (17 bit)
access : read-only
CTB bus switch control
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2_DS_CTRL23 : for P22, D51 (dsi_out[2])
bits : 10 - 20 (11 bit)
access : read-write
P3_DS_CTRL23 : for P33, D52, D62 (dsi_out[3])
bits : 11 - 22 (12 bit)
access : read-write
CTD_COS_DS_CTRL : Hold capacitor Sample switch (COS)
bits : 31 - 62 (32 bit)
access : read-write
CTB bus switch Sar Sequencer control
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2_SQ_CTRL23 : for D51
bits : 10 - 20 (11 bit)
access : read-write
P3_SQ_CTRL23 : for D52, D62
bits : 11 - 22 (12 bit)
access : read-write
CTB bus switch control status
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OA0O_D51_STAT : see OA0O_D51 bit in OA0_SW
bits : 28 - 56 (29 bit)
access : read-only
OA1O_D52_STAT : see OA1O_D52 bit in OA1_SW
bits : 29 - 58 (30 bit)
access : read-only
OA1O_D62_STAT : see OA1O_D62 bit in OA1_SW
bits : 30 - 60 (31 bit)
access : read-only
CTD_COS_STAT : see COS bit in CTD_SW
bits : 31 - 62 (32 bit)
access : read-only
Opamp0 trim control
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA0_OFFSET_TRIM : Opamp0 offset trim
bits : 0 - 5 (6 bit)
access : read-write
Opamp0 trim control
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA0_SLOPE_OFFSET_TRIM : Opamp0 slope offset drift trim
bits : 0 - 5 (6 bit)
access : read-write
Opamp0 trim control
address_offset : 0xF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA0_COMP_TRIM : Opamp0 Compensation Capacitor Trim. Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11
bits : 0 - 1 (2 bit)
access : read-write
Opamp1 trim control
address_offset : 0xF0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA1_OFFSET_TRIM : Opamp1 offset trim
bits : 0 - 5 (6 bit)
access : read-write
Opamp1 trim control
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA1_SLOPE_OFFSET_TRIM : Opamp1 slope offset drift trim
bits : 0 - 5 (6 bit)
access : read-write
Opamp1 trim control
address_offset : 0xF14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA1_COMP_TRIM : Opamp1 Compensation Capacitor Trim. Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11
bits : 0 - 1 (2 bit)
access : read-write
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