CTDAC_CTRL

CTDAC_VAL

CTDAC_VAL_NXT

INTR

INTR_SET

INTR_MASK

INTR_MASKED

CTDAC_SW

CTDAC_SW_CLEAR

DEGLITCH_CNT : To prevent glitches after VALUE changes from propagating the output switch can be opened for DEGLITCH_CNT+1 clk_peri clock cycles.
bits : 0 - 5 (6 bit)
access : read-write

DEGLITCH_CO6 : Force CTDAC.CO6 switch open after each VALUE change for the set number of clock cycles.
bits : 8 - 16 (9 bit)
access : read-write

DEGLITCH_COS : Force CTB.COS switch open after each VALUE change for the set number of clock cycles.
bits : 9 - 18 (10 bit)
access : read-write

OUT_EN : Output enable, intended to be used during the Hold phase of the Sample and Hold when power cycling : 0: output disabled, the output is either: - Tri-state (DISABLED_MODE=0) - or Vssa (DISABLED_MODE=1 && CTDAC_RANGE=0) - or Vref (DISABLED_MODE=1 && CTDAC_RANGE=1) 1: output enabled, CTDAC output drives the programmed VALUE
bits : 22 - 44 (23 bit)
access : read-write

CTDAC_RANGE : By closing the bottom switch in the R2R network the output is lifted by one LSB, effectively adding 1 0: Range is [0, 4095] * Vref / 4096 1: Range is [1, 4096] * Vref / 4096
bits : 23 - 46 (24 bit)
access : read-write

CTDAC_MODE : DAC mode, this determines the Value decoding
bits : 24 - 49 (26 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DISABLED_MODE : Select the output value when the output is disabled (OUT_EN=0) (for risk mitigation) 0: Tri-state CTDAC output when disabled 1: output Vssa or Vref when disabled (see OUT_EN description)
bits : 27 - 54 (28 bit)
access : read-write

DSI_STROBE_EN : DSI strobe input Enable. This enables CTDAC updates to be further throttled by DSI. 0: Ignore DSI strobe input 1: Only do a CTDAC update if alllowed by the DSI stobe (throttle), see below for level or edge
bits : 28 - 56 (29 bit)
access : read-write

DSI_STROBE_LEVEL : Select level or edge detect for DSI strobe - 0: DSI strobe signal is a pulse input, after a positive edge is detected on the DSI strobe signal the next DAC value update is done on the next CTDAC clock - 1: DSI strobe signal is a level input, as long as the DSI strobe signal remains high the CTDAC will do a next DAC value update on each CTDAC clock.
bits : 29 - 58 (30 bit)
access : read-write

DEEPSLEEP_ON : - 0: CTDAC IP disabled off during DeepSleep power mode - 1: CTDAC IP remains enabled during DeepSleep power mode (if ENABLED=1)
bits : 30 - 60 (31 bit)
access : read-write

ENABLED : 0: CTDAC IP disabled (put analog in power down, open all switches) 1: CTDAC IP enabled
bits : 31 - 62 (32 bit)
access : read-write

VALUE : Value, in CTDAC_MODE 1 this value is decoded
bits : 0 - 11 (12 bit)
access : read-write

VALUE : Next value fpr CTDAC_VAL.VALUE
bits : 0 - 11 (12 bit)
access : read-write

VDAC_EMPTY : VDAC Interrupt: hardware sets this interrupt when VDAC next value field is empty, i.e. was copied to the current VALUE. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write

VDAC_EMPTY_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write

VDAC_EMPTY_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write

VDAC_EMPTY_MASKED : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only

CTDD_CVD : VDDA supply to ctdrefdrive
bits : 0 - 0 (1 bit)
access : read-write

CTDO_CO6 : ctdvout to P6 pin. Note this switch will temporarily be opened for deglitching if DEGLITCH_CO6 is set
bits : 8 - 16 (9 bit)
access : read-write

CTDD_CVD : see corresponding bit in CTD_SW
bits : 0 - 0 (1 bit)
access : read-write

CTDO_CO6 : see corresponding bit in CTD_SW
bits : 8 - 16 (9 bit)
access : read-write