Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
Analog control register.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_CTRL_VREF : VREF buffer low power mode.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : PWR_100
full power (100 percent) (default), bypass cap, max clk_sar is 18MHz.
1 : PWR_80
80 percent power
2 : PWR_60
60 percent power
3 : PWR_50
50 percent power
4 : PWR_40
40 percent power
5 : PWR_30
30 percent power
6 : PWR_20
20 percent power
7 : PWR_10
10 percent power
End of enumeration elements list.
VREF_SEL : SARADC internal VREF selection.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : VREF0
VREF0 from PRB (VREF buffer on)
1 : VREF1
VREF1 from PRB (VREF buffer on)
2 : VREF2
VREF2 from PRB (VREF buffer on)
3 : VREF_AROUTE
VREF from AROUTE (VREF buffer on)
4 : VBGR
1.024V from BandGap (VREF buffer on)
5 : VREF_EXT
External precision Vref direct from a pin (low impedance path).
6 : VDDA_DIV_2
Vdda/2 (VREF buffer on)
7 : VDDA
Vdda.
End of enumeration elements list.
VREF_BYP_CAP_EN : VREF bypass cap enable for when VREF buffer is on
bits : 7 - 14 (8 bit)
access : read-write
NEG_SEL : SARADC internal NEG selection for Single ended conversion
bits : 9 - 20 (12 bit)
access : read-write
Enumeration:
0 : VSSA_KELVIN
NEG input of SARADC is connected to 'vssa_kelvin', gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-before-make cycle on those switches when SWITCH_DISABLE is high.
1 : ART_VSSA
NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC
2 : P1
NEG input of SARADC is connected to P1 pin of SARMUX
3 : P3
NEG input of SARADC is connected to P3 pin of SARMUX
4 : P5
NEG input of SARADC is connected to P5 pin of SARMUX
5 : P7
NEG input of SARADC is connected to P7 pin of SARMUX
6 : ACORE
NEG input of SARADC is connected to an ACORE in AROUTE
7 : VREF
NEG input of SARADC is shorted with VREF input of SARADC.
End of enumeration elements list.
SAR_HW_CTRL_NEGVREF : Hardware control: 0=only firmware control, 1=hardware control masked by firmware setting for VREF to NEG switch.
bits : 13 - 26 (14 bit)
access : read-write
COMP_DLY : Set the comparator latch delay in accordance with SAR conversion rate
bits : 14 - 29 (16 bit)
access : read-write
Enumeration:
0 : D2P5
2.5ns delay, use this for 2.5Msps
1 : D4
4.0ns delay, use this for 2.0Msps
2 : D10
10ns delay, use this for 1.5Msps
3 : D12
12ns delay, use this for 1.0Msps or less
End of enumeration elements list.
SPARE : Spare controls, not yet designated, for late changes done with an ECO
bits : 16 - 35 (20 bit)
access : read-write
BOOSTPUMP_EN : deprecated
bits : 20 - 40 (21 bit)
access : read-write
REFBUF_EN : For normal ADC operation this bit must be set, for all reference choices - internal, external or vdda based reference. Setting this bit is critical to proper function of switches inside SARREF block.
bits : 21 - 42 (22 bit)
access : read-write
COMP_PWR : Comparator power mode. (Sample rate TBD)
bits : 24 - 50 (27 bit)
access : read-write
Enumeration:
0 : P100
Power = 100 percent, use this for >2000Ksps
1 : P80
Power = 80 percent, use this for 1500-2000Ksps
2 : P60
Power = 60 percent, use this for 1000-1500Ksps
3 : P50
Power = 50 percent, use this for 500-1000Ksps
4 : P40
Power = 40 percent, use this for 250-500Ksps
5 : P30
Power = 30 percent, use this for 100-250Ksps
6 : P20
Power = 20 percent, use this for 100-250Ksps (TBD!)
7 : P10
Power = 10 percent, use this for <100Ksps
End of enumeration elements list.
DEEPSLEEP_ON : - 0: SARMUX IP disabled off during DeepSleep power mode - 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1)
bits : 27 - 54 (28 bit)
access : read-write
DSI_SYNC_CONFIG : - 0: bypass clock domain synchronisation of the DSI config signals. - 1: synchronize the DSI config signals to peripheral clock domain.
bits : 28 - 56 (29 bit)
access : read-write
DSI_MODE : SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1) - 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations - 1: CHAN_EN, INJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored
bits : 29 - 58 (30 bit)
access : read-write
SWITCH_DISABLE : Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control) - 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations - 1: Switches disabled, SAR sequencer does not enable any switches, it is the responsibility of the firmware or UDBs (through DSI) to set the switches to route the signal to be converted through the SARMUX
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : - 0: SAR IP disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER and INJ_START_EN (if not tailgaiting) on write. - 1: SAR IP enabled.
bits : 31 - 62 (32 bit)
access : read-write
Sample time specification ST0 and ST1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAMPLE_TIME0 : Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2.
bits : 0 - 9 (10 bit)
access : read-write
SAMPLE_TIME1 : Sample time1
bits : 16 - 41 (26 bit)
access : read-write
Channel configuration register.
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel working data register
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel result data register
address_offset : 0x1134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel working data register
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel result data register
address_offset : 0x12DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel working data register
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Sample time specification ST2 and ST3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAMPLE_TIME2 : Sample time2
bits : 0 - 9 (10 bit)
access : read-write
SAMPLE_TIME3 : Sample time3
bits : 16 - 41 (26 bit)
access : read-write
Channel result data register
address_offset : 0x1488 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel result data register
address_offset : 0x1638 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel result data register
address_offset : 0x17EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Global range detect threshold register.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANGE_LOW : Low threshold for range detect.
bits : 0 - 15 (16 bit)
access : read-write
RANGE_HIGH : High threshold for range detect.
bits : 16 - 47 (32 bit)
access : read-write
Channel configuration register.
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel result data register
address_offset : 0x19A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel result data register
address_offset : 0x1B60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Global range detect mode register.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANGE_COND : Range condition select.
bits : 30 - 61 (32 bit)
access : read-write
Enumeration:
0 : BELOW
result < RANGE_LOW
1 : INSIDE
RANGE_LOW <= result < RANGE_HIGH
2 : ABOVE
RANGE_HIGH <= result
3 : OUTSIDE
result < RANGE_LOW || RANGE_HIGH <= result
End of enumeration elements list.
Enable bits for the channels
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHAN_EN : Channel enable. - 0: the corresponding channel is disabled. - 1: the corresponding channel is enabled, it will be included in the next scan.
bits : 0 - 15 (16 bit)
access : read-write
Channel working data register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel working data register 'updated' bits
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHAN_WORK_UPDATED : If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging.
bits : 0 - 15 (16 bit)
access : read-only
Channel result data register 'updated' bits
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHAN_RESULT_UPDATED : If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging.
bits : 0 - 15 (16 bit)
access : read-only
Channel working data register 'new value' bits
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHAN_WORK_NEWVALUE : If set the corresponding WORK data received a new value, i.e. was already sampled during the current scan and data was valid. In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. In case of averaging this New Value bit is an OR of all the valid bits received by each conversion.
bits : 0 - 15 (16 bit)
access : read-only
Channel configuration register.
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel result data register 'new value' bits
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHAN_RESULT_NEWVALUE : If set the corresponding RESULT data received a new value, i.e. was sampled during the last scan and data was valid. In case of a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid. In case of averaging this New Value bit is an OR of all the valid bits received by each conversion.
bits : 0 - 15 (16 bit)
access : read-only
Interrupt request register.
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOS_INTR : End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
OVERFLOW_INTR : Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write
FW_COLLISION_INTR : Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIGGER has been completed, i.e. not when the preceeding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit.
bits : 2 - 4 (3 bit)
access : read-write
DSI_COLLISION_INTR : DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the DSI trigger has been completed, i.e. not when the preceeding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit.
bits : 3 - 6 (4 bit)
access : read-write
INJ_EOC_INTR : Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used). Write with '1' to clear bit.
bits : 4 - 8 (5 bit)
access : read-write
INJ_SATURATE_INTR : Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit.
bits : 5 - 10 (6 bit)
access : read-write
INJ_RANGE_INTR : Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit.
bits : 6 - 12 (7 bit)
access : read-write
INJ_COLLISION_INTR : Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY. Raising this interrupt is delayed to when the sampling of the injection channel has been completed, i.e. not when the preceeding scan with which this trigger collided is completed. When this interrupt is set it implies that the injection channel was sampled later than was intended. Write with '1' to clear bit.
bits : 7 - 14 (8 bit)
access : read-write
Interrupt set request register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOS_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
OVERFLOW_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
FW_COLLISION_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write
DSI_COLLISION_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 3 - 6 (4 bit)
access : read-write
INJ_EOC_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 4 - 8 (5 bit)
access : read-write
INJ_SATURATE_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 5 - 10 (6 bit)
access : read-write
INJ_RANGE_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 6 - 12 (7 bit)
access : read-write
INJ_COLLISION_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 7 - 14 (8 bit)
access : read-write
Interrupt mask register.
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOS_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write
OVERFLOW_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write
FW_COLLISION_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 2 - 4 (3 bit)
access : read-write
DSI_COLLISION_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 3 - 6 (4 bit)
access : read-write
INJ_EOC_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 4 - 8 (5 bit)
access : read-write
INJ_SATURATE_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 5 - 10 (6 bit)
access : read-write
INJ_RANGE_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 6 - 12 (7 bit)
access : read-write
INJ_COLLISION_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 7 - 14 (8 bit)
access : read-write
Interrupt masked request register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EOS_MASKED : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only
OVERFLOW_MASKED : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only
FW_COLLISION_MASKED : Logical and of corresponding request and mask bits.
bits : 2 - 4 (3 bit)
access : read-only
DSI_COLLISION_MASKED : Logical and of corresponding request and mask bits.
bits : 3 - 6 (4 bit)
access : read-only
INJ_EOC_MASKED : Logical and of corresponding request and mask bits.
bits : 4 - 8 (5 bit)
access : read-only
INJ_SATURATE_MASKED : Logical and of corresponding request and mask bits.
bits : 5 - 10 (6 bit)
access : read-only
INJ_RANGE_MASKED : Logical and of corresponding request and mask bits.
bits : 6 - 12 (7 bit)
access : read-only
INJ_COLLISION_MASKED : Logical and of corresponding request and mask bits.
bits : 7 - 14 (8 bit)
access : read-only
Saturate interrupt request register.
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SATURATE_INTR : Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit.
bits : 0 - 15 (16 bit)
access : read-write
Saturate interrupt set request register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SATURATE_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 15 (16 bit)
access : read-write
Saturate interrupt mask register.
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SATURATE_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 15 (16 bit)
access : read-write
Saturate interrupt masked request register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SATURATE_MASKED : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
Range detect interrupt request register.
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANGE_INTR : Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit.
bits : 0 - 15 (16 bit)
access : read-write
Range detect interrupt set request register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANGE_SET : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 15 (16 bit)
access : read-write
Range detect interrupt mask register.
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANGE_MASK : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 15 (16 bit)
access : read-write
Range interrupt masked request register
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RANGE_MASKED : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
Start control register (firmware trigger).
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FW_TRIGGER : When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled.
bits : 0 - 0 (1 bit)
access : read-write
Interrupt cause register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EOS_MASKED_MIR : Mirror copy of corresponding bit in SAR_INTR_MASKED
bits : 0 - 0 (1 bit)
access : read-only
OVERFLOW_MASKED_MIR : Mirror copy of corresponding bit in SAR_INTR_MASKED
bits : 1 - 2 (2 bit)
access : read-only
FW_COLLISION_MASKED_MIR : Mirror copy of corresponding bit in SAR_INTR_MASKED
bits : 2 - 4 (3 bit)
access : read-only
DSI_COLLISION_MASKED_MIR : Mirror copy of corresponding bit in SAR_INTR_MASKED
bits : 3 - 6 (4 bit)
access : read-only
INJ_EOC_MASKED_MIR : Mirror copy of corresponding bit in SAR_INTR_MASKED
bits : 4 - 8 (5 bit)
access : read-only
INJ_SATURATE_MASKED_MIR : Mirror copy of corresponding bit in SAR_INTR_MASKED
bits : 5 - 10 (6 bit)
access : read-only
INJ_RANGE_MASKED_MIR : Mirror copy of corresponding bit in SAR_INTR_MASKED
bits : 6 - 12 (7 bit)
access : read-only
INJ_COLLISION_MASKED_MIR : Mirror copy of corresponding bit in SAR_INTR_MASKED
bits : 7 - 14 (8 bit)
access : read-only
SATURATE_MASKED_RED : Reduction OR of all SAR_SATURATION_INTR_MASKED bits
bits : 30 - 60 (31 bit)
access : read-only
RANGE_MASKED_RED : Reduction OR of all SAR_RANGE_INTR_MASKED bits
bits : 31 - 62 (32 bit)
access : read-only
Injection channel configuration register.
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INJ_PIN_ADDR : Address of the pin to be sampled by this injection channel. If differential is enabled then INJ_PIN_ADDR[0] is ignored and considered to be 0, i.e. INJ_PIN_ADDR points to the even pin of a pin pair.
bits : 0 - 2 (3 bit)
access : read-write
INJ_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel.
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
6 : AROUTE_VIRT
AROUTE virtual port
7 : SARMUX_VIRT
SARMUX virtual port
End of enumeration elements list.
INJ_DIFFERENTIAL_EN : Differential enable for this channel. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (INJ_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
INJ_AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
INJ_SAMPLE_TIME_SEL : Injection sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
INJ_TAILGATING : Injection channel tailgating. - 0: no tailgating for this channel, SAR is immediately triggered when the INJ_START_EN bit is set. - 1: injection channel tailgating. The addressed pin is sampled after the next trigger and after all enabled channels have been scanned.
bits : 30 - 60 (31 bit)
access : read-write
INJ_START_EN : Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit also functions as trigger for this channel. Cleared by hardware after this channel has been sampled (i.e. this channel is always one shot even if CONTINUOUS is set). Also cleared if the SAR is disabled.
bits : 31 - 62 (32 bit)
access : read-write
Injection channel result register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INJ_RESULT : SAR conversion result of the channel.
bits : 0 - 15 (16 bit)
access : read-only
INJ_NEWVALUE : The data in this register received a new value (only relevant for UAB, this bit shows the value of the UAB valid bit)
bits : 27 - 54 (28 bit)
access : read-only
INJ_COLLISION_INTR_MIR : mirror bit of corresponding bit in SAR_INTR register
bits : 28 - 56 (29 bit)
access : read-only
INJ_SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_INTR register
bits : 29 - 58 (30 bit)
access : read-only
INJ_RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_INTR register
bits : 30 - 60 (31 bit)
access : read-only
INJ_EOC_INTR_MIR : mirror bit of corresponding bit in SAR_INTR register
bits : 31 - 62 (32 bit)
access : read-only
Channel configuration register.
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Current status of internal SAR registers (mostly for debug)
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CUR_CHAN : current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY.
bits : 0 - 4 (5 bit)
access : read-only
SW_VREF_NEG : the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL).
bits : 30 - 60 (31 bit)
access : read-only
BUSY : If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down.
bits : 31 - 62 (32 bit)
access : read-only
Current averaging status (for debug)
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CUR_AVG_ACCU : the current value of the averaging accumulator
bits : 0 - 19 (20 bit)
access : read-only
INTRLV_BUSY : If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging. This bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR.
bits : 23 - 46 (24 bit)
access : read-only
CUR_AVG_CNT : the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update.
bits : 24 - 55 (32 bit)
access : read-only
Channel result data register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
SARMUX Firmware switch controls
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_FW_P0_VPLUS : Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with '1' to set bit.
bits : 0 - 0 (1 bit)
access : read-write
MUX_FW_P1_VPLUS : Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with '1' to set bit.
bits : 1 - 2 (2 bit)
access : read-write
MUX_FW_P2_VPLUS : Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with '1' to set bit.
bits : 2 - 4 (3 bit)
access : read-write
MUX_FW_P3_VPLUS : Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with '1' to set bit.
bits : 3 - 6 (4 bit)
access : read-write
MUX_FW_P4_VPLUS : Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with '1' to set bit.
bits : 4 - 8 (5 bit)
access : read-write
MUX_FW_P5_VPLUS : Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with '1' to set bit.
bits : 5 - 10 (6 bit)
access : read-write
MUX_FW_P6_VPLUS : Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with '1' to set bit.
bits : 6 - 12 (7 bit)
access : read-write
MUX_FW_P7_VPLUS : Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with '1' to set bit.
bits : 7 - 14 (8 bit)
access : read-write
MUX_FW_P0_VMINUS : Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with '1' to set bit.
bits : 8 - 16 (9 bit)
access : read-write
MUX_FW_P1_VMINUS : Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with '1' to set bit.
bits : 9 - 18 (10 bit)
access : read-write
MUX_FW_P2_VMINUS : Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with '1' to set bit.
bits : 10 - 20 (11 bit)
access : read-write
MUX_FW_P3_VMINUS : Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with '1' to set bit.
bits : 11 - 22 (12 bit)
access : read-write
MUX_FW_P4_VMINUS : Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with '1' to set bit.
bits : 12 - 24 (13 bit)
access : read-write
MUX_FW_P5_VMINUS : Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with '1' to set bit.
bits : 13 - 26 (14 bit)
access : read-write
MUX_FW_P6_VMINUS : Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with '1' to set bit.
bits : 14 - 28 (15 bit)
access : read-write
MUX_FW_P7_VMINUS : Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with '1' to set bit.
bits : 15 - 30 (16 bit)
access : read-write
MUX_FW_VSSA_VMINUS : Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write with '1' to set bit.
bits : 16 - 32 (17 bit)
access : read-write
MUX_FW_TEMP_VPLUS : Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, also powers on the temperature sensor. Write with '1' to set bit.
bits : 17 - 34 (18 bit)
access : read-write
MUX_FW_AMUXBUSA_VPLUS : Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write with '1' to set bit.
bits : 18 - 36 (19 bit)
access : read-write
MUX_FW_AMUXBUSB_VPLUS : Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write with '1' to set bit.
bits : 19 - 38 (20 bit)
access : read-write
MUX_FW_AMUXBUSA_VMINUS : Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write with '1' to set bit.
bits : 20 - 40 (21 bit)
access : read-write
MUX_FW_AMUXBUSB_VMINUS : Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write with '1' to set bit.
bits : 21 - 42 (22 bit)
access : read-write
MUX_FW_SARBUS0_VPLUS : Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with '1' to set bit.
bits : 22 - 44 (23 bit)
access : read-write
MUX_FW_SARBUS1_VPLUS : Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with '1' to set bit.
bits : 23 - 46 (24 bit)
access : read-write
MUX_FW_SARBUS0_VMINUS : Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write with '1' to set bit.
bits : 24 - 48 (25 bit)
access : read-write
MUX_FW_SARBUS1_VMINUS : Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write with '1' to set bit.
bits : 25 - 50 (26 bit)
access : read-write
MUX_FW_P4_COREIO0 : Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with '1' to set bit.
bits : 26 - 52 (27 bit)
access : read-write
MUX_FW_P5_COREIO1 : Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with '1' to set bit.
bits : 27 - 54 (28 bit)
access : read-write
MUX_FW_P6_COREIO2 : Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with '1' to set bit.
bits : 28 - 56 (29 bit)
access : read-write
MUX_FW_P7_COREIO3 : Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with '1' to set bit.
bits : 29 - 58 (30 bit)
access : read-write
Channel working data register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
SARMUX Firmware switch control clear
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_FW_P0_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 0 - 0 (1 bit)
access : read-write
MUX_FW_P1_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 1 - 2 (2 bit)
access : read-write
MUX_FW_P2_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 2 - 4 (3 bit)
access : read-write
MUX_FW_P3_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 3 - 6 (4 bit)
access : read-write
MUX_FW_P4_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 4 - 8 (5 bit)
access : read-write
MUX_FW_P5_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 5 - 10 (6 bit)
access : read-write
MUX_FW_P6_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 6 - 12 (7 bit)
access : read-write
MUX_FW_P7_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 7 - 14 (8 bit)
access : read-write
MUX_FW_P0_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 8 - 16 (9 bit)
access : read-write
MUX_FW_P1_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 9 - 18 (10 bit)
access : read-write
MUX_FW_P2_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 10 - 20 (11 bit)
access : read-write
MUX_FW_P3_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 11 - 22 (12 bit)
access : read-write
MUX_FW_P4_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 12 - 24 (13 bit)
access : read-write
MUX_FW_P5_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 13 - 26 (14 bit)
access : read-write
MUX_FW_P6_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 14 - 28 (15 bit)
access : read-write
MUX_FW_P7_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 15 - 30 (16 bit)
access : read-write
MUX_FW_VSSA_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 16 - 32 (17 bit)
access : read-write
MUX_FW_TEMP_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 17 - 34 (18 bit)
access : read-write
MUX_FW_AMUXBUSA_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 18 - 36 (19 bit)
access : read-write
MUX_FW_AMUXBUSB_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 19 - 38 (20 bit)
access : read-write
MUX_FW_AMUXBUSA_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 20 - 40 (21 bit)
access : read-write
MUX_FW_AMUXBUSB_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 21 - 42 (22 bit)
access : read-write
MUX_FW_SARBUS0_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 22 - 44 (23 bit)
access : read-write
MUX_FW_SARBUS1_VPLUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 23 - 46 (24 bit)
access : read-write
MUX_FW_SARBUS0_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 24 - 48 (25 bit)
access : read-write
MUX_FW_SARBUS1_VMINUS : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 25 - 50 (26 bit)
access : read-write
MUX_FW_P4_COREIO0 : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 26 - 52 (27 bit)
access : read-write
MUX_FW_P5_COREIO1 : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 27 - 54 (28 bit)
access : read-write
MUX_FW_P6_COREIO2 : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 28 - 56 (29 bit)
access : read-write
MUX_FW_P7_COREIO3 : Write '1' to clear corresponding bit in MUX_SWITCH0
bits : 29 - 58 (30 bit)
access : read-write
Channel configuration register.
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
SARMUX switch DSI control
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_DS_CTRL_P0 : for P0 switches
bits : 0 - 0 (1 bit)
access : read-write
MUX_DS_CTRL_P1 : for P1 switches
bits : 1 - 2 (2 bit)
access : read-write
MUX_DS_CTRL_P2 : for P2 switches
bits : 2 - 4 (3 bit)
access : read-write
MUX_DS_CTRL_P3 : for P3 switches
bits : 3 - 6 (4 bit)
access : read-write
MUX_DS_CTRL_P4 : for P4 switches
bits : 4 - 8 (5 bit)
access : read-write
MUX_DS_CTRL_P5 : for P5 switches
bits : 5 - 10 (6 bit)
access : read-write
MUX_DS_CTRL_P6 : for P6 switches
bits : 6 - 12 (7 bit)
access : read-write
MUX_DS_CTRL_P7 : for P7 switches
bits : 7 - 14 (8 bit)
access : read-write
MUX_DS_CTRL_VSSA : for vssa switch
bits : 16 - 32 (17 bit)
access : read-write
MUX_DS_CTRL_TEMP : for temp switch
bits : 17 - 34 (18 bit)
access : read-write
MUX_DS_CTRL_AMUXBUSA : for amuxbusa switch
bits : 18 - 36 (19 bit)
access : read-write
MUX_DS_CTRL_AMUXBUSB : for amuxbusb switches
bits : 19 - 38 (20 bit)
access : read-write
MUX_DS_CTRL_SARBUS0 : for sarbus0 switch
bits : 22 - 44 (23 bit)
access : read-write
MUX_DS_CTRL_SARBUS1 : for sarbus1 switch
bits : 23 - 46 (24 bit)
access : read-write
SARMUX switch Sar Sequencer control
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUX_SQ_CTRL_P0 : for P0 switches
bits : 0 - 0 (1 bit)
access : read-write
MUX_SQ_CTRL_P1 : for P1 switches
bits : 1 - 2 (2 bit)
access : read-write
MUX_SQ_CTRL_P2 : for P2 switches
bits : 2 - 4 (3 bit)
access : read-write
MUX_SQ_CTRL_P3 : for P3 switches
bits : 3 - 6 (4 bit)
access : read-write
MUX_SQ_CTRL_P4 : for P4 switches
bits : 4 - 8 (5 bit)
access : read-write
MUX_SQ_CTRL_P5 : for P5 switches
bits : 5 - 10 (6 bit)
access : read-write
MUX_SQ_CTRL_P6 : for P6 switches
bits : 6 - 12 (7 bit)
access : read-write
MUX_SQ_CTRL_P7 : for P7 switches
bits : 7 - 14 (8 bit)
access : read-write
MUX_SQ_CTRL_VSSA : for vssa switch
bits : 16 - 32 (17 bit)
access : read-write
MUX_SQ_CTRL_TEMP : for temp switch
bits : 17 - 34 (18 bit)
access : read-write
MUX_SQ_CTRL_AMUXBUSA : for amuxbusa switch
bits : 18 - 36 (19 bit)
access : read-write
MUX_SQ_CTRL_AMUXBUSB : for amuxbusb switches
bits : 19 - 38 (20 bit)
access : read-write
MUX_SQ_CTRL_SARBUS0 : for sarbus0 switch
bits : 22 - 44 (23 bit)
access : read-write
MUX_SQ_CTRL_SARBUS1 : for sarbus1 switch
bits : 23 - 46 (24 bit)
access : read-write
SARMUX switch status
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MUX_FW_P0_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 0 - 0 (1 bit)
access : read-only
MUX_FW_P1_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 1 - 2 (2 bit)
access : read-only
MUX_FW_P2_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 2 - 4 (3 bit)
access : read-only
MUX_FW_P3_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 3 - 6 (4 bit)
access : read-only
MUX_FW_P4_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 4 - 8 (5 bit)
access : read-only
MUX_FW_P5_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 5 - 10 (6 bit)
access : read-only
MUX_FW_P6_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 6 - 12 (7 bit)
access : read-only
MUX_FW_P7_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 7 - 14 (8 bit)
access : read-only
MUX_FW_P0_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 8 - 16 (9 bit)
access : read-only
MUX_FW_P1_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 9 - 18 (10 bit)
access : read-only
MUX_FW_P2_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 10 - 20 (11 bit)
access : read-only
MUX_FW_P3_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 11 - 22 (12 bit)
access : read-only
MUX_FW_P4_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 12 - 24 (13 bit)
access : read-only
MUX_FW_P5_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 13 - 26 (14 bit)
access : read-only
MUX_FW_P6_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 14 - 28 (15 bit)
access : read-only
MUX_FW_P7_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 15 - 30 (16 bit)
access : read-only
MUX_FW_VSSA_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 16 - 32 (17 bit)
access : read-only
MUX_FW_TEMP_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 17 - 34 (18 bit)
access : read-only
MUX_FW_AMUXBUSA_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 18 - 36 (19 bit)
access : read-only
MUX_FW_AMUXBUSB_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 19 - 38 (20 bit)
access : read-only
MUX_FW_AMUXBUSA_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 20 - 40 (21 bit)
access : read-only
MUX_FW_AMUXBUSB_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 21 - 42 (22 bit)
access : read-only
MUX_FW_SARBUS0_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 22 - 44 (23 bit)
access : read-only
MUX_FW_SARBUS1_VPLUS : switch status of corresponding bit in MUX_SWITCH0
bits : 23 - 46 (24 bit)
access : read-only
MUX_FW_SARBUS0_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 24 - 48 (25 bit)
access : read-only
MUX_FW_SARBUS1_VMINUS : switch status of corresponding bit in MUX_SWITCH0
bits : 25 - 50 (26 bit)
access : read-only
Channel configuration register.
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Sample control register.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEFT_ALIGN : Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential.
bits : 1 - 2 (2 bit)
access : read-write
SINGLE_ENDED_SIGNED : Output data from a single ended conversion as a signed value
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : UNSIGNED
Default: result data is unsigned (zero extended if needed)
1 : SIGNED
result data is signed (sign extended if needed)
End of enumeration elements list.
DIFFERENTIAL_SIGNED : Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NEG_ADDR_EN is set to 1
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : UNSIGNED
result data is unsigned (zero extended if needed)
1 : SIGNED
Default: result data is signed (sign extended if needed)
End of enumeration elements list.
AVG_CNT : Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be sampled (1<<(AVG_CNT+1)) = [2..256] times. - In ACCUNDUMP mode (1st order accumulate and dump filter) a channel will be sampled back to back, the average result is calculated and stored and then the next enabled channel is sampled. If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3). - In INTERLEAVED mode one sample is taken per triggered scan, only in the scan where the final averaging count is reached a valid average is calculated and stored in the RESULT register (by definition the same scan for all the channels that have averaging enabled). In all other scans the RESULT register for averaged channels will have an invalid result and the intermediate accumulated value is stored in the 16-bit WORK register. In this mode make sure that the averaging count is low enough to ensure that the intermediate value does not exceed 16-bits otherwise the MSBs will be lost. So for a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=<3).
bits : 4 - 10 (7 bit)
access : read-write
AVG_SHIFT : Averaging shifting: after averaging the result is shifted right to fit in 12 bits.
bits : 7 - 14 (8 bit)
access : read-write
AVG_MODE : Averaging mode, in DSI mode this bit is ignored and only AccuNDump mode is available.
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : ACCUNDUMP
Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged
1 : INTERLEAVED
Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans.
End of enumeration elements list.
CONTINUOUS : - 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels. - 1: Continuously scan enabled channels, ignore triggers.
bits : 16 - 32 (17 bit)
access : read-write
DSI_TRIGGER_EN : - 0: firmware trigger only: disable hardware trigger tr_sar_in. - 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB).
bits : 17 - 34 (18 bit)
access : read-write
DSI_TRIGGER_LEVEL : - 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan. - 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans.
bits : 18 - 36 (19 bit)
access : read-write
DSI_SYNC_TRIGGER : - 0: bypass clock domain synchronisation of the trigger signal. - 1: synchronize the trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain.
bits : 19 - 38 (20 bit)
access : read-write
UAB_SCAN_MODE : Select whether UABs are scheduled or unscheduled. When no UAB is scanned this selection is ignored.
bits : 22 - 44 (23 bit)
access : read-write
Enumeration:
0 : UNSCHEDULED
Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for each channel that scans a UAB the SAR will wait for a positive edge on the trigger output of that UAB. Caveat: in this mode the length of SAR scan can be variable.
1 : SCHEDULED
Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e. their output is assumed to be valid when sampled by the SAR and the SAR does not wait. In this mode the length of the SAR scan is constant.
This mode requires that the SAR scans strictly periodically, i.e. the SAR has to either run continuously or has to be triggered by a periodic hardware trigger (TCPWM or UDB timer). It also requires that the end of the UAB valid phase is precisely aligned with the end of the SAR sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator.
End of enumeration elements list.
REPEAT_INVALID : For unscheduled UAB_SCAN_MODE only, do the following if an invalid sample is received: - 0: use the last known valid sample for that channel and clear the NEWVALUE flag - 1: repeat the conversions until a valid sample is received (caveat: could be never if the UAB valid window is incorrectly schedule w.r.t. SAR sampling)
bits : 23 - 46 (24 bit)
access : read-write
VALID_SEL : Static UAB Valid select 0=UAB0 half 0 Valid output 1=UAB0 half 1 Valid output 2=UAB1 half 0 Valid output 3=UAB1 half 1 Valid output 4=UAB2 half 0 Valid output 5=UAB2 half 1 Valid output 6=UAB3 half 0 Valid output 7=UAB3 half 1 Valid output
bits : 24 - 50 (27 bit)
access : read-write
VALID_SEL_EN : Enable static UAB Valid selection (override Hardware)
bits : 27 - 54 (28 bit)
access : read-write
VALID_IGNORE : Ignore UAB valid signal, including the dynamic/Hardware from AROUTE and the static Valid selection from the VALID_SEL fields above
bits : 28 - 56 (29 bit)
access : read-write
TRIGGER_OUT_EN : SAR output trigger enable (used for UAB synchronization). To ensure multiple UABs starting at the same trigger it is recommended to use this bit to temporarily disable the trigger output until all those UABs are set to run (UAB.SRAM_CTRL.RUN=1).
bits : 30 - 60 (31 bit)
access : read-write
EOS_DSI_OUT_EN : Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal.
bits : 31 - 62 (32 bit)
access : read-write
Channel working data register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel configuration register.
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel result data register
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel configuration register.
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel working data register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel configuration register.
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel result data register
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel working data register
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel configuration register.
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel configuration register.
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel working data register
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel configuration register.
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel result data register
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel configuration register.
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel working data register
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel configuration register.
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel result data register
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel working data register
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel configuration register.
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel configuration register.
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS_PIN_ADDR : Address of the pin to be sampled by this channel (connected to Vplus)
bits : 0 - 2 (3 bit)
access : read-write
POS_PORT_ADDR : Address of the port that contains the pin to be sampled by this channel (connected to Vplus)
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
1 : CTB0
CTB0
2 : CTB1
CTB1
3 : CTB2
CTB2
4 : CTB3
CTB3
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
DIFFERENTIAL_EN : Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).
bits : 8 - 16 (9 bit)
access : read-write
AVG_EN : Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)
bits : 10 - 20 (11 bit)
access : read-write
SAMPLE_TIME_SEL : Sample time select: select which of the 4 global sample times to use for this channel
bits : 12 - 25 (14 bit)
access : read-write
NEG_PIN_ADDR : Address of the neg pin to be sampled by this channel.
bits : 16 - 34 (19 bit)
access : read-write
NEG_PORT_ADDR : Address of the neg port that contains the pin to be sampled by this channel.
bits : 20 - 42 (23 bit)
access : read-write
Enumeration:
0 : SARMUX
SARMUX pins.
5 : AROUTE_VIRT2
AROUTE virtual port2 (VPORT2)
6 : AROUTE_VIRT1
AROUTE virtual port1 (VPORT1)
7 : SARMUX_VIRT
SARMUX virtual port (VPORT0)
End of enumeration elements list.
NEG_ADDR_EN : 1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin.
bits : 24 - 48 (25 bit)
access : read-write
DSI_OUT_EN : DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formating), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.
bits : 31 - 62 (32 bit)
access : read-write
Channel working data register
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel result data register
address_offset : 0xABC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel working data register
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel result data register
address_offset : 0xC54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel working data register
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel result data register
address_offset : 0xDF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel working data register
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Analog trim register.
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAP_TRIM : Attenuation cap trimming
bits : 0 - 4 (5 bit)
access : read-write
TRIMUNIT : Attenuation cap trimming
bits : 5 - 10 (6 bit)
access : read-write
Analog trim register.
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR_REF_BUF_TRIM : SAR Reference buffer trim
bits : 0 - 5 (6 bit)
access : read-write
Channel working data register
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WORK : SAR conversion working data of the channel. The data is written here right after sampling this channel.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_WORK_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
CHAN_WORK_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
Channel result data register
address_offset : 0xF90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.
bits : 0 - 15 (16 bit)
access : read-only
CHAN_RESULT_NEWVALUE_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register
bits : 27 - 54 (28 bit)
access : read-only
SATURATE_INTR_MIR : mirror bit of corresponding bit in SAR_SATURATE_INTR register
bits : 29 - 58 (30 bit)
access : read-only
RANGE_INTR_MIR : mirror bit of corresponding bit in SAR_RANGE_INTR register
bits : 30 - 60 (31 bit)
access : read-only
CHAN_RESULT_UPDATED_MIR : mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
bits : 31 - 62 (32 bit)
access : read-only
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