\n

PASS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

INTR_CAUSE

AREF - AREF_CTRL

VREF_TRIM0

VREF_TRIM1

VREF_TRIM2

VREF_TRIM3

IZTAT_TRIM0

IZTAT_TRIM1

IPTAT_TRIM0

ICTAT_TRIM0


INTR_CAUSE

Interrupt cause register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTR_CAUSE INTR_CAUSE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTB0_INT CTB1_INT CTB2_INT CTB3_INT CTDAC0_INT CTDAC1_INT CTDAC2_INT CTDAC3_INT

CTB0_INT : CTB0 interrupt pending
bits : 0 - 0 (1 bit)
access : read-only

CTB1_INT : CTB1 interrupt pending
bits : 1 - 2 (2 bit)
access : read-only

CTB2_INT : CTB2 interrupt pending
bits : 2 - 4 (3 bit)
access : read-only

CTB3_INT : CTB3 interrupt pending
bits : 3 - 6 (4 bit)
access : read-only

CTDAC0_INT : CTDAC0 interrupt pending
bits : 4 - 8 (5 bit)
access : read-only

CTDAC1_INT : CTDAC1 interrupt pending
bits : 5 - 10 (6 bit)
access : read-only

CTDAC2_INT : CTDAC2 interrupt pending
bits : 6 - 12 (7 bit)
access : read-only

CTDAC3_INT : CTDAC3 interrupt pending
bits : 7 - 14 (8 bit)
access : read-only


AREF - AREF_CTRL

AREF configuration - - global AREF control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREF - AREF_CTRL AREF - AREF_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AREF_MODE AREF_BIAS_SCALE AREF_RMB CTB_IPTAT_SCALE CTB_IPTAT_REDIRECT IZTAT_SEL CLOCK_PUMP_PERI_SEL VREF_SEL DEEPSLEEP_MODE DEEPSLEEP_ON ENABLED

AREF_MODE : Control bit to trade off AREF settling and noise performance
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NORMAL

Nominal noise normal startup mode (meets normal mode settling and noise specifications)

1 : FAST_START

High noise fast startup mode (meets fast mode settling and noise specifications)

End of enumeration elements list.

AREF_BIAS_SCALE : BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized) 0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times) 1: 250nA ('default' setting to meet bandgap performance (noise/startup) and IDDA specifications) 2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times) 3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times)
bits : 2 - 5 (4 bit)
access : read-write

AREF_RMB : AREF control signals (RMB). Bit 0: Manual VBG startup circuit enable 0: normal VBG startup circuit operation 1: VBG startup circuit is forced 'always on' Bit 1: Manual disable of IPTAT2 DAC 0: normal IPTAT2 DAC operation 1: PTAT2 DAC is disabled while VBG startup is active Bit 2: Manual enable of VBG offset correction DAC 0: normal VBG offset correction DAC operation 1: VBG offset correction DAC is enabled while VBG startup is active
bits : 4 - 10 (7 bit)
access : read-write

CTB_IPTAT_SCALE : CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers). 0: 1uA 1: 100nA
bits : 7 - 14 (8 bit)
access : read-write

CTB_IPTAT_REDIRECT : Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility). 0: Opamp.IPTAT = AREF.IPTAT and Opamp.IZTAT= AREF.IZTAT 1: Opamp.IPTAT = HiZ and Opamp.IZTAT= AREF.IPTAT *Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp.IZTAT/IPTAT will be HiZ.
bits : 8 - 23 (16 bit)
access : read-write

IZTAT_SEL : iztat current select control
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

0 : SRSS

Use 250nA IZTAT from SRSS

1 : LOCAL

Use locally generated 250nA

End of enumeration elements list.

CLOCK_PUMP_PERI_SEL : CTBm charge pump clock source select. This field has nothing to do with the AREF. 0: Use the dedicated pump clock from SRSS (default) 1: Use one of the CLK_PERI dividers
bits : 19 - 38 (20 bit)
access : read-write

VREF_SEL : bandgap voltage select control
bits : 20 - 41 (22 bit)
access : read-write

Enumeration:

0 : SRSS

Use 0.8V Vref from SRSS

1 : LOCAL

Use locally generated Vref

2 : EXTERNAL

Use externally supplied Vref (aref_ext_vref)

End of enumeration elements list.

DEEPSLEEP_MODE : AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1)
bits : 28 - 57 (30 bit)
access : read-write

Enumeration:

0 : OFF

All blocks 'OFF' in DeepSleep

1 : IPTAT

IPTAT bias generator 'ON' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available)

2 : IPTAT_IZTAT

IPTAT bias generator and outputs 'ON' in DeepSleep (used for biasing the CTBm with a PTAT current only in deepsleep) *Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep

3 : IPTAT_IZTAT_VREF

IPTAT, VREF, and IZTAT generators 'ON' in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode.

End of enumeration elements list.

DEEPSLEEP_ON : - 0: AREF IP disabled/off during DeepSleep power mode - 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1)
bits : 30 - 60 (31 bit)
access : read-write

ENABLED : Disable AREF
bits : 31 - 62 (32 bit)
access : read-write


VREF_TRIM0

VREF Trim bits
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREF_TRIM0 VREF_TRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF_ABS_TRIM

VREF_ABS_TRIM : N/A
bits : 0 - 7 (8 bit)
access : read-write


VREF_TRIM1

VREF Trim bits
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREF_TRIM1 VREF_TRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF_TEMPCO_TRIM

VREF_TEMPCO_TRIM : N/A
bits : 0 - 7 (8 bit)
access : read-write


VREF_TRIM2

VREF Trim bits
address_offset : 0xF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREF_TRIM2 VREF_TRIM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF_CURV_TRIM

VREF_CURV_TRIM : N/A
bits : 0 - 7 (8 bit)
access : read-write


VREF_TRIM3

VREF Trim bits
address_offset : 0xF0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREF_TRIM3 VREF_TRIM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF_ATTEN_TRIM

VREF_ATTEN_TRIM : Obsolete
bits : 0 - 3 (4 bit)
access : read-write


IZTAT_TRIM0

IZTAT Trim bits
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IZTAT_TRIM0 IZTAT_TRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IZTAT_ABS_TRIM

IZTAT_ABS_TRIM : N/A
bits : 0 - 7 (8 bit)
access : read-write


IZTAT_TRIM1

IZTAT Trim bits
address_offset : 0xF14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IZTAT_TRIM1 IZTAT_TRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IZTAT_TC_TRIM

IZTAT_TC_TRIM : IZTAT temperature correction trim (RMB) 0x00 : No IZTAT temperature correction 0xFF : Maximum IZTAT temperature correction As this is a Risk Mitigation Register, it should be loaded with 0x08.
bits : 0 - 7 (8 bit)
access : read-write


IPTAT_TRIM0

IPTAT Trim bits
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPTAT_TRIM0 IPTAT_TRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPTAT_CORE_TRIM IPTAT_CTBM_TRIM

IPTAT_CORE_TRIM : IPTAT trim 0x0 : Minimum IPTAT current (~150nA at room) 0xF : Maximum IPTAT current (~350nA at room)
bits : 0 - 3 (4 bit)
access : read-write

IPTAT_CTBM_TRIM : CTMB PTAT Current Trim 0x0 : Minimum CTMB IPTAT Current (~875nA) 0xF : Maximum CTMB IPTAT Current (~1.1uA)
bits : 4 - 11 (8 bit)
access : read-write


ICTAT_TRIM0

ICTAT Trim bits
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICTAT_TRIM0 ICTAT_TRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICTAT_TRIM

ICTAT_TRIM : ICTAT trim 0x00 : Minimum ICTAT current (~150nA at room) 0x0F : Maximum ICTAT current (~350nA at room)
bits : 0 - 3 (4 bit)
access : read-write



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