CTL

CLOCK_CTL

MODE_CTL

DATA_CTL

CMD

RX_FIFO_CTL

RX_FIFO_STATUS

RX_FIFO_RD

RX_FIFO_RD_SILENT

TR_CTL

INTR

INTR_SET

INTR_MASK

INTR_MASKED

PGA_R : Right channel PGA gain: +1.5dB/step, -12dB ~ +10.5dB '0': -12 dB '1': -10.5 dB ... '15' +10.5 dB (Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_R)
bits : 0 - 3 (4 bit)
access : read-write

PGA_L : Left channel PGA gain: +1.5dB/step, -12dB ~ +10.5dB '0': -12 dB '1': -10.5 dB ... '15': +10.5 dB (Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_L)
bits : 8 - 19 (12 bit)
access : read-write

SOFT_MUTE : Soft mute function to mute the volume smoothly '0': Disabled. '1': Enabled. (Note: This bit is connected to AR36U12.PDM_CORE_CFG.SOFT_MUTE)
bits : 16 - 32 (17 bit)
access : read-write

STEP_SEL : Set fine gain step for smooth PGA or Soft-Mute attenuation transition. '0': 0.13dB '1': 0.26dB (Note: This bit is connected to AR36U12.PDM_CORE2_CFG.SEL_STEP)
bits : 17 - 34 (18 bit)
access : read-write

ENABLED : Enables the PDM component: '0': Disabled. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write

CLK_CLOCK_DIV : PDM CLK (FPDM_CLK) (1st divider): This configures a frequency of PDM CLK. The configured frequency is used to operate PDM core. I.e. the frequency is input to MCLKQ_CLOCK_DIV register. Note: configure a frequency of PDM CLK as lower than or equal 50MHz with this divider.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MCLKQ_CLOCK_DIV : MCLKQ divider (2nd divider) (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.DIV_MCLKQ)
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CKO_CLOCK_DIV : PDM CKO (FPDM_CKO) clock divider (3rd divider): FPDM_CKO = MCLKQ / (CKO_CLOCK_DIV + 1) Note: To configure '0' to this field is prohibited. (Note: PDM_CKO is configured by MCLKQ_CLOCK_DIV, CLK_CLOCK_DIV and CKO_CLOCK_DIV. ) (Note: These bits are connected to AR36U12.PDM_CORE_CFG.MCLKDIV)
bits : 8 - 19 (12 bit)
access : read-write

SINC_RATE : SINC Decimation Rate. For details, see the data sheet provided by Archband. Oversampling Ratio = Decimation Rate = 2 X SINC_RATE (Note: These bits are connected to AR36U12.PDM_CORE_CFG.SINC_RATE)
bits : 16 - 38 (23 bit)
access : read-write

PCM_CH_SET : Specifies PCM output channels as mono or stereo: (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_CHSET)
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWAP_LR : Input data L/R channel swap: '1': Right/Left channel recording swap '0': No Swap (Note: This bit is connected to AR36U12.PDM_CORE_CFG.LRSWAP)
bits : 2 - 4 (3 bit)
access : read-write

S_CYCLES : Set time step for gain change during PGA or soft mute operation in number of 1/a sampling rate. (Note: These bits are connected to AR36U12.PDM_CORE_CFG.S_CYCLES)
bits : 8 - 18 (11 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CKO_DELAY : Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of PDM_CKO clock: (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PDMCKO_DLY)
bits : 16 - 34 (19 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HPF_GAIN : Adjust high pass filter coefficients. H(Z) = (1 - Z-1 ) / [1 - (1- 2 -HPF_GAIN) Z-1 ] (Note: These bits are connected to AR36U12.PDM_CORE_CFG.HPGAIN)
bits : 24 - 51 (28 bit)
access : read-write

HPF_EN_N : Enable high pass filter (active low) '1': Disabled. '0': Enabled. (Note: This bit is connected to AR36U12.PDM_CORE_CFG.ADCHPD)
bits : 28 - 56 (29 bit)
access : read-write

WORD_LEN : PCM Word Length in number of bits: (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_IWL)
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIT_EXTENSION : When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. '0': Extended by '0' '1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0')
bits : 8 - 16 (9 bit)
access : read-write

STREAM_EN : Enable data streaming flow: '0': Disabled. '1': Enabled. (Note: This bit is connected to AR36U12.PDM_CORE_CFG.PDMA_EN)
bits : 0 - 0 (1 bit)
access : read-write

TRIGGER_LEVEL : Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. Note: software can configure up to 254 in Mono channel enabled (MODE_CTL.PCM_CH_SET = '1' or '2'), up to 253 in Stereo channel enabled (MODE_CTL.PCM_CH_SET = '3').
bits : 0 - 7 (8 bit)
access : read-write

CLEAR : When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.
bits : 16 - 32 (17 bit)
access : read-write

FREEZE : When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer.This field is used only for debugging purposes.
bits : 17 - 34 (18 bit)
access : read-write

USED : Number of entries in the RX FIFO. The field value is in the range [0, 255]. When this is zero, the RX FIFO is empty.
bits : 0 - 7 (8 bit)
access : read-only

RD_PTR : RX FIFO read pointer: RX FIFO location from which a data frame is read by the host.This field is used only for debugging purposes.
bits : 16 - 39 (24 bit)
access : read-only

WR_PTR : RX FIFO write pointer: RX FIFO location at which a new data frame is written by the hardware.This field is used only for debugging purposes.
bits : 24 - 55 (32 bit)
access : read-only

DATA : Data read from the RX FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'.
bits : 0 - 31 (32 bit)
access : read-only

DATA : Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes. Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'.
bits : 0 - 31 (32 bit)
access : read-only

RX_REQ_EN : Trigger output ('tr_pdm_rx_req') enable for requests of DMA transfer '0': Disabled. '1': Enabled.
bits : 16 - 32 (17 bit)
access : read-write

RX_TRIGGER : More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL.
bits : 16 - 32 (17 bit)
access : read-write

RX_NOT_EMPTY : RX FIFO is not empty.
bits : 18 - 36 (19 bit)
access : read-write

RX_OVERFLOW : Attempt to write to a full RX FIFO
bits : 21 - 42 (22 bit)
access : read-write

RX_UNDERFLOW : Attempt to read from an empty RX FIFO
bits : 22 - 44 (23 bit)
access : read-write

RX_TRIGGER : Write with '1' to set corresponding bit in interrupt request register.
bits : 16 - 32 (17 bit)
access : read-write

RX_NOT_EMPTY : Write with '1' to set corresponding bit in interrupt request register.
bits : 18 - 36 (19 bit)
access : read-write

RX_OVERFLOW : Write with '1' to set corresponding bit in interrupt request register.
bits : 21 - 42 (22 bit)
access : read-write

RX_UNDERFLOW : Write with '1' to set corresponding bit in interrupt request register.
bits : 22 - 44 (23 bit)
access : read-write

RX_TRIGGER : Mask bit for corresponding bit in interrupt request register.
bits : 16 - 32 (17 bit)
access : read-write

RX_NOT_EMPTY : Mask bit for corresponding bit in interrupt request register.
bits : 18 - 36 (19 bit)
access : read-write

RX_OVERFLOW : Mask bit for corresponding bit in interrupt request register.
bits : 21 - 42 (22 bit)
access : read-write

RX_UNDERFLOW : Mask bit for corresponding bit in interrupt request register.
bits : 22 - 44 (23 bit)
access : read-write

RX_TRIGGER : Logical and of corresponding request and mask bits.
bits : 16 - 32 (17 bit)
access : read-only

RX_NOT_EMPTY : Logical and of corresponding request and mask bits.
bits : 18 - 36 (19 bit)
access : read-only

RX_OVERFLOW : Logical and of corresponding request and mask bits.
bits : 21 - 42 (22 bit)
access : read-only

RX_UNDERFLOW : Logical and of corresponding request and mask bits.
bits : 22 - 44 (23 bit)
access : read-only