\n
address_offset : 0x0 Bytes (0x0)
size : 0x300 byte (0x0)
mem_usage : registers
protection : not protected
Flash Access Protection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0AP : Master 0 Access Protection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M1AP : Master 1 Access Protection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M2AP : Master 2 Access Protection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M3AP : Master 3 Access Protection
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M4AP : Master 4 Access Protection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M5AP : Master 5 Access Protection
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M6AP : Master 6 Access Protection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M7AP : Master 7 Access Protection
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master.
#01 : 01
Only read accesses may be performed by this master.
#10 : 10
Only write accesses may be performed by this master.
#11 : 11
Both read and write accesses may be performed by this master.
End of enumeration elements list.
M0PFD : Master 0 Prefetch Disable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M1PFD : Master 1 Prefetch Disable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M2PFD : Master 2 Prefetch Disable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M3PFD : Master 3 Prefetch Disable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M4PFD : Master 4 Prefetch Disable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M5PFD : Master 5 Prefetch Disable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M6PFD : Master 6 Prefetch Disable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M7PFD : Master 7 Prefetch Disable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
Cache Data Storage (upper word)
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x10A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x10E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x11F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x1214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x12A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x12C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x1304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x13B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x13D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x14A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x14C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x1520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x1544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x16A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x16C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x1760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x1784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x19A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x19C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Flash Bank 0 Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B0SEBE : Bank 0 Single Entry Buffer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single entry buffer is disabled.
#1 : 1
Single entry buffer is enabled.
End of enumeration elements list.
B0IPE : Bank 0 Instruction Prefetch Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to instruction fetches.
#1 : 1
Enable prefetches in response to instruction fetches.
End of enumeration elements list.
B0DPE : Bank 0 Data Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to data references.
#1 : 1
Enable prefetches in response to data references.
End of enumeration elements list.
B0ICE : Bank 0 Instruction Cache Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not cache instruction fetches.
#1 : 1
Cache instruction fetches.
End of enumeration elements list.
B0DCE : Bank 0 Data Cache Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not cache data references.
#1 : 1
Cache data references.
End of enumeration elements list.
CRC : Cache Replacement Control
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 000
LRU replacement algorithm per set across all four ways
#010 : 010
Independent LRU with ways [0-1] for ifetches, [2-3] for data
#011 : 011
Independent LRU with ways [0-2] for ifetches, [3] for data
End of enumeration elements list.
B0MW : Bank 0 Memory Width
bits : 17 - 18 (2 bit)
access : read-only
Enumeration:
#00 : 00
32 bits
#01 : 01
64 bits
End of enumeration elements list.
S_B_INV : Invalidate Prefetch Speculation Buffer
bits : 19 - 19 (1 bit)
access : write-only
Enumeration:
#0 : 0
Speculation buffer and single entry buffer are not affected.
#1 : 1
Invalidate (clear) speculation buffer and single entry buffer.
End of enumeration elements list.
CINV_WAY : Cache Invalidate Way x
bits : 20 - 23 (4 bit)
access : write-only
Enumeration:
#0000 : 0
No cache way invalidation for the corresponding cache
#0001 : 1
Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
End of enumeration elements list.
CLCK_WAY : Cache Lock Way x
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Cache way is unlocked and may be displaced
#0001 : 1
Cache way is locked and its contents are not displaced
End of enumeration elements list.
B0RWSC : Bank 0 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only
Cache Data Storage (upper word)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x6C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x6D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x6F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Flash Bank 1 Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B1SEBE : Bank 1 Single Entry Buffer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single entry buffer is disabled.
#1 : 1
Single entry buffer is enabled.
End of enumeration elements list.
B1IPE : Bank 1 Instruction Prefetch Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to instruction fetches.
#1 : 1
Enable prefetches in response to instruction fetches.
End of enumeration elements list.
B1DPE : Bank 1 Data Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to data references.
#1 : 1
Enable prefetches in response to data references.
End of enumeration elements list.
B1ICE : Bank 1 Instruction Cache Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not cache instruction fetches.
#1 : 1
Cache instruction fetches.
End of enumeration elements list.
B1DCE : Bank 1 Data Cache Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not cache data references.
#1 : 1
Cache data references.
End of enumeration elements list.
B1MW : Bank 1 Memory Width
bits : 17 - 18 (2 bit)
access : read-only
Enumeration:
#00 : 00
32 bits
#01 : 01
64 bits
End of enumeration elements list.
B1RWSC : Bank 1 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only
Cache Data Storage (upper word)
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0x9DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0xA28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0xA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0xA44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0xA54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Tag Storage
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0xB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0xB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0xB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0xBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0xC50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0xC68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0xCB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0xCC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0xCD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0xDD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0xDE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0xDF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0xE04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0xE78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0xE94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0xF50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0xF68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.