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FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x300 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PFAPR

DATAW1S5U

DATAW1S5L

DATAW0S6U

DATAW0S6L

DATAW3S4U

DATAW3S4L

DATAW2S5U

DATAW2S5L

DATAW1S6U

DATAW1S6L

DATAW0S7U

DATAW0S7L

DATAW3S5U

DATAW3S5L

DATAW2S6U

DATAW2S6L

DATAW1S7U

DATAW1S7L

DATAW3S6U

DATAW3S6L

DATAW2S7U

DATAW2S7L

DATAW3S7U

DATAW3S7L

TAGVDW0S0

TAGVDW1S0

TAGVDW2S0

TAGVDW3S0

TAGVDW0S1

TAGVDW1S1

TAGVDW2S1

PFB0CR

DATAW0S0U

DATAW0S0L

TAGVDW0S2

TAGVDW3S1

DATAW1S0U

DATAW1S0L

TAGVDW1S2

DATAW2S0U

DATAW2S0L

TAGVDW2S2

TAGVDW0S3

DATAW3S0U

DATAW3S0L

TAGVDW3S2

TAGVDW1S3

DATAW0S1U

DATAW0S1L

TAGVDW0S4

TAGVDW2S3

DATAW1S1U

DATAW1S1L

TAGVDW1S4

TAGVDW3S3

TAGVDW0S5

DATAW2S1U

DATAW2S1L

TAGVDW2S4

PFB1CR

DATAW0S2U

TAGVDW1S5

DATAW0S2L

DATAW3S1U

TAGVDW0S6

DATAW3S1L

TAGVDW3S4

TAGVDW2S5

DATAW1S2U

DATAW1S2L

TAGVDW1S6

TAGVDW0S7

TAGVDW3S5

DATAW2S2U

DATAW2S2L

DATAW0S3U

DATAW0S3L

TAGVDW2S6

TAGVDW1S7

DATAW3S2U

DATAW3S2L

TAGVDW3S6

DATAW1S3U

DATAW1S3L

TAGVDW2S7

DATAW0S4U

DATAW0S4L

DATAW2S3U

DATAW2S3L

TAGVDW3S7

DATAW1S4U

DATAW1S4L

DATAW3S3U

DATAW3S3L

DATAW0S5U

DATAW0S5L

DATAW2S4U

DATAW2S4L


PFAPR

Flash Access Protection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFAPR PFAPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0AP M1AP M2AP M3AP M4AP M5AP M6AP M7AP M0PFD M1PFD M2PFD M3PFD M4PFD M5PFD M6PFD M7PFD

M0AP : Master 0 Access Protection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M1AP : Master 1 Access Protection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M2AP : Master 2 Access Protection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M3AP : Master 3 Access Protection
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M4AP : Master 4 Access Protection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M5AP : Master 5 Access Protection
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M6AP : Master 6 Access Protection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M7AP : Master 7 Access Protection
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master.

#01 : 01

Only read accesses may be performed by this master.

#10 : 10

Only write accesses may be performed by this master.

#11 : 11

Both read and write accesses may be performed by this master.

End of enumeration elements list.

M0PFD : Master 0 Prefetch Disable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M1PFD : Master 1 Prefetch Disable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M2PFD : Master 2 Prefetch Disable
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M3PFD : Master 3 Prefetch Disable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M4PFD : Master 4 Prefetch Disable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M5PFD : Master 5 Prefetch Disable
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M6PFD : Master 6 Prefetch Disable
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M7PFD : Master 7 Prefetch Disable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.


DATAW1S5U

Cache Data Storage (upper word)
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S5U DATAW1S5U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S5L

Cache Data Storage (lower word)
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S5L DATAW1S5L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S6U

Cache Data Storage (upper word)
address_offset : 0x10A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S6U DATAW0S6U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S6L

Cache Data Storage (lower word)
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S6L DATAW0S6L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S4U

Cache Data Storage (upper word)
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S4U DATAW3S4U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S4L

Cache Data Storage (lower word)
address_offset : 0x10E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S4L DATAW3S4L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S5U

Cache Data Storage (upper word)
address_offset : 0x11F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S5U DATAW2S5U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S5L

Cache Data Storage (lower word)
address_offset : 0x1214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S5L DATAW2S5L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S6U

Cache Data Storage (upper word)
address_offset : 0x12A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S6U DATAW1S6U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S6L

Cache Data Storage (lower word)
address_offset : 0x12C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S6L DATAW1S6L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S7U

Cache Data Storage (upper word)
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S7U DATAW0S7U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S7L

Cache Data Storage (lower word)
address_offset : 0x1304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S7L DATAW0S7L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S5U

Cache Data Storage (upper word)
address_offset : 0x13B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S5U DATAW3S5U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S5L

Cache Data Storage (lower word)
address_offset : 0x13D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S5L DATAW3S5L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S6U

Cache Data Storage (upper word)
address_offset : 0x14A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S6U DATAW2S6U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S6L

Cache Data Storage (lower word)
address_offset : 0x14C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S6L DATAW2S6L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S7U

Cache Data Storage (upper word)
address_offset : 0x1520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S7U DATAW1S7U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S7L

Cache Data Storage (lower word)
address_offset : 0x1544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S7L DATAW1S7L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S6U

Cache Data Storage (upper word)
address_offset : 0x16A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S6U DATAW3S6U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S6L

Cache Data Storage (lower word)
address_offset : 0x16C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S6L DATAW3S6L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S7U

Cache Data Storage (upper word)
address_offset : 0x1760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S7U DATAW2S7U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S7L

Cache Data Storage (lower word)
address_offset : 0x1784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S7L DATAW2S7L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S7U

Cache Data Storage (upper word)
address_offset : 0x19A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S7U DATAW3S7U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S7L

Cache Data Storage (lower word)
address_offset : 0x19C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S7L DATAW3S7L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW0S0

Cache Tag Storage
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S0 TAGVDW0S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW1S0

Cache Tag Storage
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S0 TAGVDW1S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW2S0

Cache Tag Storage
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S0 TAGVDW2S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW3S0

Cache Tag Storage
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S0 TAGVDW3S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW0S1

Cache Tag Storage
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S1 TAGVDW0S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW1S1

Cache Tag Storage
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S1 TAGVDW1S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW2S1

Cache Tag Storage
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S1 TAGVDW2S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


PFB0CR

Flash Bank 0 Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFB0CR PFB0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0SEBE B0IPE B0DPE B0ICE B0DCE CRC B0MW S_B_INV CINV_WAY CLCK_WAY B0RWSC

B0SEBE : Bank 0 Single Entry Buffer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Single entry buffer is disabled.

#1 : 1

Single entry buffer is enabled.

End of enumeration elements list.

B0IPE : Bank 0 Instruction Prefetch Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not prefetch in response to instruction fetches.

#1 : 1

Enable prefetches in response to instruction fetches.

End of enumeration elements list.

B0DPE : Bank 0 Data Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not prefetch in response to data references.

#1 : 1

Enable prefetches in response to data references.

End of enumeration elements list.

B0ICE : Bank 0 Instruction Cache Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not cache instruction fetches.

#1 : 1

Cache instruction fetches.

End of enumeration elements list.

B0DCE : Bank 0 Data Cache Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not cache data references.

#1 : 1

Cache data references.

End of enumeration elements list.

CRC : Cache Replacement Control
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

#000 : 000

LRU replacement algorithm per set across all four ways

#010 : 010

Independent LRU with ways [0-1] for ifetches, [2-3] for data

#011 : 011

Independent LRU with ways [0-2] for ifetches, [3] for data

End of enumeration elements list.

B0MW : Bank 0 Memory Width
bits : 17 - 18 (2 bit)
access : read-only

Enumeration:

#00 : 00

32 bits

#01 : 01

64 bits

End of enumeration elements list.

S_B_INV : Invalidate Prefetch Speculation Buffer
bits : 19 - 19 (1 bit)
access : write-only

Enumeration:

#0 : 0

Speculation buffer and single entry buffer are not affected.

#1 : 1

Invalidate (clear) speculation buffer and single entry buffer.

End of enumeration elements list.

CINV_WAY : Cache Invalidate Way x
bits : 20 - 23 (4 bit)
access : write-only

Enumeration:

#0000 : 0

No cache way invalidation for the corresponding cache

#0001 : 1

Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected

End of enumeration elements list.

CLCK_WAY : Cache Lock Way x
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Cache way is unlocked and may be displaced

#0001 : 1

Cache way is locked and its contents are not displaced

End of enumeration elements list.

B0RWSC : Bank 0 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only


DATAW0S0U

Cache Data Storage (upper word)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S0U DATAW0S0U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S0L

Cache Data Storage (lower word)
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S0L DATAW0S0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW0S2

Cache Tag Storage
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S2 TAGVDW0S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW3S1

Cache Tag Storage
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S1 TAGVDW3S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW1S0U

Cache Data Storage (upper word)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S0U DATAW1S0U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S0L

Cache Data Storage (lower word)
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S0L DATAW1S0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW1S2

Cache Tag Storage
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S2 TAGVDW1S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW2S0U

Cache Data Storage (upper word)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S0U DATAW2S0U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S0L

Cache Data Storage (lower word)
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S0L DATAW2S0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW2S2

Cache Tag Storage
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S2 TAGVDW2S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW0S3

Cache Tag Storage
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S3 TAGVDW0S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW3S0U

Cache Data Storage (upper word)
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S0U DATAW3S0U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S0L

Cache Data Storage (lower word)
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S0L DATAW3S0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW3S2

Cache Tag Storage
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S2 TAGVDW3S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW1S3

Cache Tag Storage
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S3 TAGVDW1S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW0S1U

Cache Data Storage (upper word)
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S1U DATAW0S1U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S1L

Cache Data Storage (lower word)
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S1L DATAW0S1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW0S4

Cache Tag Storage
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S4 TAGVDW0S4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW2S3

Cache Tag Storage
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S3 TAGVDW2S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW1S1U

Cache Data Storage (upper word)
address_offset : 0x6C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S1U DATAW1S1U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S1L

Cache Data Storage (lower word)
address_offset : 0x6D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S1L DATAW1S1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW1S4

Cache Tag Storage
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S4 TAGVDW1S4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW3S3

Cache Tag Storage
address_offset : 0x6F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S3 TAGVDW3S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW0S5

Cache Tag Storage
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S5 TAGVDW0S5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW2S1U

Cache Data Storage (upper word)
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S1U DATAW2S1U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S1L

Cache Data Storage (lower word)
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S1L DATAW2S1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW2S4

Cache Tag Storage
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S4 TAGVDW2S4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


PFB1CR

Flash Bank 1 Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFB1CR PFB1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B1SEBE B1IPE B1DPE B1ICE B1DCE B1MW B1RWSC

B1SEBE : Bank 1 Single Entry Buffer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Single entry buffer is disabled.

#1 : 1

Single entry buffer is enabled.

End of enumeration elements list.

B1IPE : Bank 1 Instruction Prefetch Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not prefetch in response to instruction fetches.

#1 : 1

Enable prefetches in response to instruction fetches.

End of enumeration elements list.

B1DPE : Bank 1 Data Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not prefetch in response to data references.

#1 : 1

Enable prefetches in response to data references.

End of enumeration elements list.

B1ICE : Bank 1 Instruction Cache Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not cache instruction fetches.

#1 : 1

Cache instruction fetches.

End of enumeration elements list.

B1DCE : Bank 1 Data Cache Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not cache data references.

#1 : 1

Cache data references.

End of enumeration elements list.

B1MW : Bank 1 Memory Width
bits : 17 - 18 (2 bit)
access : read-only

Enumeration:

#00 : 00

32 bits

#01 : 01

64 bits

End of enumeration elements list.

B1RWSC : Bank 1 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only


DATAW0S2U

Cache Data Storage (upper word)
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S2U DATAW0S2U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW1S5

Cache Tag Storage
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S5 TAGVDW1S5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW0S2L

Cache Data Storage (lower word)
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S2L DATAW0S2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S1U

Cache Data Storage (upper word)
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S1U DATAW3S1U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW0S6

Cache Tag Storage
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S6 TAGVDW0S6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW3S1L

Cache Data Storage (lower word)
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S1L DATAW3S1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW3S4

Cache Tag Storage
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S4 TAGVDW3S4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW2S5

Cache Tag Storage
address_offset : 0x8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S5 TAGVDW2S5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW1S2U

Cache Data Storage (upper word)
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S2U DATAW1S2U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S2L

Cache Data Storage (lower word)
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S2L DATAW1S2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW1S6

Cache Tag Storage
address_offset : 0x954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S6 TAGVDW1S6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW0S7

Cache Tag Storage
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S7 TAGVDW0S7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW3S5

Cache Tag Storage
address_offset : 0x9DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S5 TAGVDW3S5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW2S2U

Cache Data Storage (upper word)
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S2U DATAW2S2U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S2L

Cache Data Storage (lower word)
address_offset : 0xA28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S2L DATAW2S2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S3U

Cache Data Storage (upper word)
address_offset : 0xA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S3U DATAW0S3U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S3L

Cache Data Storage (lower word)
address_offset : 0xA44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S3L DATAW0S3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW2S6

Cache Tag Storage
address_offset : 0xA54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S6 TAGVDW2S6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW1S7

Cache Tag Storage
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S7 TAGVDW1S7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW3S2U

Cache Data Storage (upper word)
address_offset : 0xB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S2U DATAW3S2U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S2L

Cache Data Storage (lower word)
address_offset : 0xB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S2L DATAW3S2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW3S6

Cache Tag Storage
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S6 TAGVDW3S6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW1S3U

Cache Data Storage (upper word)
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S3U DATAW1S3U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S3L

Cache Data Storage (lower word)
address_offset : 0xB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S3L DATAW1S3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW2S7

Cache Tag Storage
address_offset : 0xBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S7 TAGVDW2S7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW0S4U

Cache Data Storage (upper word)
address_offset : 0xC50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S4U DATAW0S4U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S4L

Cache Data Storage (lower word)
address_offset : 0xC68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S4L DATAW0S4L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S3U

Cache Data Storage (upper word)
address_offset : 0xCB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S3U DATAW2S3U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S3L

Cache Data Storage (lower word)
address_offset : 0xCC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S3L DATAW2S3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW3S7

Cache Tag Storage
address_offset : 0xCD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S7 TAGVDW3S7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW1S4U

Cache Data Storage (upper word)
address_offset : 0xDD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S4U DATAW1S4U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S4L

Cache Data Storage (lower word)
address_offset : 0xDE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S4L DATAW1S4L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S3U

Cache Data Storage (upper word)
address_offset : 0xDF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S3U DATAW3S3U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S3L

Cache Data Storage (lower word)
address_offset : 0xE04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S3L DATAW3S3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S5U

Cache Data Storage (upper word)
address_offset : 0xE78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S5U DATAW0S5U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S5L

Cache Data Storage (lower word)
address_offset : 0xE94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S5L DATAW0S5L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S4U

Cache Data Storage (upper word)
address_offset : 0xF50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S4U DATAW2S4U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S4L

Cache Data Storage (lower word)
address_offset : 0xF68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S4L DATAW2S4L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write



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