Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1064 byte (0x0)
mem_usage : registers
protection : not protected
System Options Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMSIZE : RAM size
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
Undefined
#0001 : 0001
8 KBytes
#0010 : 0010
Undefined
#0011 : 0011
16 KBytes
#0100 : 0100
Undefined
#0101 : 0101
32 KBytes
#0110 : 0110
Undefined
#0111 : 0111
64 KBytes
#1000 : 1000
Undefined
#1001 : 1001
128 KBytes
#1010 : 1010
Undefined
#1011 : 1011
Undefined
#1100 : 1100
Undefined
#1101 : 1101
Undefined
#1110 : 1110
Undefined
#1111 : 1111
Undefined
End of enumeration elements list.
OSC32KSEL : 32K oscillator clock select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
System oscillator (OSC32KCLK)
#10 : 10
RTC 32.768kHz oscillator
#11 : 11
LPO 1 kHz
End of enumeration elements list.
System Options Register 2
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCCLKOUTSEL : RTC clock out select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC 1 Hz clock is output on the RTC_CLKOUT pin.
#1 : 1
RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
End of enumeration elements list.
CLKOUTSEL : CLKOUT select
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 000
FlexBus CLKOUT
#010 : 010
Flash clock
#011 : 011
LPO clock (1 kHz)
#100 : 100
MCGIRCLK
#101 : 101
RTC 32.768kHz clock
#110 : 110
OSCERCLK0
End of enumeration elements list.
FBSL : FlexBus security level
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
All off-chip accesses (instruction and data) via the FlexBus are disallowed.
#01 : 01
All off-chip accesses (instruction and data) via the FlexBus are disallowed.
#10 : 10
Off-chip instruction accesses are disallowed. Data accesses are allowed.
#11 : 11
Off-chip instruction accesses and data accesses are allowed.
End of enumeration elements list.
PTD7PAD : PTD7 pad drive strength
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single-pad drive strength for PTD7.
#1 : 1
Double pad drive strength for PTD7.
End of enumeration elements list.
TRACECLKSEL : Debug trace clock select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCGOUTCLK
#1 : 1
Core/system clock
End of enumeration elements list.
PLLFLLSEL : PLL/FLL clock select
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCGFLLCLK clock
#1 : 1
MCGPLLCLK clock
End of enumeration elements list.
SDHCSRC : SDHC clock source select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
Core/system clock.
#01 : 01
MCGPLLCLK/MCGFLLCLK clock
#10 : 10
OSCERCLK clock
#11 : 11
External bypass clock (SDHC0_CLKIN)
End of enumeration elements list.
System Options Register 4
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTM0FLT0 : FTM0 Fault 0 Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_FLT0 pin
#1 : 1
CMP0 out
End of enumeration elements list.
FTM0FLT1 : FTM0 Fault 1 Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_FLT1 pin
#1 : 1
CMP1 out
End of enumeration elements list.
FTM0FLT2 : FTM0 Fault 2 Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_FLT2 pin
#1 : 1
CMP2 out
End of enumeration elements list.
FTM1FLT0 : FTM1 Fault 0 Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM1_FLT0 pin
#1 : 1
CMP0 out
End of enumeration elements list.
FTM2FLT0 : FTM2 Fault 0 Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2_FLT0 pin
#1 : 1
CMP0 out
End of enumeration elements list.
FTM1CH0SRC : FTM1 channel 0 input capture source select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
FTM1_CH0 signal
#01 : 01
CMP0 output
#10 : 10
CMP1 output
End of enumeration elements list.
FTM2CH0SRC : FTM2 channel 0 input capture source select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
FTM2_CH0 signal
#01 : 01
CMP0 output
#10 : 10
CMP1 output
End of enumeration elements list.
FTM0CLKSEL : FlexTimer 0 External Clock Pin Select
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM_CLK0 pin
#1 : 1
FTM_CLK1 pin
End of enumeration elements list.
FTM1CLKSEL : FTM1 External Clock Pin Select
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM_CLK0 pin
#1 : 1
FTM_CLK1 pin
End of enumeration elements list.
FTM2CLKSEL : FlexTimer 2 External Clock Pin Select
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2 external clock driven by FTM_CLK0 pin.
#1 : 1
FTM2 external clock driven by FTM_CLK1 pin.
End of enumeration elements list.
FTM0TRG0SRC : FlexTimer 0 Hardware Trigger 0 Source Select
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
HSCMP0 output drives FTM0 hardware trigger 0
#1 : 1
FTM1 channel match drives FTM0 hardware trigger 0
End of enumeration elements list.
FTM0TRG1SRC : FlexTimer 0 Hardware Trigger 1 Source Select
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB output trigger 1 drives FTM0 hardware trigger 1
#1 : 1
FTM2 channel match drives FTM0 hardware trigger 1
End of enumeration elements list.
System Options Register 5
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART0TXSRC : UART 0 transmit data source select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
UART0_TX pin
#01 : 01
UART0_TX pin modulated with FTM1 channel 0 output
#10 : 10
UART0_TX pin modulated with FTM2 channel 0 output
End of enumeration elements list.
UART0RXSRC : UART 0 receive data source select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
UART0_RX pin
#01 : 01
CMP0
#10 : 10
CMP1
End of enumeration elements list.
UART1TXSRC : UART 1 transmit data source select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
UART1_TX pin
#01 : 01
UART1_TX pin modulated with FTM1 channel 0 output
#10 : 10
UART1_TX pin modulated with FTM2 channel 0 output
End of enumeration elements list.
UART1RXSRC : UART 1 receive data source select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
UART1_RX pin
#01 : 01
CMP0
#10 : 10
CMP1
End of enumeration elements list.
System Options Register 7
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0TRGSEL : ADC0 trigger select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
PDB external trigger pin input (PDB0_EXTRG)
#0001 : 0001
High speed comparator 0 output
#0010 : 0010
High speed comparator 1 output
#0011 : 0011
High speed comparator 2 output
#0100 : 0100
PIT trigger 0
#0101 : 0101
PIT trigger 1
#0110 : 0110
PIT trigger 2
#0111 : 0111
PIT trigger 3
#1000 : 1000
FTM0 trigger
#1001 : 1001
FTM1 trigger
#1010 : 1010
FTM2 trigger
#1011 : 1011
Unused
#1100 : 1100
RTC alarm
#1101 : 1101
RTC seconds
#1110 : 1110
Low-power timer trigger
#1111 : 1111
Unused
End of enumeration elements list.
ADC0PRETRGSEL : ADC0 pretrigger select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pre-trigger A
#1 : 1
Pre-trigger B
End of enumeration elements list.
ADC0ALTTRGEN : ADC0 alternate trigger enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB trigger selected for ADC0.
#1 : 1
Alternate trigger selected for ADC0.
End of enumeration elements list.
ADC1TRGSEL : ADC1 trigger select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
PDB external trigger pin input (PDB0_EXTRG)
#0001 : 0001
High speed comparator 0 output
#0010 : 0010
High speed comparator 1 output
#0011 : 0011
High speed comparator 2 output
#0100 : 0100
PIT trigger 0
#0101 : 0101
PIT trigger 1
#0110 : 0110
PIT trigger 2
#0111 : 0111
PIT trigger 3
#1000 : 1000
FTM0 trigger
#1001 : 1001
FTM1 trigger
#1010 : 1010
FTM2 trigger
#1011 : 1011
Unused
#1100 : 1100
RTC alarm
#1101 : 1101
RTC seconds
#1110 : 1110
Low-power timer trigger
#1111 : 1111
Unused
End of enumeration elements list.
ADC1PRETRGSEL : ADC1 pre-trigger select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pre-trigger A selected for ADC1.
#1 : 1
Pre-trigger B selected for ADC1.
End of enumeration elements list.
ADC1ALTTRGEN : ADC1 alternate trigger enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB trigger selected for ADC1
#1 : 1
Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
End of enumeration elements list.
System Device Identification Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PINID : Pincount identification
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
#0110 : 0110
80-pin
#0111 : 0111
81-pin
#1000 : 1000
100-pin
#1001 : 1001
121-pin
#1010 : 1010
144-pin
End of enumeration elements list.
FAMID : Kinetis family identification
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
#000 : 000
K10
#001 : 001
K20
#010 : 010
K30
#011 : 011
K40
#100 : 100
K60
#110 : 110
K50 and K52
#111 : 111
K51 and K53
End of enumeration elements list.
REVID : Device revision number
bits : 12 - 15 (4 bit)
access : read-only
System Clock Gating Control Register 1
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART4 : UART4 Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART5 : UART5 Clock Gate Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 2
address_offset : 0x102C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAC0 : DAC0 Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DAC1 : DAC1 Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 3
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLEXCAN1 : FlexCAN1 Clock Gate Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI2 : SPI2 Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SDHC : SDHC Clock Gate Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
FTM2 : FTM2 Clock Gate Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
ADC1 : ADC1 Clock Gate Control
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 4
address_offset : 0x1034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EWM : EWM Clock Gate Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CMT : CMT Clock Gate Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2C0 : I2C0 Clock Gate Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2C1 : I2C1 Clock Gate Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART0 : UART0 Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART1 : UART1 Clock Gate Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART2 : UART2 Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART3 : UART3 Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CMP : Comparator Clock Gate Control
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
VREF : VREF Clock Gate Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
LLWU : LLWU Clock Gate Control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Access disabled
#1 : 1
Access enabled
End of enumeration elements list.
System Clock Gating Control Register 5
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIMER : Low Power Timer Access Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Access disabled
#1 : 1
Access enabled
End of enumeration elements list.
TSI : TSI Clock Gate Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTA : Port A Clock Gate Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTB : Port B Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTC : Port C Clock Gate Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTD : Port D Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTE : Port E Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 6
address_offset : 0x103C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTFL : Flash Memory Clock Gate Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMAMUX : DMA Mux Clock Gate Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
FLEXCAN0 : FlexCAN0 Clock Gate Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI0 : SPI0 Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI1 : SPI1 Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2S : I2S Clock Gate Control
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CRC : CRC Clock Gate Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PDB : PDB Clock Gate Control
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PIT : PIT Clock Gate Control
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
FTM0 : FTM0 Clock Gate Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
FTM1 : FTM1 Clock Gate Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
ADC0 : ADC0 Clock Gate Control
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
RTC : RTC Access Control
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Access and interrupts disabled
#1 : 1
Access and interrupts enabled
End of enumeration elements list.
System Clock Gating Control Register 7
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLEXBUS : FlexBus Clock Gate Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMA : DMA Clock Gate Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
MPU : MPU Clock Gate Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Divider Register 1
address_offset : 0x1044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTDIV4 : Clock 4 output divider value
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
OUTDIV3 : Clock 3 output divider value
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
OUTDIV2 : Clock 2 output divider value
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
OUTDIV1 : Clock 1 output divider value
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
System Clock Divider Register 2
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Flash Configuration Register 1
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASHDIS : Flash Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash is enabled
#1 : 1
Flash is disabled
End of enumeration elements list.
FLASHDOZE : Flash Doze
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash remains enabled during Wait mode
#1 : 1
Flash is disabled for the duration of Wait mode
End of enumeration elements list.
DEPART : FlexNVM partition
bits : 8 - 11 (4 bit)
access : read-only
EESIZE : EEPROM size
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
#0010 : 0010
4 KB
#0100 : 0100
1 KB
#0101 : 0101
512 Bytes
#0110 : 0110
256 Bytes
#0111 : 0111
128 Bytes
#1000 : 1000
64 Bytes
#1001 : 1001
32 Bytes
#1111 : 1111
0 Bytes
End of enumeration elements list.
PFSIZE : Program flash size
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0111 : 0111
128 KB of program flash, 4 KB protection region
#1001 : 1001
256 KB of program flash, 8 KB protection region
#1011 : 1011
512 KB of program flash, 16 KB protection region
End of enumeration elements list.
NVMSIZE : FlexNVM size
bits : 28 - 31 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
0 KB of FlexNVM
#0111 : 0111
128 KB of FlexNVM, 32 KB protection region
#1001 : 1001
256 KB of FlexNVM, 32 KB protection region
End of enumeration elements list.
Flash Configuration Register 2
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAXADDR1 : Max address block 1
bits : 16 - 22 (7 bit)
access : read-only
PFLSH : Program flash
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
Physical flash block 1 is used as FlexNVM. Reserved for devices without FlexNVM.
#1 : 1
Physical flash block 1 is used as program flash
End of enumeration elements list.
MAXADDR0 : Max address block 0
bits : 24 - 30 (7 bit)
access : read-only
SWAPPFLSH : Swap program flash
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Swap is not active.
#1 : 1
Swap is active.
End of enumeration elements list.
Unique Identification Register High
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Mid-High
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Mid Low
address_offset : 0x105C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Low
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
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