Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection : not protected
I2S Transmit Data Registers 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX0 : I2S transmit data
bits : 0 - 31 (32 bit)
access : read-write
I2S Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2SEN : I2S Enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S is disabled.
#1 : 1
I2S is enabled.
End of enumeration elements list.
TE : Transmit Enable.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit section disabled.
#1 : 1
Transmit section enabled.
End of enumeration elements list.
RE : Receive Enable.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive section disabled.
#1 : 1
Receive section enabled.
End of enumeration elements list.
NET : Network Mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Network mode not selected.
#1 : 1
Network mode selected.
End of enumeration elements list.
SYN : Synchronous Mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Asynchronous mode selected.
#1 : 1
Synchronous mode selected.
End of enumeration elements list.
I2SMODE : I2S Mode Select
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 00
Normal mode
#01 : 01
I2S master mode
#10 : 10
I2S slave mode
#11 : 11
Normal mode
End of enumeration elements list.
SYSCLKEN : System Clock (Oversampling Clock) Enable.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Network clock not output on SRCK port.
#1 : 1
Network clock output on SRCK port.
End of enumeration elements list.
TCHEN : Two-Channel Operation Enable.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Two-channel mode disabled.
#1 : 1
Two-channel mode enabled.
End of enumeration elements list.
CLKIST : Clock Idle State.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock idle state is `0'.
#1 : 1
Clock idle state is `1'.
End of enumeration elements list.
TFRCLKDIS : Transmit Frame Clock Disable.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Continue frame-sync/clock generation after current frame during which CR[TE] is cleared. This may be required when frame-sync and clocks are required from I2S, even when no data is to be received.
#1 : 1
Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where transmitter is already disabled in current or previous frames.
End of enumeration elements list.
RFRCLKDIS : Receive Frame Clock Disable.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Continue frame-sync/clock generation after current frame during which CR[RE] is cleared. This may be required when Frame-sync and Clocks are required from I2S, even when no data is to be received.
#1 : 1
Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where receiver is already disabled in current or previous frames.
End of enumeration elements list.
SYNCTXFS : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
CR[TE] not latched with FS occurrence and used directly for transmitter enable/disable.
#1 : 1
CR[TE] latched with FS occurrence and latched-TE used for transmitter enable/disable.
End of enumeration elements list.
I2S Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFE0 : Transmit FIFO Empty 0.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO0 has data for transmission.
#1 : 1
Transmit FIFO0 is empty.
End of enumeration elements list.
TFE1 : Transmit FIFO Empty 1.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO1 has data for transmission.
#1 : 1
Transmit FIFO1 is empty.
End of enumeration elements list.
RFF0 : Receive FIFO Full 0.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Space available in receive FIFO0.
#1 : 1
Receive FIFO0 is full.
End of enumeration elements list.
RFF1 : Receive FIFO Full 1.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Space available in receive FIFO1.
#1 : 1
Receive FIFO1 is full.
End of enumeration elements list.
RLS : Receive Last Time Slot.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Current time slot is not last time slot of frame.
#1 : 1
Current time slot is the last receive time slot of frame.
End of enumeration elements list.
TLS : Transmit Last Time Slot.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Current time slot is not last time slot of frame.
#1 : 1
Current time slot is the last transmit time slot of frame.
End of enumeration elements list.
RFS : Receive Frame Sync.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
No occurrence of receive frame sync.
#1 : 1
Receive frame sync occurred during reception of next word in RX registers.
End of enumeration elements list.
TFS : Transmit Frame Sync.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No occurrence of transmit frame sync.
#1 : 1
Transmit frame sync occurred during transmission of last word written to TX registers.
End of enumeration elements list.
TUE0 : Transmitter Underrun Error 1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No underrun detected
#1 : 1
Transmitter underrun error occurred
End of enumeration elements list.
TUE1 : Transmitter Underrun Error 1.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No underrun detected
#1 : 1
Transmitter underrun error occurred
End of enumeration elements list.
ROE0 : Receiver Overrun Error 0.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overrun detected
#1 : 1
Receiver overrun error occurred
End of enumeration elements list.
ROE1 : Receiver Overrun Error 1.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overrun detected
#1 : 1
Receiver overrun error occurred
End of enumeration elements list.
TDE0 : Transmit Data Register Empty 0.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data available for transmission.
#1 : 1
Data needs to be written by the core for transmission.
End of enumeration elements list.
TDE1 : Transmit Data Register Empty 1.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data available for transmission.
#1 : 1
Data needs to be written by the core for transmission.
End of enumeration elements list.
RDR0 : Receive Data Ready 0.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
No new data for core to read.
#1 : 1
New data for core to read.
End of enumeration elements list.
RDR1 : Receive Data Ready 1.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
No new data for core to read.
#1 : 1
New data for core to read.
End of enumeration elements list.
RXT : Receive Tag Updated.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
No change in ATAG register.
#1 : 1
ATAG register updated with different value.
End of enumeration elements list.
CMDDU : Command Data Register Updated.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
No change in ACDAT register.
#1 : 1
ACDAT register updated with different value.
End of enumeration elements list.
CMDAU : Command Address Register Updated.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
No change in ACADD register.
#1 : 1
ACADD register updated with different value.
End of enumeration elements list.
TRFC : Transmit Frame Complete.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
End of frame not reached.
#1 : 1
End of frame reached after disabling CR[TE] or disabling CR[TFRCLKDIS], when transmitter is already disabled.
End of enumeration elements list.
RFRC : Receive Frame Complete.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
End of frame not reached.
#1 : 1
End of frame reached after disabling CR[RE] or disabling CR[RFRCLKDIS], when receiver is already disabled.
End of enumeration elements list.
I2S Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFE0EN : Enable Bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TFE1EN : Enable Bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFF0EN : Enable Bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFF1EN : Enable Bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RLSEN : Enable Bit.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TLSEN : Enable Bit.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFSEN : Enable Bit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TFSEN : Enable Bit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TUE0EN : Enable Bit.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TUE1EN : Enable Bit.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
ROE0EN : Enable Bit.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
ROE1EN : Enable Bit.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TDE0EN : Enable Bit.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TDE1EN : Enable Bit.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RDR0EN : Enable Bit.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RDR1EN : Enable Bit.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RXTEN : Enable Bit.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
CMDDUEN : Enable Bit.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
CMDAUEN : Enable Bit.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TIE : Transmit Interrupt Enable.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S transmitter interrupt requests disabled.
#1 : 1
I2S transmitter interrupt requests enabled.
End of enumeration elements list.
TDMAE : Transmit DMA Enable.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S transmitter DMA requests disabled.
#1 : 1
I2S transmitter DMA requests enabled.
End of enumeration elements list.
RIE : Receive Interrupt Enable.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S receiver interrupt requests disabled.
#1 : 1
I2S receiver interrupt requests enabled.
End of enumeration elements list.
RDMAE : Receive DMA Enable.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S receiver DMA requests disabled.
#1 : 1
I2S receiver DMA requests enabled.
End of enumeration elements list.
TFRC_EN : Enable Bit.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFRC_EN : Enable Bit.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
I2S Transmit Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEFS : Transmit Early Frame Sync.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit frame sync initiated as the first bit of data is transmitted.
#1 : 1
Transmit frame sync is initiated one bit before the data is transmitted.
End of enumeration elements list.
TFSL : Transmit Frame Sync Length.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit frame sync is one-word long.
#1 : 1
Transmit frame sync is one-clock-bit long.
End of enumeration elements list.
TFSI : Transmit Frame Sync Invert.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit frame sync is active high.
#1 : 1
Transmit frame sync is active low.
End of enumeration elements list.
TSCKP : Transmit Clock Polarity.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data clocked out on rising edge of bit clock.
#1 : 1
Data clocked out on falling edge of bit clock.
End of enumeration elements list.
TSHFD : Transmit Shift Direction.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data transmitted MSB first.
#1 : 1
Data transmitted LSB first.
End of enumeration elements list.
TXDIR : Transmit clock direction
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit clock is external.
#1 : 1
Transmit clock generated internally
End of enumeration elements list.
TFDIR : Transmit Frame Direction.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync is external.
#1 : 1
Frame sync generated internally.
End of enumeration elements list.
TFEN0 : Transmit FIFO Enable 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit FIFO 0 disabled.
#1 : 1
Transmit FIFO 0 enabled.
End of enumeration elements list.
TFEN1 : Transmit FIFO Enable 1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit FIFO 1 disabled.
#1 : 1
Transmit FIFO 1 enabled.
End of enumeration elements list.
TXBIT0 : Transmit Bit 0.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of transmit shift register (MSB aligned).
#1 : 1
Shifting with respect to bit 0 of transmit shift register (LSB aligned).
End of enumeration elements list.
I2S Receive Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFS : Receive Early Frame Sync.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive frame sync initiated as the first bit of data is received.
#1 : 1
Receive frame sync is initiated one bit before the data is received.
End of enumeration elements list.
RFSL : Receive Frame Sync Length.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive frame sync is one-word long.
#1 : 1
Receive frame sync is one-clock-bit long.
End of enumeration elements list.
RFSI : Receive Frame Sync Invert.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive frame sync is active high.
#1 : 1
Receive frame sync is active low.
End of enumeration elements list.
RSCKP : Receive Clock Polarity.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data latched on falling edge of bit clock.
#1 : 1
Data latched on rising edge of bit clock.
End of enumeration elements list.
RSHFD : Receive Shift Direction.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data received MSB first.
#1 : 1
Data received LSB first.
End of enumeration elements list.
RXDIR : Receive Clock Direction.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive Clock is external.
#1 : 1
Receive Clock generated internally.
End of enumeration elements list.
RFDIR : Receive Frame Direction.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame Sync is external.
#1 : 1
Frame Sync generated internally.
End of enumeration elements list.
RFEN0 : Receive FIFO Enable 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO 0 disabled.
#1 : 1
Receive FIFO 0 enabled.
End of enumeration elements list.
RFEN1 : Receive FIFO Enable 1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO 1 disabled.
#1 : 1
Receive FIFO 1 enabled.
End of enumeration elements list.
RXBIT0 : Receive Bit 0.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of receive shift register (MSB aligned).
#1 : 1
Shifting with respect to bit 0 of receive shift register (LSB aligned).
End of enumeration elements list.
RXEXT : Receive Data Extension.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sign extension turned off.
#1 : 1
Sign extension turned on.
End of enumeration elements list.
I2S Transmit Clock Control Registers
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PM : Prescaler Modulus Select.
bits : 0 - 7 (8 bit)
access : read-write
DC : Frame Rate Divider Control.
bits : 8 - 12 (5 bit)
access : read-write
WL : Word Length Control.
bits : 13 - 16 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Reserved. Do not program this value.
#0001 : 0001
Reserved. Do not program this value.
#0010 : 0010
Reserved. Do not program this value.
#0011 : 0011
8
#0100 : 0100
10
#0101 : 0101
12
#0110 : 0110
Reserved. Do not program this value.
#0111 : 0111
16
#1000 : 1000
18
#1001 : 1001
20
#1010 : 1010
22
#1011 : 1011
24
#1100 : 1100
Reserved. Do not program this value.
#1101 : 1101
Reserved. Do not program this value.
#1110 : 1110
Reserved. Do not program this value.
#1111 : 1111
Reserved. Do not program this value.
End of enumeration elements list.
PSR : Prescaler Range.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prescaler bypassed.
#1 : 1
Prescaler used to divide clock by 8.
End of enumeration elements list.
DIV2 : Divide By 2.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divider bypassed.
#1 : 1
Divider used to divide clock by 2.
End of enumeration elements list.
I2S Receive Clock Control Registers
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PM : Prescaler Modulus Select.
bits : 0 - 7 (8 bit)
access : read-write
DC : Frame Rate Divider Control.
bits : 8 - 12 (5 bit)
access : read-write
WL : Word Length Control.
bits : 13 - 16 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Number of Bits/Word: 2; Supported in Implementation: No.
#0001 : 0001
Number of Bits/Word: 4; Supported in Implementation: No.
#0010 : 0010
Number of Bits/Word: 6; Supported in Implementation: No.
#0011 : 0011
Number of Bits/Word: 8; Supported in Implementation: Yes.
#0100 : 0100
Number of Bits/Word: 10; Supported in Implementation: Yes.
#0101 : 0101
Number of Bits/Word: 12; Supported in Implementation: Yes.
#0110 : 0110
Number of Bits/Word: 14; Supported in Implementation: No.
#0111 : 0111
Number of Bits/Word: 16; Supported in Implementation: Yes.
#1000 : 1000
Number of Bits/Word: 18; Supported in Implementation: Yes.
#1001 : 1001
Number of Bits/Word: 20; Supported in Implementation: Yes.
#1010 : 1010
Number of Bits/Word: 22; Supported in Implementation: Yes.
#1011 : 1011
Number of Bits/Word: 24; Supported in Implementation: Yes.
#1100 : 1100
Number of Bits/Word: 26; Supported in Implementation: No.
#1101 : 1101
Number of Bits/Word: 28; Supported in Implementation: No.
#1110 : 1110
Number of Bits/Word: 30; Supported in Implementation: No.
#1111 : 1111
Number of Bits/Word: 32; Supported in Implementation: No.
End of enumeration elements list.
PSR : Prescaler Range.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prescaler bypassed.
#1 : 1
Prescaler used to divide clock by 8.
End of enumeration elements list.
DIV2 : Divide By 2.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divider bypassed.
#1 : 1
Divider used to divide clock by 2.
End of enumeration elements list.
I2S FIFO Control/Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFWM0 : Transmit FIFO Empty WaterMark 0.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0001 : 0001
TFE set when there are more than or equal to 1 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 14 data.
#0010 : 0010
TFE set when there are more than or equal to 2 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 13 data.
#0011 : 0011
TFE set when there are more than or equal to 3 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 12 data.
#0100 : 0100
TFE set when there are more than or equal to 4 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 11 data.
#0101 : 0101
TFE set when there are more than or equal to 5 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 10 data.
#0110 : 0110
TFE set when there are more than or equal to 6 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 9 data.
#0111 : 0111
TFE set when there are more than or equal to 7 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 8 data.
#1000 : 1000
TFE set when there are more than or equal to 8 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 7 data.
#1001 : 1001
TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 6 data.
#1010 : 1010
TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 5 data.
#1011 : 1011
TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 4 data.
#1100 : 1100
TFE set when there are more than or equal to 12 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 3 data.
#1101 : 1101
TFE set when there are more than or equal to 13 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 2 data.
#1110 : 1110
TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 1 data.
#1111 : 1111
TFE set when there are more than or equal to 15 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 0 data.
End of enumeration elements list.
RFWM0 : Receive FIFO Full WaterMark 0.
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0001 : 0001
RFF set when at least one data word have been written to the Receive FIFO Set when RxFIFO = 1,2.....15 data words
#0010 : 0010
RFF set when more than or equal to 2 data word have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words
#0011 : 0011
RFF set when more than or equal to 3 data word have been written to the Receive FIFO. Set when RxFIFO = 3,4.....15 data words
#0100 : 0100
RFF set when more than or equal to 4 data word have been written to the Receive FIFO. Set when RxFIFO = 4,5.....15 data words
#0101 : 0101
RFF set when more than or equal to 5 data word have been written to the Receive FIFO. Set when RxFIFO = 5,6.....15 data words
#0110 : 0110
RFF set when more than or equal to 6 data word have been written to the Receive. Set when RxFIFO = 6,7......15 data words
#0111 : 0111
RFF set when more than or equal to 7 data word have been written to the Receive FIFO. Set when RxFIFO = 7,8......15 data words
#1000 : 1000
RFF set when more than or equal to 8 data word have been written to the Receive FIFO. Set when RxFIFO = 8,9......15 data words
#1001 : 1001
RFF set when more than or equal to 9 data word have been written to the Receive FIFO. Set when RxFIFO = 9,10.....15 data words
#1010 : 1010
RFF set when more than or equal to 10 data word have been written to the Receive FIFO. Set when RxFIFO = 10,11.....15 data words
#1011 : 1011
RFF set when more than or equal to 11 data word have been written to the Receive FIFO. Set when RxFIFO = 11,12.....15 data words
#1100 : 1100
RFF set when more than or equal to 12 data word have been written to the Receive FIFO. Set when RxFIFO = 12,13.....15 data words
#1101 : 1101
RFF set when more than or equal to 13 data word have been written to the Receive FIFO. Set when RxFIFO = 13,14,15data words
#1110 : 1110
RFF set when more than or equal to 14 data word have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words
#1111 : 1111
RFF set when 15 data word have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words
End of enumeration elements list.
TFCNT0 : Transmit FIFO Counter 0.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0 data word in transmit FIFO.
#0001 : 0001
1 data word in transmit FIFO.
#0010 : 0010
2 data word in transmit FIFO.
#0011 : 0011
3 data word in transmit FIFO.
#0100 : 0100
4 data word in transmit FIFO.
#0101 : 0101
5 data word in transmit FIFO.
#0110 : 0110
6 data word in transmit FIFO.
#0111 : 0111
7 data word in transmit FIFO.
#1000 : 1000
8 data word in transmit FIFO.
#1001 : 1001
9 data word in transmit FIFO.
#1010 : 1010
10 data word in transmit FIFO.
#1011 : 1011
11 data word in transmit FIFO.
#1100 : 1100
12 data word in transmit FIFO.
#1101 : 1101
13 data word in transmit FIFO.
#1110 : 1110
14 data word in transmit FIFO.
#1111 : 1111
15 data word in transmit FIFO.
End of enumeration elements list.
RFCNT0 : Receive FIFO Counter 0.
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0 data word in receive FIFO.
#0001 : 0001
1 data word in receive FIFO.
#0010 : 0010
2 data word in receive FIFO.
#0011 : 0011
3 data word in receive FIFO.
#0100 : 0100
4 data word in receive FIFO.
#0101 : 0101
5 data word in receive FIFO.
#0110 : 0110
6 data word in receive FIFO.
#0111 : 0111
7 data word in receive FIFO.
#1000 : 1000
8 data word in receive FIFO.
#1001 : 1001
9 data word in receive FIFO.
#1010 : 1010
10 data word in receive FIFO.
#1011 : 1011
11 data word in receive FIFO.
#1100 : 1100
12 data word in receive FIFO.
#1101 : 1101
13 data word in receive FIFO.
#1110 : 1110
14 data word in receive FIFO.
#1111 : 1111
15 data word in receive FIFO.
End of enumeration elements list.
TFWM1 : Transmit FIFO Empty WaterMark 1.
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0001 : 0001
TFE set when there are more than or equal to 1 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 14 data.
#0010 : 0010
TFE set when there are more than or equal to 2 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 13 data.
#0011 : 0011
TFE set when there are more than or equal to 3 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 12 data.
#0100 : 0100
TFE set when there are more than or equal to 4 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 11 data.
#0101 : 0101
TFE set when there are more than or equal to 5 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 10 data.
#0110 : 0110
TFE set when there are more than or equal to 6 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 9 data.
#0111 : 0111
TFE set when there are more than or equal to 7 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 8 data.
#1000 : 1000
TFE set when there are more than or equal to 8 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 7 data.
#1001 : 1001
TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 6 data.
#1010 : 1010
TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 5 data.
#1011 : 1011
TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 4 data.
#1100 : 1100
TFE set when there are more than or equal to 12 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 3 data.
#1101 : 1101
TFE set when there are more than or equal to 13 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 2 data.
#1110 : 1110
TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 1 data.
#1111 : 1111
TFE set when there are more than or equal to 15 empty slots in Transmit FIFO. (default) Transmit FIFO empty is set when TxFIFO <= 0 data.
End of enumeration elements list.
RFWM1 : Receive FIFO Full WaterMark 1.
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0001 : 0001
RFF set when at least one data word have been written to the Receive FIFO Set when RxFIFO = 1,2.....15 data words
#0010 : 0010
RFF set when more than or equal to 2 data word have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words
#0011 : 0011
RFF set when more than or equal to 3 data word have been written to the Receive FIFO. Set when RxFIFO = 3,4.....15 data words
#0100 : 0100
RFF set when more than or equal to 4 data word have been written to the Receive FIFO. Set when RxFIFO = 4,5.....15 data words
#0101 : 0101
RFF set when more than or equal to 5 data word have been written to the Receive FIFO. Set when RxFIFO = 5,6.....15 data words
#0110 : 0110
RFF set when more than or equal to 6 data word have been written to the Receive. Set when RxFIFO = 6,7......15 data words
#0111 : 0111
RFF set when more than or equal to 7 data word have been written to the Receive FIFO. Set when RxFIFO = 7,8......15 data words
#1000 : 1000
RFF set when more than or equal to 8 data word have been written to the Receive FIFO. Set when RxFIFO = 8,9......15 data words
#1001 : 1001
RFF set when more than or equal to 9 data word have been written to the Receive FIFO. Set when RxFIFO = 9,10.....15 data words
#1010 : 1010
RFF set when more than or equal to 10 data word have been written to the Receive FIFO. Set when RxFIFO = 10,11.....15 data words
#1011 : 1011
RFF set when more than or equal to 11 data word have been written to the Receive FIFO. Set when RxFIFO = 11,12.....15 data words
#1100 : 1100
RFF set when more than or equal to 12 data word have been written to the Receive FIFO. Set when RxFIFO = 12,13.....15 data words
#1101 : 1101
RFF set when more than or equal to 13 data word have been written to the Receive FIFO. Set when RxFIFO = 13,14,15data words
#1110 : 1110
RFF set when more than or equal to 14 data word have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words
#1111 : 1111
RFF set when 15 data word have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words
End of enumeration elements list.
TFCNT1 : Transmit FIFO Counter1.
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0 data word in transmit FIFO.
#0001 : 0001
1 data word in transmit FIFO.
#0010 : 0010
2 data word in transmit FIFO.
#0011 : 0011
3 data word in transmit FIFO.
#0100 : 0100
4 data word in transmit FIFO.
#0101 : 0101
5 data word in transmit FIFO.
#0110 : 0110
6 data word in transmit FIFO.
#0111 : 0111
7 data word in transmit FIFO.
#1000 : 1000
8 data word in transmit FIFO.
#1001 : 1001
9 data word in transmit FIFO.
#1010 : 1010
10 data word in transmit FIFO.
#1011 : 1011
11 data word in transmit FIFO.
#1100 : 1100
12 data word in transmit FIFO.
#1101 : 1101
13 data word in transmit FIFO.
#1110 : 1110
14 data word in transmit FIFO.
#1111 : 1111
15 data word in transmit FIFO.
End of enumeration elements list.
RFCNT1 : Receive FIFO Counter1.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0 data word in receive FIFO.
#0001 : 0001
1 data word in receive FIFO.
#0010 : 0010
2 data word in receive FIFO.
#0011 : 0011
3 data word in receive FIFO.
#0100 : 0100
4 data word in receive FIFO.
#0101 : 0101
5 data word in receive FIFO.
#0110 : 0110
6 data word in receive FIFO.
#0111 : 0111
7 data word in receive FIFO.
#1000 : 1000
8 data word in receive FIFO.
#1001 : 1001
9 data word in receive FIFO.
#1010 : 1010
10 data word in receive FIFO.
#1011 : 1011
11 data word in receive FIFO.
#1100 : 1100
12 data word in receive FIFO.
#1101 : 1101
13 data word in receive FIFO.
#1110 : 1110
14 data word in receive FIFO.
#1111 : 1111
15 data word in receive FIFO.
End of enumeration elements list.
I2S AC97 Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AC97EN : AC97 Mode Enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
AC97 mode disabled.
#1 : 1
I2S in AC97 mode.
End of enumeration elements list.
FV : Fixed/Variable Operation.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
AC97 Fixed Mode
#1 : 1
AC97 Variable Mode.
End of enumeration elements list.
TIF : Tag in FIFO.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tag info stored in ATAG register.
#1 : 1
Tag info stored in ATAG register and Rx FIFO 0.
End of enumeration elements list.
RD : Read Command.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Next frame will not have a Read Command.
#1 : 1
Next frame will have a Read Command.
End of enumeration elements list.
WR : Write Command.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Next frame will not have a Write Command.
#1 : 1
Next frame will have a Write Command.
End of enumeration elements list.
FRDIV : Frame Rate Divider.
bits : 5 - 10 (6 bit)
access : read-write
I2S AC97 Command Address Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACADD : AC97 Command Address.
bits : 0 - 18 (19 bit)
access : read-write
I2S Transmit Data Registers 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX1 : I2S transmit data
bits : 0 - 31 (32 bit)
access : read-write
I2S AC97 Command Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACDAT : AC97 Command Data.
bits : 0 - 19 (20 bit)
access : read-write
I2S AC97 Tag Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATAG : AC97 Tag Value.
bits : 0 - 15 (16 bit)
access : read-write
I2S Transmit Time Slot Mask Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSK : Transmit Mask.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
Valid Time Slot.
#1 : 1
Time Slot masked (no data transmitted in this time slot).
End of enumeration elements list.
I2S Receive Time Slot Mask Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RMSK : Receive Mask.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
Valid Time Slot.
#1 : 1
Time Slot masked (no data received in this time slot).
End of enumeration elements list.
I2S AC97 Channel Status Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACCST : AC97 Channel Status.
bits : 0 - 9 (10 bit)
access : read-only
Enumeration:
#0 : 0
Data channel disabled.
#1 : 1
Data channel enabled.
End of enumeration elements list.
I2S AC97 Channel Enable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCEN : AC97 Channel Enable.
bits : 0 - 9 (10 bit)
access : write-only
Enumeration:
#0 : 0
Write has no effect.
#1 : 1
Write enables the corresponding data channel.
End of enumeration elements list.
I2S AC97 Channel Disable Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCDIS : AC97 Channel Disable.
bits : 0 - 9 (10 bit)
access : write-only
Enumeration:
#0 : 0
Write has no effect.
#1 : 1
Write disables the corresponding data channel.
End of enumeration elements list.
I2S Receive Data Registers 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX0 : I2S Receive Data
bits : 0 - 31 (32 bit)
access : read-write
I2S Receive Data Registers 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX1 : I2S Receive Data
bits : 0 - 31 (32 bit)
access : read-write
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