\n

VREF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TRM

SC


TRM

VREF Trim Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRM TRM read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRIM

TRIM : Trim bits
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#000000 : 000000

Min

#111111 : 111111

Max

End of enumeration elements list.


SC

VREF Status and Control Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC SC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MODE_LV VREFST REGEN VREFEN

MODE_LV : Buffer Mode selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Bandgap on only, for stabilization and startup

#10 : 10

Tight-regulation buffer enabled

End of enumeration elements list.

VREFST : Internal Voltage Reference has settled
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

The bandgap is disabled or not ready.

#1 : 1

The bandgap is ready.

End of enumeration elements list.

REGEN : Regulator enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal 1.75 V regulator is disabled.

#1 : 1

Internal 1.75 V regulator is enabled.

End of enumeration elements list.

VREFEN : Internal Voltage Reference enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The module is disabled.

#1 : 1

The module is enabled.

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.