Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x108 byte (0x0)
mem_usage : registers
protection : not protected
SAI Transmit Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRDE : FIFO request DMA enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
FWDE : FIFO warning DMA enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
FRIE : FIFO request interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FWIE : FIFO warning interrupt enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FEIE : FIFO error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt,
#1 : 1
Enables the interrupt.
End of enumeration elements list.
SEIE : Sync error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
WSIE : Word start interrupt enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
FRF : FIFO request flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO watermark not reached.
#1 : 1
Transmit FIFO watermark has been reached.
End of enumeration elements list.
FWF : FIFO warning flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
No enabled transmit FIFO is empty.
#1 : 1
Enabled transmit FIFO is empty.
End of enumeration elements list.
FEF : FIFO error flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit underrun not detected.
#1 : 1
Transmit underrun detected.
End of enumeration elements list.
SEF : Sync error flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sync error not detected.
#1 : 1
Frame sync error detected.
End of enumeration elements list.
WSF : Word start flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Start of word not detected.
#1 : 1
Start of word detected.
End of enumeration elements list.
SR : Software reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Software reset.
End of enumeration elements list.
FR : FIFO reset
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
FIFO reset.
End of enumeration elements list.
BCE : Bit Clock Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit bit clock is disabled
#1 : 1
Transmit bit clock is enabled
End of enumeration elements list.
DBGE : Debug enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter is disabled in debug mode, after completing the current frame.
#1 : 1
Transmitter is enabled in debug mode.
End of enumeration elements list.
STOPE : Stop enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter disabled in stop mode.
#1 : 1
Transmitter enabled in stop mode.
End of enumeration elements list.
TE : Transmitter enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter is disabled.
#1 : 1
Transmitter is enabled, or transmitter has been disabled and not end of frame.
End of enumeration elements list.
SAI Transmit Configuration 4 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSD : Frame sync direction
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame Sync is generated externally (slave mode).
#1 : 1
Frame Sync is generated internally (master mode).
End of enumeration elements list.
FSP : Frame sync polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync is active high.
#1 : 1
Frame sync is active low.
End of enumeration elements list.
FSE : Frame sync early
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync asserts with the first bit of the frame.
#1 : 1
Frame sync asserts one bit before the first bit of the frame.
End of enumeration elements list.
MF : MSB first
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
LBS is transmitted/received first.
#1 : 1
MBS is transmitted/received first.
End of enumeration elements list.
SYWD : Sync width
bits : 8 - 12 (5 bit)
access : read-write
FRSZ : Frame size
bits : 16 - 20 (5 bit)
access : read-write
SAI MCLK Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MICS : MCLK Input Clock Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
MCLK Divider input clock 0 selected.
#01 : 01
MCLK Divider input clock 1 selected.
#10 : 10
MCLK Divider input clock 2 selected.
#11 : 11
MCLK Divider input clock 3 selected.
End of enumeration elements list.
MOE : MCLK Output Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAI_MCLK pin is configured as an input that bypasses the MCLK Divider.
#1 : 1
SAI_MCLK pin is configured as an output from the MCLK Divider and the MCLK Divider is enabled.
End of enumeration elements list.
DUF : Divider Update Flag
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
MCLK Divider ratio is not being updated currently.
#1 : 1
MCLK Divider ratio is updating on-the-fly. Furthur updates to the MCLK Divider ratio are blocked while this flag remains set.
End of enumeration elements list.
MCLK Divide Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDE : MCLK Divide
bits : 0 - 11 (12 bit)
access : read-write
FRACT : MCLK Fraction
bits : 12 - 19 (8 bit)
access : read-write
SAI Transmit Configuration 5 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBT : First bit shifted
bits : 8 - 12 (5 bit)
access : read-write
W0W : Word 0 width
bits : 16 - 20 (5 bit)
access : read-write
WNW : Word N width
bits : 24 - 28 (5 bit)
access : read-write
SAI Receive Data Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive data register
bits : 0 - 31 (32 bit)
access : read-only
SAI Receive FIFO Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO pointer
bits : 0 - 3 (4 bit)
access : read-only
WFP : Write FIFO pointer
bits : 16 - 19 (4 bit)
access : read-only
SAI Receive Data Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive data register
bits : 0 - 31 (32 bit)
access : read-only
SAI Receive FIFO Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO pointer
bits : 0 - 3 (4 bit)
access : read-only
WFP : Write FIFO pointer
bits : 16 - 19 (4 bit)
access : read-only
SAI Transmit Configuration 1 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFW : Transmit FIFO watermark
bits : 0 - 2 (3 bit)
access : read-write
SAI Transmit Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit data register
bits : 0 - 31 (32 bit)
access : write-only
SAI Transmit Mask Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TWM : Transmit word mask
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
SAI Transmit Data Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit data register
bits : 0 - 31 (32 bit)
access : write-only
SAI Transmit Configuration 2 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Bit clock divide
bits : 0 - 7 (8 bit)
access : read-write
BCD : Bit clock direction
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit clock is generated externally (slave mode).
#1 : 1
Bit clock is generated internally (master mode).
End of enumeration elements list.
BCP : Bit clock polarity
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit Clock is active high (drive outputs on rising edge and sample inputs on falling edge).
#1 : 1
Bit Clock is active low (drive outputs on falling edge and sample inputs on rising edge).
End of enumeration elements list.
MSEL : MCLK Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock selected.
#01 : 01
Master Clock 1 selected.
#10 : 10
Master Clock 2 selected.
#11 : 11
Master Clock 3 selected.
End of enumeration elements list.
BCI : Bit Clock Input
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Internal logic is clocked by external bit clock.
End of enumeration elements list.
BCS : Bit Clock Swap
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use the normal bit clock source.
#1 : 1
Swap the bit clock source.
End of enumeration elements list.
SYNC : Synchronous Mode
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
Asynchronous mode.
#01 : 01
Synchronous with receiver.
#10 : 10
Synchronous with another SAI transmitter.
#11 : 11
Synchronous with another SAI receiver.
End of enumeration elements list.
SAI Transmit FIFO Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO pointer
bits : 0 - 3 (4 bit)
access : read-only
WFP : Write FIFO pointer
bits : 16 - 19 (4 bit)
access : read-only
SAI Receive Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRDE : FIFO request DMA enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
FWDE : FIFO warning DMA enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
FRIE : FIFO request interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FWIE : FIFO warning interrupt enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FEIE : FIFO error interrupt enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt,
#1 : 1
Enables the interrupt.
End of enumeration elements list.
SEIE : Sync error interrupt enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
WSIE : Word start interrupt enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
FRF : FIFO request flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO watermark not reached.
#1 : 1
Receive FIFO watermark has been reached.
End of enumeration elements list.
FWF : FIFO warning flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
No enabled receive FIFO is full.
#1 : 1
Enabled receive FIFO is full.
End of enumeration elements list.
FEF : FIFO error flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive overflow not detected.
#1 : 1
Receive overflow detected.
End of enumeration elements list.
SEF : Sync error flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sync error not detected.
#1 : 1
Frame sync error detected.
End of enumeration elements list.
WSF : Word start flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Start of word not detected.
#1 : 1
Start of word detected.
End of enumeration elements list.
SR : Software reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Software reset.
End of enumeration elements list.
FR : FIFO reset
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
FIFO reset.
End of enumeration elements list.
BCE : Bit Clock enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive bit clock is disabled
#1 : 1
Receive bit clock is enabled
End of enumeration elements list.
DBGE : Debug enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver is disabled in debug mode, after completing the current frame.
#1 : 1
Receiver is enabled in debug mode.
End of enumeration elements list.
STOPE : Stop enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver disabled in stop mode.
#1 : 1
Receiver enabled in stop mode.
End of enumeration elements list.
RE : Receiver enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver is disabled.
#1 : 1
Receiver is enabled, or receiver has been disabled and not end of frame.
End of enumeration elements list.
SAI Receive Configuration 1 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFW : Receive FIFO watermark
bits : 0 - 2 (3 bit)
access : read-write
SAI Receive Configuration 2 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Bit clock divide
bits : 0 - 7 (8 bit)
access : read-write
BCD : Bit clock direction
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit clock is generated externally (slave mode).
#1 : 1
Bit clock is generated internally (master mode).
End of enumeration elements list.
BCP : Bit clock polarity
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit Clock is active high (drive outputs on rising edge and sample inputs on falling edge).
#1 : 1
Bit Clock is active low (drive outputs on falling edge and sample inputs on rising edge).
End of enumeration elements list.
MSEL : MCLK Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock selected.
#01 : 01
Master Clock 1 selected.
#10 : 10
Master Clock 2 selected.
#11 : 11
Master Clock 3 selected.
End of enumeration elements list.
BCI : Bit Clock Input
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Internal logic is clocked as if bit clock was externally generated.
End of enumeration elements list.
BCS : Bit Clock Swap
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use the normal bit clock source.
#1 : 1
Swap the bit clock source.
End of enumeration elements list.
SYNC : Synchronous Mode
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
Asynchronous mode.
#01 : 01
Synchronous with transmitter.
#10 : 10
Synchronous with another SAI receiver.
#11 : 11
Synchronous with another SAI transmitter.
End of enumeration elements list.
SAI Receive Configuration 3 Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDFL : Word flag configuration
bits : 0 - 4 (5 bit)
access : read-write
RCE : Receive channel enable
bits : 16 - 17 (2 bit)
access : read-write
SAI Receive Configuration 4 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSD : Frame sync direction
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame Sync is generated externally (slave mode).
#1 : 1
Frame Sync is generated internally (master mode).
End of enumeration elements list.
FSP : Frame sync polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync is active high.
#1 : 1
Frame sync is active low.
End of enumeration elements list.
FSE : Frame sync early
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync asserts with the first bit of the frame.
#1 : 1
Frame sync asserts one bit before the first bit of the frame.
End of enumeration elements list.
MF : MSB first
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
LBS is transmitted/received first.
#1 : 1
MBS is transmitted/received first.
End of enumeration elements list.
SYWD : Sync width
bits : 8 - 12 (5 bit)
access : read-write
FRSZ : Frame size
bits : 16 - 20 (5 bit)
access : read-write
SAI Receive Configuration 5 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBT : First bit shifted
bits : 8 - 12 (5 bit)
access : read-write
W0W : Word 0 width
bits : 16 - 20 (5 bit)
access : read-write
WNW : Word N width
bits : 24 - 28 (5 bit)
access : read-write
SAI Transmit Configuration 3 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDFL : Word flag configuration
bits : 0 - 4 (5 bit)
access : read-write
TCE : Transmit channel enable
bits : 16 - 17 (2 bit)
access : read-write
SAI Transmit FIFO Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO pointer
bits : 0 - 3 (4 bit)
access : read-only
WFP : Write FIFO pointer
bits : 16 - 19 (4 bit)
access : read-only
SAI Receive Mask Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWM : Receive word mask
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
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