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GPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

GPIOA_PDOR

PDOR

GPIOA_PDIR

PDIR

GPIOA_PDDR

PDDR

GPIOA_PSOR

PSOR

GPIOA_PCOR

PCOR

GPIOA_PTOR

PTOR


GPIOA_PDOR

Port Data Output Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_PDOR GPIOA_PDOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO

PDO : Port Data Output
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Logic level 0 is driven on pin provided pin is configured for General Purpose Output.

#1 : 1

Logic level 1 is driven on pin provided pin is configured for General Purpose Output.

End of enumeration elements list.


PDOR

Port Data Output Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDOR PDOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO

PDO : Port Data Output
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Logic level 0 is driven on pin provided pin is configured for General Purpose Output.

#1 : 1

Logic level 1 is driven on pin provided pin is configured for General Purpose Output.

End of enumeration elements list.


GPIOA_PDIR

Port Data Input Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_PDIR GPIOA_PDIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDI

PDI : Port Data Input
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

#0 : 0

Pin logic level is logic zero or is configured for use by digital function.

#1 : 1

Pin logic level is logic one.

End of enumeration elements list.


PDIR

Port Data Input Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIR PDIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDI

PDI : Port Data Input
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

#0 : 0

Pin logic level is logic zero or is configured for use by digital function.

#1 : 1

Pin logic level is logic one.

End of enumeration elements list.


GPIOA_PDDR

Port Data Direction Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_PDDR GPIOA_PDDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDD

PDD : Port data direction
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Pin is configured as general purpose input, if configured for the GPIO function

#1 : 1

Pin is configured for general purpose output, if configured for the GPIO function

End of enumeration elements list.


PDDR

Port Data Direction Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDDR PDDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDD

PDD : Port data direction
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Pin is configured as general purpose input, if configured for the GPIO function

#1 : 1

Pin is configured for general purpose output, if configured for the GPIO function

End of enumeration elements list.


GPIOA_PSOR

Port Set Output Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_PSOR GPIOA_PSOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTSO

PTSO : Port Set Output
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding bit in PDORn does not change.

#1 : 1

Corresponding bit in PDORn is set to logic one.

End of enumeration elements list.


PSOR

Port Set Output Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSOR PSOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTSO

PTSO : Port Set Output
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding bit in PDORn does not change.

#1 : 1

Corresponding bit in PDORn is set to logic one.

End of enumeration elements list.


GPIOA_PCOR

Port Clear Output Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_PCOR GPIOA_PCOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTCO

PTCO : Port Clear Output
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding bit in PDORn does not change.

#1 : 1

Corresponding bit in PDORn is cleared to logic zero.

End of enumeration elements list.


PCOR

Port Clear Output Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCOR PCOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTCO

PTCO : Port Clear Output
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding bit in PDORn does not change.

#1 : 1

Corresponding bit in PDORn is cleared to logic zero.

End of enumeration elements list.


GPIOA_PTOR

Port Toggle Output Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_PTOR GPIOA_PTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTTO

PTTO : Port Toggle Output
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding bit in PDORn does not change.

#1 : 1

Corresponding bit in PDORn is set to the inverse of its existing logic state.

End of enumeration elements list.


PTOR

Port Toggle Output Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PTOR PTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTTO

PTTO : Port Toggle Output
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding bit in PDORn does not change.

#1 : 1

Corresponding bit in PDORn is set to the inverse of its existing logic state.

End of enumeration elements list.



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