\n
address_offset : 0x8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
Crossbar switch (AXBS) slave configuration
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASC : Each bit in the ASC field indicates if there is a corresponding connection to the crossbar switch's slave input port.
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
#0 : 0
A bus slave connection to AXBS input port n is absent
#1 : 1
A bus slave connection to AXBS input port n is present
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only
Crossbar switch (AXBS) master configuration
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMC : Each bit in the AMC field indicates if there is a corresponding connection to the AXBS master input port.
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
#0 : 0
A bus master connection to AXBS input port n is absent
#1 : 1
A bus master connection to AXBS input port n is present
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only
Control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 8 (9 bit)
access : read-only
RESERVED : no description available
bits : 9 - 9 (1 bit)
access : read-only
RESERVED : no description available
bits : 10 - 23 (14 bit)
access : read-only
SRAMUAP : SRAM_U arbitration priority
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Round robin
#01 : 01
Special round robin (favors SRAM backoor accesses over the processor)
#10 : 10
Fixed priority. Processor has highest, backdoor has lowest
#11 : 11
Fixed priority. Backdoor has highest, processor has lowest
End of enumeration elements list.
SRAMUWP : SRAM_U write protect
bits : 26 - 26 (1 bit)
access : read-write
RESERVED : no description available
bits : 27 - 27 (1 bit)
access : read-only
SRAMLAP : SRAM_L arbitration priority
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
Round robin
#01 : 01
Special round robin (favors SRAM backoor accesses over the processor)
#10 : 10
Fixed priority. Processor has highest, backdoor has lowest
#11 : 11
Fixed priority. Backdoor has highest, processor has lowest
End of enumeration elements list.
SRAMLWP : SRAM_L write protect
bits : 30 - 30 (1 bit)
access : read-write
RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-only
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