Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x240 byte (0x0)
mem_usage : registers
protection : not protected
Flash Access Protection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0AP : Master 0 Access Protection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M1AP : Master 1 Access Protection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M2AP : Master 2 Access Protection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M3AP : Master 3 Access Protection
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M4AP : Master 4 Access Protection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M5AP : Master 5 Access Protection
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M6AP : Master 6 Access Protection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M7AP : Master 7 Access Protection
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master.
#01 : 01
Only read accesses may be performed by this master.
#10 : 10
Only write accesses may be performed by this master.
#11 : 11
Both read and write accesses may be performed by this master.
End of enumeration elements list.
M0PFD : Master 0 Prefetch Disable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M1PFD : Master 1 Prefetch Disable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M2PFD : Master 2 Prefetch Disable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M3PFD : Master 3 Prefetch Disable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M4PFD : Master 4 Prefetch Disable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M5PFD : Master 5 Prefetch Disable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M6PFD : Master 6 Prefetch Disable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M7PFD : Master 7 Prefetch Disable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Cache Tag Storage
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
tag : 15-bit tag for cache entry
bits : 4 - 18 (15 bit)
access : read-write
Cache Tag Storage
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
tag : 15-bit tag for cache entry
bits : 4 - 18 (15 bit)
access : read-write
Cache Tag Storage
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
tag : 15-bit tag for cache entry
bits : 4 - 18 (15 bit)
access : read-write
Cache Tag Storage
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
tag : 15-bit tag for cache entry
bits : 4 - 18 (15 bit)
access : read-write
Cache Tag Storage
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
tag : 15-bit tag for cache entry
bits : 4 - 18 (15 bit)
access : read-write
Cache Tag Storage
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
tag : 15-bit tag for cache entry
bits : 4 - 18 (15 bit)
access : read-write
Cache Tag Storage
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
tag : 15-bit tag for cache entry
bits : 4 - 18 (15 bit)
access : read-write
Cache Tag Storage
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
tag : 15-bit tag for cache entry
bits : 4 - 18 (15 bit)
access : read-write
Flash Bank 0 Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B0SEBE : Bank 0 Single Entry Buffer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single entry buffer is disabled.
#1 : 1
Single entry buffer is enabled.
End of enumeration elements list.
B0IPE : Bank 0 Instruction Prefetch Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to instruction fetches.
#1 : 1
Enable prefetches in response to instruction fetches.
End of enumeration elements list.
B0DPE : Bank 0 Data Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to data references.
#1 : 1
Enable prefetches in response to data references.
End of enumeration elements list.
B0ICE : Bank 0 Instruction Cache Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not cache instruction fetches.
#1 : 1
Cache instruction fetches.
End of enumeration elements list.
B0DCE : Bank 0 Data Cache Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not cache data references.
#1 : 1
Cache data references.
End of enumeration elements list.
CRC : Cache Replacement Control
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 000
LRU replacement algorithm per set across all four ways
#001 : 001
Reserved
#010 : 010
Independent LRU with ways [0-1] for ifetches, [2-3] for data
#011 : 011
Independent LRU with ways [0-2] for ifetches, [3] for data
#1xx : 1xx
Reserved
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only
RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only
B0MW : Bank 0 Memory Width
bits : 17 - 18 (2 bit)
access : read-only
Enumeration:
#00 : 00
32 bits
#01 : 01
64 bits
#10 : 10
Reserved
#11 : 11
Reserved
End of enumeration elements list.
S_B_INV : Invalidate Prefetch Speculation Buffer
bits : 19 - 19 (1 bit)
access : write-only
Enumeration:
#0 : 0
Speculation buffer and single entry buffer are not affected.
#1 : 1
Invalidate (clear) speculation buffer and single entry buffer.
End of enumeration elements list.
CINV_WAY : Cache Invalidate Way x
bits : 20 - 23 (4 bit)
access : write-only
Enumeration:
#0 : 0
No cache way invalidation for the corresponding cache
#1 : 1
Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
End of enumeration elements list.
CLCK_WAY : Cache Lock Way x
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0 : 0
Cache way is unlocked and may be displaced
#1 : 1
Cache way is locked and its contents are not displaced
End of enumeration elements list.
B0RWSC : Bank 0 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only
Cache Data Storage (upper word)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (upper word)
address_offset : 0x698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lower word)
address_offset : 0x6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Flash Bank 1 Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B1SEBE : Bank 1 Single Entry Buffer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single entry buffer is disabled.
#1 : 1
Single entry buffer is enabled.
End of enumeration elements list.
B1IPE : Bank 1 Instruction Prefetch Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to instruction fetches.
#1 : 1
Enable prefetches in response to instruction fetches.
End of enumeration elements list.
B1DPE : Bank 1 Data Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to data references.
#1 : 1
Enable prefetches in response to data references.
End of enumeration elements list.
B1ICE : Bank 1 Instruction Cache Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not cache instruction fetches.
#1 : 1
Cache instruction fetches.
End of enumeration elements list.
B1DCE : Bank 1 Data Cache Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not cache data references.
#1 : 1
Cache data references.
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only
RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only
RESERVED : no description available
bits : 16 - 16 (1 bit)
access : read-only
RESERVED : no description available
bits : 16 - 16 (1 bit)
access : read-only
B1MW : Bank 1 Memory Width
bits : 17 - 18 (2 bit)
access : read-only
Enumeration:
#00 : 00
32 bits
#01 : 01
64 bits
#10 : 10
Reserved
#11 : 11
Reserved
End of enumeration elements list.
B1RWSC : Bank 1 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only
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