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USBHS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x204 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ID

HWTXBUF

GPTIMER0LD

HCIVERSION

HCSPARAMS

GPTIMER0CTL

HCCPARAMS

DCIVERSION

DCCPARAMS

HWRXBUF

USBCMD

USBSTS

USBINTR

FRINDEX

DEVICEADDR

PERIODICLISTBASE

ASYNCLISTADDR

EPLISTADDR

TTCTRL

BURSTSIZE

TXFILLTUNING

ULPI_VIEWPORT

ENDPTNAK

ENDPTNAKEN

CONFIGFLAG

PORTSC1

GPTIMER1LD

GPTIMER1CTL

OTGSC

USBMODE

EPSETUPSR

EPPRIME

EPFLUSH

EPSR

EPCOMPLETE

EPCR0

USBGENCTRL

EPCR1

HWGENERAL

EPCR2

EPCR3

HWHOST

USB_SBUSCFG

HWDEVICE


ID

Identification Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ID ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID RESERVED NID RESERVED TAG REVISION VERSION VERSIONID

ID : Configuration number
bits : 0 - 5 (6 bit)
access : read-only

RESERVED : Reserved
bits : 6 - 7 (2 bit)
access : read-only

NID : no description available
bits : 8 - 13 (6 bit)
access : read-only

RESERVED : Reserved
bits : 14 - 15 (2 bit)
access : read-only

TAG : Tag
bits : 16 - 20 (5 bit)
access : read-only

REVISION : Revision
bits : 21 - 24 (4 bit)
access : read-only

VERSION : Version
bits : 25 - 28 (4 bit)
access : read-only

VERSIONID : Version ID
bits : 29 - 31 (3 bit)
access : read-only


HWTXBUF

Transmit Buffer Hardware Parameters Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWTXBUF HWTXBUF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBURST TXADD TXCHANADD RESERVED TXLC

TXBURST : Transmit Burst.
bits : 0 - 7 (8 bit)
access : read-only

TXADD : Transmit Address.
bits : 8 - 15 (8 bit)
access : read-only

TXCHANADD : Transmit Channel Address
bits : 16 - 23 (8 bit)
access : read-only

RESERVED : Reserved
bits : 24 - 30 (7 bit)
access : read-only

TXLC : Transmit local Context Registers
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Store device transmit contexts in the TX FIFO

#1 : 1

Store device transmit contexts in a register file

End of enumeration elements list.


GPTIMER0LD

General Purpose Timer n Load Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER0LD GPTIMER0LD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTLD RESERVED

GPTLD : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : Reserved
bits : 24 - 31 (8 bit)
access : read-only


HCIVERSION

Host Controller Interface Version and Capability Registers Length Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCIVERSION HCIVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPLENGTH RESERVED HCIVERSION

CAPLENGTH : Capability registers length
bits : 0 - 7 (8 bit)
access : read-only

RESERVED : Reserved
bits : 8 - 15 (8 bit)
access : read-only

HCIVERSION : EHCI revision number
bits : 16 - 31 (16 bit)
access : read-only


HCSPARAMS

Host Controller Structural Parameters Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCSPARAMS HCSPARAMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N_PORTS PPC RESERVED N_PCC N_CC PI RESERVED N_PTT N_TT RESERVED

N_PORTS : Number of Ports
bits : 0 - 3 (4 bit)
access : read-only

PPC : Power Port Control
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#1 : 1

Ports have power port switches

End of enumeration elements list.

RESERVED : Reserved
bits : 5 - 7 (3 bit)
access : read-only

N_PCC : Number Ports per CC
bits : 8 - 11 (4 bit)
access : read-only

N_CC : Number of Companion Controllers
bits : 12 - 15 (4 bit)
access : read-only

PI : Port Indicators
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

No port indicator fields

#1 : 1

The port status and control registers include a R/W field for controlling the state of the port indicator

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 19 (3 bit)
access : read-only

N_PTT : Ports per Transaction Translator
bits : 20 - 23 (4 bit)
access : read-only

N_TT : Number of Transaction Translators.
bits : 24 - 27 (4 bit)
access : read-only

RESERVED : Reserved
bits : 28 - 31 (4 bit)
access : read-only


GPTIMER0CTL

General Purpose Timer n Control Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER0CTL GPTIMER0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTCNT MODE RESERVED RST RUN

GPTCNT : Timer Count
bits : 0 - 23 (24 bit)
access : read-only

MODE : Timer Mode
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

One shot

#1 : 1

Repeat

End of enumeration elements list.

RESERVED : Reserved
bits : 25 - 29 (5 bit)
access : read-only

RST : Timer Reset
bits : 30 - 30 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Load counter value

End of enumeration elements list.

RUN : Timer Run
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer stop

#1 : 1

Timer run

End of enumeration elements list.


HCCPARAMS

Host Controller Capability Parameters Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCCPARAMS HCCPARAMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC PFL ASP RESERVED IST EECP RESERVED

ADC : 64-bit addressing capability.
bits : 0 - 0 (1 bit)
access : read-only

PFL : Programmable Frame List flag
bits : 1 - 1 (1 bit)
access : read-only

ASP : Asynchronous Schedule Park capability
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Park not supported.

#1 : 1

Park supported.

End of enumeration elements list.

RESERVED : Reserved
bits : 3 - 3 (1 bit)
access : read-only

IST : Isochronous Scheduling Threshold
bits : 4 - 7 (4 bit)
access : read-only

Enumeration:

#0 : 0

The value of the least significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data structures (one or more) before flushing the state

End of enumeration elements list.

EECP : EHCI Extended Capabilities Pointer
bits : 8 - 15 (8 bit)
access : read-only

Enumeration:

#0 : 0

No extended capabilities are implemented

End of enumeration elements list.

RESERVED : Reserved
bits : 16 - 31 (16 bit)
access : read-only


DCIVERSION

Device Controller Interface Version
address_offset : 0x122 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCIVERSION DCIVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCIVERSION

DCIVERSION : no description available
bits : 0 - 15 (16 bit)
access : read-only


DCCPARAMS

Device Controller Capability Parameters
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCCPARAMS DCCPARAMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN RESERVED DC HC RESERVED

DEN : Device Endpoint Number
bits : 0 - 4 (5 bit)
access : read-only

RESERVED : Reserved
bits : 5 - 6 (2 bit)
access : read-only

DC : Device Capable
bits : 7 - 7 (1 bit)
access : read-only

HC : Host Capable
bits : 8 - 8 (1 bit)
access : read-only

RESERVED : Reserved
bits : 9 - 31 (23 bit)
access : read-only


HWRXBUF

Receive Buffer Hardware Parameters Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWRXBUF HWRXBUF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBURST RXADD RESERVED

RXBURST : Receive Burst.
bits : 0 - 7 (8 bit)
access : read-only

RXADD : Receive Address.
bits : 8 - 15 (8 bit)
access : read-only

RESERVED : Reserved
bits : 16 - 31 (16 bit)
access : read-only


USBCMD

USB Command Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCMD USBCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS RST FS PSE ASE IAA RESERVED ASP RESERVED ASPE RESERVED SUTW ATDTW FS2 ITC RESERVED

RS : Run/Stop
bits : 0 - 0 (1 bit)
access : read-write

RST : Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

FS : Frame list Size
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

When FS2 = 0, the size is 1024 elements (4096 bytes). When FS2 = 1, the size is 64 elements (256 bytes).

#01 : 01

When FS2 = 0, the size is 512 elements (2048 bytes). When FS2 = 1, the size is 32 elements (128 bytes).

#10 : 10

When FS2 = 0, the size is 256 elements (1024 bytes). When FS2 = 1, the size is 16 elements (64 bytes).

#11 : 11

When FS2 = 0, the size is 128 elements (512 bytes). When FS2 = 1, the size is 8 elements (32 bytes).

End of enumeration elements list.

PSE : Periodic Schedule Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not process periodic schedule.

#1 : 1

Use the PERIODICLISTBASE register to access the periodic schedule.

End of enumeration elements list.

ASE : Asynchronous Schedule Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not process asynchronous schedule.

#1 : 1

Use the ASYNCLISTADDR register to access asynchronous schedule.

End of enumeration elements list.

IAA : Interrupt on Async Advance doorbell
bits : 6 - 6 (1 bit)
access : read-write

RESERVED : Reserved
bits : 7 - 7 (1 bit)
access : read-only

ASP : Asynchronous Schedule Park mode count
bits : 8 - 9 (2 bit)
access : read-write

RESERVED : Reserved
bits : 10 - 10 (1 bit)
access : read-only

ASPE : Asynchronous Schedule Park mode Enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Park mode disabled

#1 : 1

Park mode enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 12 - 12 (1 bit)
access : read-only

SUTW : Setup TripWire
bits : 13 - 13 (1 bit)
access : read-write

ATDTW : Add dTD TripWire
bits : 14 - 14 (1 bit)
access : read-write

FS2 : Frame list Size 2
bits : 15 - 15 (1 bit)
access : read-write

ITC : Interrupt Threshold Control
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

#0 : 0

Immediate (no threshold)

#1 : 1

1 microframe

#10 : 10

2 microframes

#100 : 100

4 microframes

#1000 : 1000

8 microframes

#10000 : 10000

16 microframes

#100000 : 100000

32 microframes

#1000000 : 1000000

64 microframes

End of enumeration elements list.

RESERVED : Reserved
bits : 24 - 31 (8 bit)
access : read-only


USBSTS

USB Status Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSTS USBSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UI UEI PCI FRI SEI AAI URI SRI SLI RESERVED ULPII RESERVED HCH RCL PS AS NAKI RESERVED UAI UPI RESERVED TI0 TI1 RESERVED

UI : USB Interrupt (USBINT)
bits : 0 - 0 (1 bit)
access : read-write

UEI : USB Error Interrupt
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No error

#1 : 1

Error detected

End of enumeration elements list.

PCI : Port Change detect
bits : 2 - 2 (1 bit)
access : read-write

FRI : Frame-list Rollover
bits : 3 - 3 (1 bit)
access : read-write

SEI : System Error
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Error

End of enumeration elements list.

AAI : Interrupt on Async Advance
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No async advance interrupt

#1 : 1

Async advance interrupt

End of enumeration elements list.

URI : USB Reset received
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset received

#1 : 1

Reset received

End of enumeration elements list.

SRI : SOF Received
bits : 7 - 7 (1 bit)
access : read-write

SLI : Device-controller suspend
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Active

#1 : 1

Suspended

End of enumeration elements list.

RESERVED : Reserved
bits : 9 - 9 (1 bit)
access : read-only

ULPII : ULPI Interrupt
bits : 10 - 10 (1 bit)
access : read-only

RESERVED : Reserved
bits : 11 - 11 (1 bit)
access : read-only

HCH : Host Controller Halted
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

#0 : 0

Running

#1 : 1

Halted

End of enumeration elements list.

RCL : Reclamation
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

#0 : 0

Non-empty asynchronous schedule

#1 : 1

Empty asynchronous schedule

End of enumeration elements list.

PS : Periodic schedule Status
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

AS : Asynchronous schedule Status
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

NAKI : NAK Interrupt
bits : 16 - 16 (1 bit)
access : read-only

RESERVED : Reserved
bits : 17 - 17 (1 bit)
access : read-only

UAI : USB host Asynchronous Interrupt
bits : 18 - 18 (1 bit)
access : read-write

UPI : USB host Periodic Interrupt
bits : 19 - 19 (1 bit)
access : read-write

RESERVED : Reserved
bits : 20 - 23 (4 bit)
access : read-only

TI0 : General purpose Timer 0 Interrupt
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt

#1 : 1

Interrupt occurred

End of enumeration elements list.

TI1 : General purpose Timer 1 Interrupt
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt

#1 : 1

Interrupt occurred

End of enumeration elements list.

RESERVED : Reserved
bits : 26 - 31 (6 bit)
access : read-only


USBINTR

USB Interrupt Enable Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBINTR USBINTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UE UEE PCE FRE SEE AAE URE SRE SLE RESERVED ULPIE RESERVED NAKE RESERVED UAIE UPIE RESERVED TIE0 TIE1 RESERVED

UE : USB interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

UEE : USB Error interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

PCE : Port Change detect Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

FRE : Frame list Rollover Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

SEE : System Error Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

AAE : Interrupt on Async advance Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

URE : USB-Reset Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

SRE : SOF-Received Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

SLE : Sleep (DC suspend) Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 9 - 9 (1 bit)
access : read-only

ULPIE : ULPI Enable
bits : 10 - 10 (1 bit)
access : read-write

RESERVED : Reserved
bits : 11 - 15 (5 bit)
access : read-only

NAKE : NAK Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 17 (1 bit)
access : read-only

UAIE : USB host Asynchronous Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write

UPIE : USB host Periodic Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write

RESERVED : Reserved
bits : 20 - 23 (4 bit)
access : read-only

TIE0 : General purpose Timer 0 Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

TIE1 : General purpose Timer 1 Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 26 - 31 (6 bit)
access : read-only


FRINDEX

Frame Index Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRINDEX FRINDEX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRINDEX Reerved

FRINDEX : Frame Index
bits : 0 - 13 (14 bit)
access : read-write

Reerved : Reserved
bits : 14 - 31 (18 bit)
access : read-only


DEVICEADDR

Device Address Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : USBHS
reset_Mask : 0x0

DEVICEADDR DEVICEADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED USBADRA USBADR

RESERVED : Reserved
bits : 0 - 23 (24 bit)
access : read-only

USBADRA : Device Address Advance
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to USBADR are instantaneous.

#1 : 1

When this bit is written to a 1 at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR is loaded from the holding register.

End of enumeration elements list.

USBADR : Device Address
bits : 25 - 31 (7 bit)
access : read-write


PERIODICLISTBASE

Periodic Frame List Base Address Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : USBHS
reset_Mask : 0x0

PERIODICLISTBASE PERIODICLISTBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED PERBASE

RESERVED : Reserved
bits : 0 - 11 (12 bit)
access : read-only

PERBASE : Base address
bits : 12 - 31 (20 bit)
access : read-write


ASYNCLISTADDR

Current Asynchronous List Address Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : USBHS
reset_Mask : 0x0

ASYNCLISTADDR ASYNCLISTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ASYBASE

RESERVED : Reserved
bits : 0 - 4 (5 bit)
access : read-only

ASYBASE : Link pointer low (LPL)
bits : 5 - 31 (27 bit)
access : read-write


EPLISTADDR

Endpoint List Address Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : USBHS
reset_Mask : 0x0

EPLISTADDR EPLISTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED EPBASE

RESERVED : Reserved
bits : 0 - 10 (11 bit)
access : read-only

EPBASE : Endpoint list address
bits : 11 - 31 (21 bit)
access : read-write


TTCTRL

Host TT Asynchronous Buffer Control
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TTCTRL TTCTRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED TTHA Reerved

RESERVED : Reserved
bits : 0 - 23 (24 bit)
access : read-only

TTHA : TT Hub Address
bits : 24 - 30 (7 bit)
access : read-only

Reerved : Reserved
bits : 31 - 31 (1 bit)
access : read-only


BURSTSIZE

Master Interface Data Burst Size Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BURSTSIZE BURSTSIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPBURST TXPBURST RESERVED

RXPBURST : Programable RX Burst length
bits : 0 - 7 (8 bit)
access : read-write

TXPBURST : Programable TX Burst length
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : Reserved
bits : 16 - 31 (16 bit)
access : read-only


TXFILLTUNING

Transmit FIFO Tuning Control Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFILLTUNING TXFILLTUNING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXSCHOH RESERVED TXSCHHEALTH RESERVED TXFIFOTHRES RESERVED

TXSCHOH : Scheduler Overhead
bits : 0 - 6 (7 bit)
access : read-write

RESERVED : Reserved
bits : 7 - 7 (1 bit)
access : read-only

TXSCHHEALTH : Scheduler Health counter
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : Reserved
bits : 13 - 15 (3 bit)
access : read-only

TXFIFOTHRES : FIFO burst Threshold
bits : 16 - 21 (6 bit)
access : read-write

RESERVED : Reserved
bits : 22 - 31 (10 bit)
access : read-only


ULPI_VIEWPORT

ULPI Register Access
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ULPI_VIEWPORT ULPI_VIEWPORT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULPI_DATWR ULPI_DATRD ULPI_ADDR ULPI_PORT ULPI_SS RESERVED ULPI_RW ULPI_RUN ULPI_WU

ULPI_DATWR : ULPI Data Write
bits : 0 - 7 (8 bit)
access : read-write

ULPI_DATRD : ULPI Data Read
bits : 8 - 15 (8 bit)
access : read-only

ULPI_ADDR : ULPI data Address
bits : 16 - 23 (8 bit)
access : read-write

ULPI_PORT : ULPI Port number
bits : 24 - 26 (3 bit)
access : read-write

ULPI_SS : ULPI Sync State
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Any other state (that is, carkit, serial, low power)

#1 : 1

Normal sync state

End of enumeration elements list.

RESERVED : Reserved
bits : 28 - 28 (1 bit)
access : read-only

ULPI_RW : ULPI Read/Write
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Read

#1 : 1

Write

End of enumeration elements list.

ULPI_RUN : ULPI Run
bits : 30 - 30 (1 bit)
access : read-write

ULPI_WU : ULPI Wake-Up
bits : 31 - 31 (1 bit)
access : read-write


ENDPTNAK

Endpoint NAK Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTNAK ENDPTNAK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPRN RESERVED EPTN RESERVED

EPRN : RX Endpoint NAK
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : Reserved
bits : 4 - 15 (12 bit)
access : read-only

EPTN : TX Endpoint NAK
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : Reserved
bits : 20 - 31 (12 bit)
access : read-only


ENDPTNAKEN

Endpoint NAK Enable Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTNAKEN ENDPTNAKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPRNE RESERVED EPTNE RESERVED

EPRNE : RX Endpoint NAK
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : Reserved
bits : 4 - 15 (12 bit)
access : read-only

EPTNE : TX Endpoint NAK
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : Reserved
bits : 20 - 31 (12 bit)
access : read-only


CONFIGFLAG

Configure Flag Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CONFIGFLAG CONFIGFLAG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED

RESERVED : Reserved
bits : 0 - 0 (1 bit)
access : read-only

RESERVED : Reserved
bits : 1 - 31 (31 bit)
access : read-only


PORTSC1

Port Status and Control Registers
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORTSC1 PORTSC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCS CSC PE PEC OCA OCC FPR SUSP PR HSP LS PP PO PIC PTC WKCN WKDS WKOC PHCD PFSC RESERVED PSPD RESERVED RESERVED PTS

CCS : Current Connect Status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

No device present (host mode) or attached (device mode)

#1 : 1

Device is present (host mode) or attached (device mode)

End of enumeration elements list.

CSC : Connect Change Status
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No change

#1 : 1

Connect status has changed

End of enumeration elements list.

PE : Port Enabled/disabled
bits : 2 - 2 (1 bit)
access : read-write

PEC : Port Enable/disable Change
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No change

#1 : 1

Port disabled

End of enumeration elements list.

OCA : Over-current active
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Port not in over-current condition

#1 : 1

Port currently in over-current condition

End of enumeration elements list.

OCC : Over-Current Change
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No over-current

#1 : 1

Over-current detect

End of enumeration elements list.

FPR : Force Port Resume
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No resume (K-state) detected/driven on port

#1 : 1

Resume detected/driven on port

End of enumeration elements list.

SUSP : Suspend
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port not in suspend state

#1 : 1

Port in suspend state

End of enumeration elements list.

PR : Port Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port is not in reset

#1 : 1

Port is in reset

End of enumeration elements list.

HSP : High Speed Port.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

FS or LS

#1 : 1

HS

End of enumeration elements list.

LS : Line Status
bits : 10 - 11 (2 bit)
access : read-only

Enumeration:

#00 : 00

SE0

#01 : 01

J-state

#10 : 10

K-state

#11 : 11

Undefined

End of enumeration elements list.

PP : Port Power
bits : 12 - 12 (1 bit)
access : read-write

PO : Port Owner
bits : 13 - 13 (1 bit)
access : read-write

PIC : Port Indicator Control
bits : 14 - 15 (2 bit)
access : read-write

PTC : Port Test Control
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Not enabled

#0001 : 0001

J_STATE

#0010 : 0010

K_STATE

#0011 : 0011

SEQ_NAK

#0100 : 0100

Packet

#0101 : 0101

FORCE_ENABLE_HS

#0110 : 0110

FORCE_ENABLE_FS

#0111 : 0111

FORCE_ENABLE_LS

End of enumeration elements list.

WKCN : Wake on Connect enable
bits : 20 - 20 (1 bit)
access : read-write

WKDS : Wake on Disconnect enable
bits : 21 - 21 (1 bit)
access : read-write

WKOC : Wake on Over-Current enable
bits : 22 - 22 (1 bit)
access : read-write

PHCD : PHY low power suspend
bits : 23 - 23 (1 bit)
access : read-write

PFSC : Port force Full-Speed Connect
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Allow the port to identify itself as high speed

#1 : 1

Force the port to only connect at full speed

End of enumeration elements list.

RESERVED : Reserved
bits : 25 - 25 (1 bit)
access : read-only

PSPD : Port Speed
bits : 26 - 27 (2 bit)
access : read-only

Enumeration:

#00 : 00

Full speed

#01 : 01

Low speed

#10 : 10

High speed

#11 : 11

Undefined

End of enumeration elements list.

RESERVED : Reserved
bits : 28 - 28 (1 bit)
access : read-only

RESERVED : Reserved
bits : 29 - 29 (1 bit)
access : read-only

PTS : Port Transceiver Select
bits : 30 - 31 (2 bit)
access : read-write


GPTIMER1LD

General Purpose Timer n Load Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER1LD GPTIMER1LD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTLD RESERVED

GPTLD : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : Reserved
bits : 24 - 31 (8 bit)
access : read-only


GPTIMER1CTL

General Purpose Timer n Control Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER1CTL GPTIMER1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTCNT MODE RESERVED RST RUN

GPTCNT : Timer Count
bits : 0 - 23 (24 bit)
access : read-only

MODE : Timer Mode
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

One shot

#1 : 1

Repeat

End of enumeration elements list.

RESERVED : Reserved
bits : 25 - 29 (5 bit)
access : read-only

RST : Timer Reset
bits : 30 - 30 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Load counter value

End of enumeration elements list.

RUN : Timer Run
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer stop

#1 : 1

Timer run

End of enumeration elements list.


OTGSC

On-the-Go Status and Control Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTGSC OTGSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VD VC HAAR OT DP IDPU RESERVED HABA ID AVV ASV BSV BSE MST DPS RESERVED IDIS AVVIS ASVIS BSVIS BSEIS MSS DPIS RESERVED IDIE AVVIE ASVIE BSVIE BSEIE MSE DPIE RESERVED

VD : VBUS Discharge
bits : 0 - 0 (1 bit)
access : read-write

VC : VBUS Charge
bits : 1 - 1 (1 bit)
access : read-write

HAAR : Hardware Assist Auto-Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled.

#1 : 1

Enable automatic reset after connect on host port.

End of enumeration elements list.

OT : OTG Termination
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable pull-down on DM

#1 : 1

Enable pull-down on DM

End of enumeration elements list.

DP : Data Pulsing
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The pull-up on DP is not asserted

#1 : 1

The pull-up on DP is asserted for data pulsing during SRP

End of enumeration elements list.

IDPU : ID Pull-Up
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable pull-up. ID input not sampled.

#1 : 1

Enable pull-up

End of enumeration elements list.

RESERVED : Reserved
bits : 6 - 6 (1 bit)
access : read-only

HABA : Hardware Assist B-Disconnect to A-connect
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled.

#1 : 1

Enable automatic B-disconnect to A-connect sequence.

End of enumeration elements list.

ID : USB ID
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

A device

#1 : 1

B device

End of enumeration elements list.

AVV : A VBus Valid
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

VBus is below A VBus valid threshold

#1 : 1

VBus is above A VBus valid threshold

End of enumeration elements list.

ASV : A Session Valid
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

#0 : 0

VBus is below A session valid threshold

#1 : 1

VBus is above A session valid threshold

End of enumeration elements list.

BSV : B Session Valid
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

#0 : 0

VBus is below B session valid threshold

#1 : 1

VBus is above B session valid threshold

End of enumeration elements list.

BSE : B Session End
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

#0 : 0

VBus is above B session end threshold

#1 : 1

VBus is below B session end threshold

End of enumeration elements list.

MST : 1 Milli-Second timer Toggle
bits : 13 - 13 (1 bit)
access : read-only

DPS : Data bus Pulsing Status
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#0 : 0

No pulsing on port

#1 : 1

Pulsing detected on port

End of enumeration elements list.

RESERVED : Reserved
bits : 15 - 15 (1 bit)
access : read-only

IDIS : USB ID Interrupt Status
bits : 16 - 16 (1 bit)
access : read-write

AVVIS : A VBUS Valid Interrupt Status
bits : 17 - 17 (1 bit)
access : read-write

ASVIS : A Session Valid Interrupt Status
bits : 18 - 18 (1 bit)
access : read-write

BSVIS : B Session Valid Interrupt Status
bits : 19 - 19 (1 bit)
access : read-write

BSEIS : B Session End Interrupt Status
bits : 20 - 20 (1 bit)
access : read-write

MSS : 1 Milli-Second timer interrupt Status
bits : 21 - 21 (1 bit)
access : read-write

DPIS : Data Pulse interrupt Status
bits : 22 - 22 (1 bit)
access : read-write

RESERVED : Reserved
bits : 23 - 23 (1 bit)
access : read-only

IDIE : USB ID Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

AVVIE : A VBUS Valid Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

ASVIE : A Session Valid Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

BSVIE : B Session Valid Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

BSEIE : B Session End Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

MSE : 1 Milli-Second timer interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

DPIE : Data Pulse Interrupt Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : Reserved
bits : 31 - 31 (1 bit)
access : read-only


USBMODE

USB Mode Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBMODE USBMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM ES SLOM SDIS RESERVED TXHSD RESERVED

CM : Controller Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Idle (default for the USBHS module)

#10 : 10

Device controller

#11 : 11

Host controller

#01 : 01

Reserved

End of enumeration elements list.

ES : Endian Select
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Little endian. First byte referenced in least significant byte of 32-bit word.

#1 : 1

Big endian. First byte referenced in most significant byte of 32-bit word.

End of enumeration elements list.

SLOM : Setup Lock-Out Mode
bits : 3 - 3 (1 bit)
access : read-write

SDIS : Stream DISable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inactive

#1 : 1

Active

End of enumeration elements list.

RESERVED : Reserved
bits : 5 - 11 (7 bit)
access : read-only

TXHSD : Tx to Tx HS Delay
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 000

10

#001 : 001

11

#010 : 010

12

#011 : 011

13

#100 : 100

14

#101 : 101

15

#110 : 110

16

#111 : 111

17

End of enumeration elements list.

RESERVED : Reserved
bits : 15 - 31 (17 bit)
access : read-only


EPSETUPSR

Endpoint Setup Status Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPSETUPSR EPSETUPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPSETUPSTAT RESERVED

EPSETUPSTAT : Setup Endpoint Status
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : Reserved
bits : 4 - 31 (28 bit)
access : read-only


EPPRIME

Endpoint Initialization Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPPRIME EPPRIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERB RESERVED PETB RESERVED

PERB : Prime Endpoint Receive Buffer
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : Reserved
bits : 4 - 15 (12 bit)
access : read-only

PETB : Prime Endpoint tTansmit Buffer
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : Reserved
bits : 20 - 31 (12 bit)
access : read-only


EPFLUSH

Endpoint Flush Register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFLUSH EPFLUSH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FERB RESERVED FETB RESERVED

FERB : Flush Endpoint Receive Buffer
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : Reserved
bits : 4 - 15 (12 bit)
access : read-only

FETB : Flush Endpoint Transmit Buffer
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : Reserved
bits : 20 - 31 (12 bit)
access : read-only


EPSR

Endpoint Status Register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPSR EPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERBR RESERVED ETBR RESERVED

ERBR : Endpoint Receive Buffer Ready
bits : 0 - 3 (4 bit)
access : read-only

RESERVED : Reserved
bits : 4 - 15 (12 bit)
access : read-only

ETBR : Endpoint Transmit Buffer Ready
bits : 16 - 19 (4 bit)
access : read-only

RESERVED : Reserved
bits : 20 - 31 (12 bit)
access : read-only


EPCOMPLETE

Endpoint Complete Register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCOMPLETE EPCOMPLETE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERCE RESERVED ETCE RESERVED

ERCE : Endpoint Receive Complete Event
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : Reserved
bits : 4 - 15 (12 bit)
access : read-only

ETCE : Endpoint Transmit Complete Event
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : Reserved
bits : 20 - 31 (12 bit)
access : read-only


EPCR0

Endpoint Control Register 0
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCR0 EPCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RESERVED RXT RESERVED RXE RESERVED TXS RESERVED TXT RESERVED TXE RESERVED

RXS : RX endpoint Stall
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Endpoint OK

#1 : 1

Endpoint stalled

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 1 (1 bit)
access : read-only

RXT : RX endpoint Type
bits : 2 - 3 (2 bit)
access : read-only

Enumeration:

#00 : 00

Control

End of enumeration elements list.

RESERVED : Reserved
bits : 4 - 6 (3 bit)
access : read-only

RXE : RX endpoint Enable
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 8 - 15 (8 bit)
access : read-only

TXS : TX Endpoint Stall
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Endpoint OK

#1 : 1

Endpoint stalled

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 17 (1 bit)
access : read-only

TXT : TX Endpoint Type
bits : 18 - 19 (2 bit)
access : read-only

Enumeration:

#00 : 00

Control

End of enumeration elements list.

RESERVED : Reserved
bits : 20 - 22 (3 bit)
access : read-only

TXE : TX Endpoint Enable
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

#1 : 1

Enable

End of enumeration elements list.

RESERVED : This register is not defined in the EHCI specification. Every device implements endpoint 0 as a control endpoint.
bits : 24 - 31 (8 bit)
access : read-only


USBGENCTRL

USB General Control Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBGENCTRL USBGENCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WU_IE WU_ULPI_EN RESERVED WU_INT_CLR RESERVED

WU_IE : Wakeup Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

WU_ULPI_EN : Wakeup on ULPI Interrupt Event
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 2 - 4 (3 bit)
access : read-write

WU_INT_CLR : Wakeup Interrupt Clear
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Default, no action.

#1 : 1

Clear the wake-up interrupt.

End of enumeration elements list.

RESERVED : Reserved
bits : 6 - 31 (26 bit)
access : read-only


EPCR1

Endpoint Control Register n
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCR1 EPCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RESERVED RXI RXR RXE RESERVED TXS TXD TXT RESERVED TXI TXR TXE RESERVED

RXS : RX endpoint Stall
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Endpoint OK

#1 : 1

Endpoint stalled

End of enumeration elements list.

RXD : RX endpoint Data sink
bits : 1 - 1 (1 bit)
access : read-write

RXT : RX endpoint Type
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Control

#01 : 01

Isochronous

#10 : 10

Bulk

#11 : 11

Interrupt

End of enumeration elements list.

RESERVED : Reserved
bits : 4 - 4 (1 bit)
access : read-only

RXI : RX data toggle Inhibit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PID sequencing enabled

#1 : 1

PID sequencing disabled

End of enumeration elements list.

RXR : RX data toggle Reset
bits : 6 - 6 (1 bit)
access : write-only

RXE : RX endpoint Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 8 - 15 (8 bit)
access : read-only

TXS : TX endpoint Stall
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Endpoint OK

#1 : 1

Endpoint stalled

End of enumeration elements list.

TXD : TX endpoint Data source
bits : 17 - 17 (1 bit)
access : read-write

TXT : TX endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 00

Control

#01 : 01

Isochronous

#10 : 10

Bulk

#11 : 11

Interrupt

End of enumeration elements list.

RESERVED : Reserved
bits : 20 - 20 (1 bit)
access : read-only

TXI : TX data toggle Inhibit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PID sequencing enabled

#1 : 1

PID sequencing disabled

End of enumeration elements list.

TXR : TX data toggle Reset
bits : 22 - 22 (1 bit)
access : write-only

TXE : TX endpoint Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 24 - 31 (8 bit)
access : read-only


HWGENERAL

General Hardware Parameters Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWGENERAL HWGENERAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED RESERVED RESERVED PHYM SM RESERVED

RESERVED : Reserved
bits : 0 - 0 (1 bit)
access : read-only

RESERVED : Reserved
bits : 1 - 1 (1 bit)
access : read-only

RESERVED : Reserved
bits : 2 - 2 (1 bit)
access : read-only

RESERVED : Reserved
bits : 3 - 5 (3 bit)
access : read-only

PHYM : PHY Mode
bits : 6 - 8 (3 bit)
access : read-only

SM : Serial mode
bits : 9 - 10 (2 bit)
access : read-only

RESERVED : Reserved
bits : 11 - 31 (21 bit)
access : read-only


EPCR2

Endpoint Control Register n
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCR2 EPCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RESERVED RXI RXR RXE RESERVED TXS TXD TXT RESERVED TXI TXR TXE RESERVED

RXS : RX endpoint Stall
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Endpoint OK

#1 : 1

Endpoint stalled

End of enumeration elements list.

RXD : RX endpoint Data sink
bits : 1 - 1 (1 bit)
access : read-write

RXT : RX endpoint Type
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Control

#01 : 01

Isochronous

#10 : 10

Bulk

#11 : 11

Interrupt

End of enumeration elements list.

RESERVED : Reserved
bits : 4 - 4 (1 bit)
access : read-only

RXI : RX data toggle Inhibit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PID sequencing enabled

#1 : 1

PID sequencing disabled

End of enumeration elements list.

RXR : RX data toggle Reset
bits : 6 - 6 (1 bit)
access : write-only

RXE : RX endpoint Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 8 - 15 (8 bit)
access : read-only

TXS : TX endpoint Stall
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Endpoint OK

#1 : 1

Endpoint stalled

End of enumeration elements list.

TXD : TX endpoint Data source
bits : 17 - 17 (1 bit)
access : read-write

TXT : TX endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 00

Control

#01 : 01

Isochronous

#10 : 10

Bulk

#11 : 11

Interrupt

End of enumeration elements list.

RESERVED : Reserved
bits : 20 - 20 (1 bit)
access : read-only

TXI : TX data toggle Inhibit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PID sequencing enabled

#1 : 1

PID sequencing disabled

End of enumeration elements list.

TXR : TX data toggle Reset
bits : 22 - 22 (1 bit)
access : write-only

TXE : TX endpoint Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 24 - 31 (8 bit)
access : read-only


EPCR3

Endpoint Control Register n
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCR3 EPCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RESERVED RXI RXR RXE RESERVED TXS TXD TXT RESERVED TXI TXR TXE RESERVED

RXS : RX endpoint Stall
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Endpoint OK

#1 : 1

Endpoint stalled

End of enumeration elements list.

RXD : RX endpoint Data sink
bits : 1 - 1 (1 bit)
access : read-write

RXT : RX endpoint Type
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Control

#01 : 01

Isochronous

#10 : 10

Bulk

#11 : 11

Interrupt

End of enumeration elements list.

RESERVED : Reserved
bits : 4 - 4 (1 bit)
access : read-only

RXI : RX data toggle Inhibit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PID sequencing enabled

#1 : 1

PID sequencing disabled

End of enumeration elements list.

RXR : RX data toggle Reset
bits : 6 - 6 (1 bit)
access : write-only

RXE : RX endpoint Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 8 - 15 (8 bit)
access : read-only

TXS : TX endpoint Stall
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Endpoint OK

#1 : 1

Endpoint stalled

End of enumeration elements list.

TXD : TX endpoint Data source
bits : 17 - 17 (1 bit)
access : read-write

TXT : TX endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 00

Control

#01 : 01

Isochronous

#10 : 10

Bulk

#11 : 11

Interrupt

End of enumeration elements list.

RESERVED : Reserved
bits : 20 - 20 (1 bit)
access : read-only

TXI : TX data toggle Inhibit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PID sequencing enabled

#1 : 1

PID sequencing disabled

End of enumeration elements list.

TXR : TX data toggle Reset
bits : 22 - 22 (1 bit)
access : write-only

TXE : TX endpoint Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 24 - 31 (8 bit)
access : read-only


HWHOST

Host Hardware Parameters Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWHOST HWHOST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HC NPORT RESERVED TTASY TTPER

HC : Host Capable
bits : 0 - 0 (1 bit)
access : read-only

NPORT : Number of Ports
bits : 1 - 3 (3 bit)
access : read-only

RESERVED : Reserved
bits : 4 - 15 (12 bit)
access : read-only

TTASY : Transaction translator contexts.
bits : 16 - 23 (8 bit)
access : read-only

TTPER : Transaction translator periodic contexts.
bits : 24 - 31 (8 bit)
access : read-only


USB_SBUSCFG

System Bus Interface Configuration Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB_SBUSCFG USB_SBUSCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BURSTMODE RESERVED

BURSTMODE : Burst mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

INCR burst of unspecified length

#001 : 001

INCR4, non-multiple transfers of INCR4 is decomposed into singles.

#010 : 010

INCR8, non-multiple transfers of INCR8, is decomposed into INCR4 or singles.

#011 : 011

INCR16, non-multiple transfers of INCR16, is decomposed into INCR8, INCR4 or singles.

#100 : 100

Reserved, do not use.

#101 : 101

INCR4, non-multiple transfers of INCR4 is decomposed into smaller unspecified length bursts.

#110 : 110

INCR8, non-multiple transfers of INCR8 is decomposed into smaller unspecified length bursts.

#111 : 111

INCR16, non-multiple transfers of INCR16 is decomposed into smaller unspecified length bursts.

End of enumeration elements list.

RESERVED : Reserved
bits : 3 - 31 (29 bit)
access : read-only


HWDEVICE

Device Hardware Parameters Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWDEVICE HWDEVICE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DC DEVEP RESERVED

DC : Device Capable
bits : 0 - 0 (1 bit)
access : read-only

DEVEP : Device endpoints.
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : Reserved
bits : 6 - 31 (26 bit)
access : read-only



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