Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1A4 byte (0x0)
mem_usage : registers
protection : not protected
Status and Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDOK : Load OK
bits : 0 - 0 (1 bit)
access : read-write
CONT : Continuous Mode Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB operation in One-Shot mode
#1 : 1
PDB operation in Continuous mode
End of enumeration elements list.
MULT : Multiplication Factor Select for Prescaler
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Multiplication factor is 1
#01 : 01
Multiplication factor is 10
#10 : 10
Multiplication factor is 20
#11 : 11
Multiplication factor is 40
End of enumeration elements list.
RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only
PDBIE : PDB Interrupt Enable.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB interrupt disabled
#1 : 1
PDB interrupt enabled
End of enumeration elements list.
PDBIF : PDB Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write
PDBEN : PDB Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB disabled. Counter is off.
#1 : 1
PDB enabled
End of enumeration elements list.
TRGSEL : Trigger Input Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Trigger-In 0 is selected
#0001 : 0001
Trigger-In 1 is selected
#0010 : 0010
Trigger-In 2 is selected
#0011 : 0011
Trigger-In 3 is selected
#0100 : 0100
Trigger-In 4 is selected
#0101 : 0101
Trigger-In 5 is selected
#0110 : 0110
Trigger-In 6 is selected
#0111 : 0111
Trigger-In 7 is selected
#1000 : 1000
Trigger-In 8 is selected
#1001 : 1001
Trigger-In 9 is selected
#1010 : 1010
Trigger-In 10 is selected
#1011 : 1011
Trigger-In 11 is selected
#1100 : 1100
Trigger-In 12 is selected
#1101 : 1101
Trigger-In 13 is selected
#1110 : 1110
Trigger-In 14 is selected
#1111 : 1111
Software trigger is selected
End of enumeration elements list.
PRESCALER : Prescaler Divider Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 000
Counting uses the peripheral clock divided by multiplication factor selected by MULT.
#001 : 001
Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.
#010 : 010
Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.
#011 : 011
Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.
#100 : 100
Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.
#101 : 101
Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.
#110 : 110
Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.
#111 : 111
Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.
End of enumeration elements list.
DMAEN : DMA Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA disabled
#1 : 1
DMA enabled
End of enumeration elements list.
SWTRIG : Software Trigger
bits : 16 - 16 (1 bit)
access : write-only
PDBEIE : PDB Sequence Error Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB sequence error interrupt disabled.
#1 : 1
PDB sequence error interrupt enabled.
End of enumeration elements list.
LDMOD : Load Mode Select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.
#01 : 01
The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.
#10 : 10
The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.
#11 : 11
The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 31 (12 bit)
access : read-only
Channel n Control Register 1
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : PDB Channel Pre-Trigger Enable
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger disabled.
#1 : 1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
TOS : PDB Channel Pre-Trigger Output Select
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
#1 : 1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
End of enumeration elements list.
BB : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
#1 : 1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Channel n Status Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR : PDB Channel Sequence Error Flags
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#0 : 0
Sequence error not detected on PDB channel's corresponding pre-trigger.
#1 : 1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags.
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only
CF : PDB Channel Flags
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Channel n Delay 0 Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Channel n Delay 1 Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Pulse-Out n Enable Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POEN : PDB Pulse-Out Enable
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB Pulse-Out disabled
#1 : 1
PDB Pulse-Out enabled
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only
Channel n Control Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : PDB Channel Pre-Trigger Enable
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger disabled.
#1 : 1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
TOS : PDB Channel Pre-Trigger Output Select
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
#1 : 1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
End of enumeration elements list.
BB : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
#1 : 1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Channel n Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR : PDB Channel Sequence Error Flags
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#0 : 0
Sequence error not detected on PDB channel's corresponding pre-trigger.
#1 : 1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags.
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only
CF : PDB Channel Flags
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
DAC Interval Trigger n Control Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOE : DAC Interval Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC interval trigger disabled.
#1 : 1
DAC interval trigger enabled.
End of enumeration elements list.
EXT : DAC External Trigger Input Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
#1 : 1
DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 31 (30 bit)
access : read-only
DAC Interval n Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : DAC Interval
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Channel n Delay 0 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Pulse-Out n Delay Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY2 : PDB Pulse-Out Delay 2
bits : 0 - 15 (16 bit)
access : read-write
DLY1 : PDB Pulse-Out Delay 1
bits : 16 - 31 (16 bit)
access : read-write
Channel n Delay 1 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
DAC Interval Trigger n Control Register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOE : DAC Interval Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC interval trigger disabled.
#1 : 1
DAC interval trigger enabled.
End of enumeration elements list.
EXT : DAC External Trigger Input Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
#1 : 1
DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 31 (30 bit)
access : read-only
Modulus Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD : PDB Modulus.
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
DAC Interval n Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : DAC Interval
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Pulse-Out n Delay Register
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY2 : PDB Pulse-Out Delay 2
bits : 0 - 15 (16 bit)
access : read-write
DLY1 : PDB Pulse-Out Delay 1
bits : 16 - 31 (16 bit)
access : read-write
Channel n Control Register 1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : PDB Channel Pre-Trigger Enable
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger disabled.
#1 : 1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
TOS : PDB Channel Pre-Trigger Output Select
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
#1 : 1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
End of enumeration elements list.
BB : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
#1 : 1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Channel n Status Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR : PDB Channel Sequence Error Flags
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#0 : 0
Sequence error not detected on PDB channel's corresponding pre-trigger.
#1 : 1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags.
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only
CF : PDB Channel Flags
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Pulse-Out n Delay Register
address_offset : 0x65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY2 : PDB Pulse-Out Delay 2
bits : 0 - 15 (16 bit)
access : read-write
DLY1 : PDB Pulse-Out Delay 1
bits : 16 - 31 (16 bit)
access : read-write
Channel n Delay 0 Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Channel n Delay 1 Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Pulse-Out n Delay Register
address_offset : 0x7FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY2 : PDB Pulse-Out Delay 2
bits : 0 - 15 (16 bit)
access : read-write
DLY1 : PDB Pulse-Out Delay 1
bits : 16 - 31 (16 bit)
access : read-write
Counter Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : PDB Counter
bits : 0 - 15 (16 bit)
access : read-only
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Channel n Control Register 1
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : PDB Channel Pre-Trigger Enable
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger disabled.
#1 : 1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
TOS : PDB Channel Pre-Trigger Output Select
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
#1 : 1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
End of enumeration elements list.
BB : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
#0 : 0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
#1 : 1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Interrupt Delay Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDLY : PDB Interrupt Delay
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Channel n Status Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR : PDB Channel Sequence Error Flags
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#0 : 0
Sequence error not detected on PDB channel's corresponding pre-trigger.
#1 : 1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags.
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only
CF : PDB Channel Flags
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Channel n Delay 0 Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Channel n Delay 1 Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
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