Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x108 byte (0x0)
mem_usage : registers
protection : not protected
SAI Transmit Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRDE : FIFO Request DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
FWDE : FIFO Warning DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 4 (3 bit)
access : read-only
RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only
FRIE : FIFO Request Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FWIE : FIFO Warning Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FEIE : FIFO Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
SEIE : Sync Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
WSIE : Word Start Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only
FRF : FIFO Request Flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO watermark has not been reached.
#1 : 1
Transmit FIFO watermark has been reached.
End of enumeration elements list.
FWF : FIFO Warning Flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
No enabled transmit FIFO is empty.
#1 : 1
Enabled transmit FIFO is empty.
End of enumeration elements list.
FEF : FIFO Error Flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit underrun not detected.
#1 : 1
Transmit underrun detected.
End of enumeration elements list.
SEF : Sync Error Flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sync error not detected.
#1 : 1
Frame sync error detected.
End of enumeration elements list.
WSF : Word Start Flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Start of word not detected.
#1 : 1
Start of word detected.
End of enumeration elements list.
RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only
RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only
SR : Software Reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Software reset.
End of enumeration elements list.
FR : FIFO Reset
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
FIFO reset.
End of enumeration elements list.
BCE : Bit Clock Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit bit clock is disabled.
#1 : 1
Transmit bit clock is enabled.
End of enumeration elements list.
DBGE : Debug Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter is disabled in Debug mode, after completing the current frame.
#1 : 1
Transmitter is enabled in Debug mode.
End of enumeration elements list.
STOPE : Stop Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter disabled in Stop mode.
#1 : 1
Transmitter enabled in Stop mode.
End of enumeration elements list.
TE : Transmitter Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter is disabled.
#1 : 1
Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
End of enumeration elements list.
SAI Transmit Configuration 4 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSD : Frame Sync Direction
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync is generated externally in Slave mode.
#1 : 1
Frame sync is generated internally in Master mode.
End of enumeration elements list.
FSP : Frame Sync Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync is active high.
#1 : 1
Frame sync is active low.
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-only
FSE : Frame Sync Early
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync asserts with the first bit of the frame.
#1 : 1
Frame sync asserts one bit before the first bit of the frame.
End of enumeration elements list.
MF : MSB First
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
LSB is transmitted first.
#1 : 1
MSB is transmitted first.
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only
SYWD : Sync Width
bits : 8 - 12 (5 bit)
access : read-write
RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only
FRSZ : Frame size
bits : 16 - 19 (4 bit)
access : read-write
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only
RESERVED : no description available
bits : 26 - 27 (2 bit)
access : read-only
RESERVED : no description available
bits : 28 - 28 (1 bit)
access : read-only
RESERVED : no description available
bits : 28 - 28 (1 bit)
access : read-only
SAI MCLK Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 23 (24 bit)
access : read-only
RESERVED : no description available
bits : 0 - 23 (24 bit)
access : read-only
MICS : MCLK Input Clock Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
MCLK divider input clock 0 selected.
#01 : 01
MCLK divider input clock 1 selected.
#10 : 10
MCLK divider input clock 2 selected.
#11 : 11
MCLK divider input clock 3 selected.
End of enumeration elements list.
MOE : MCLK Output Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCLK signal pin is configured as an input that bypasses the MCLK divider.
#1 : 1
MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.
End of enumeration elements list.
DUF : Divider Update Flag
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
MCLK divider ratio is not being updated currently.
#1 : 1
MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.
End of enumeration elements list.
SAI MCLK Divide Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDE : MCLK Divide
bits : 0 - 11 (12 bit)
access : read-write
FRACT : MCLK Fraction
bits : 12 - 19 (8 bit)
access : read-write
RESERVED : no description available
bits : 20 - 31 (12 bit)
access : read-only
SAI Transmit Configuration 5 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only
FBT : First Bit Shifted
bits : 8 - 12 (5 bit)
access : read-write
RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only
W0W : Word 0 Width
bits : 16 - 20 (5 bit)
access : read-write
RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only
RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only
WNW : Word N Width
bits : 24 - 28 (5 bit)
access : read-write
SAI Transmit Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
SAI Transmit Configuration 1 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFW : Transmit FIFO Watermark
bits : 0 - 2 (3 bit)
access : read-write
RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-only
SAI Transmit FIFO Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 3 (4 bit)
access : read-only
RESERVED : no description available
bits : 4 - 15 (12 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 19 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 30 (11 bit)
access : read-only
RESERVED : no description available
bits : 20 - 30 (11 bit)
access : read-only
SAI Transmit Mask Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TWM : Transmit Word Mask
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
SAI Transmit Configuration 2 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Bit Clock Divide
bits : 0 - 7 (8 bit)
access : read-write
RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only
BCD : Bit Clock Direction
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit clock is generated externally in Slave mode.
#1 : 1
Bit clock is generated internally in Master mode.
End of enumeration elements list.
BCP : Bit Clock Polarity
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
#1 : 1
Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
End of enumeration elements list.
MSEL : MCLK Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock selected.
#01 : 01
Master Clock (MCLK) 1 option selected.
#10 : 10
Master Clock (MCLK) 2 option selected.
#11 : 11
Master Clock (MCLK) 3 option selected.
End of enumeration elements list.
BCI : Bit Clock Input
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Internal logic is clocked as if bit clock was externally generated.
End of enumeration elements list.
BCS : Bit Clock Swap
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use the normal bit clock source.
#1 : 1
Swap the bit clock source.
End of enumeration elements list.
SYNC : Synchronous Mode
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
Asynchronous mode.
#01 : 01
Synchronous with receiver.
#10 : 10
Synchronous with another SAI transmitter.
#11 : 11
Synchronous with another SAI receiver.
End of enumeration elements list.
SAI Receive Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRDE : FIFO Request DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
FWDE : FIFO Warning DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 4 (3 bit)
access : read-only
RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only
FRIE : FIFO Request Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FWIE : FIFO Warning Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FEIE : FIFO Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
SEIE : Sync Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
WSIE : Word Start Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only
FRF : FIFO Request Flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO watermark not reached.
#1 : 1
Receive FIFO watermark has been reached.
End of enumeration elements list.
FWF : FIFO Warning Flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
No enabled receive FIFO is full.
#1 : 1
Enabled receive FIFO is full.
End of enumeration elements list.
FEF : FIFO Error Flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive overflow not detected.
#1 : 1
Receive overflow detected.
End of enumeration elements list.
SEF : Sync Error Flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sync error not detected.
#1 : 1
Frame sync error detected.
End of enumeration elements list.
WSF : Word Start Flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Start of word not detected.
#1 : 1
Start of word detected.
End of enumeration elements list.
RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only
RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only
SR : Software Reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Software reset.
End of enumeration elements list.
FR : FIFO Reset
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
FIFO reset.
End of enumeration elements list.
BCE : Bit Clock Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive bit clock is disabled.
#1 : 1
Receive bit clock is enabled.
End of enumeration elements list.
DBGE : Debug Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver is disabled in Debug mode, after completing the current frame.
#1 : 1
Receiver is enabled in Debug mode.
End of enumeration elements list.
STOPE : Stop Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver disabled in Stop mode.
#1 : 1
Receiver enabled in Stop mode.
End of enumeration elements list.
RE : Receiver Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver is disabled.
#1 : 1
Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
End of enumeration elements list.
SAI Receive Configuration 1 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFW : Receive FIFO Watermark
bits : 0 - 2 (3 bit)
access : read-write
RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-only
SAI Receive Configuration 2 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Bit Clock Divide
bits : 0 - 7 (8 bit)
access : read-write
RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only
BCD : Bit Clock Direction
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit clock is generated externally in Slave mode.
#1 : 1
Bit clock is generated internally in Master mode.
End of enumeration elements list.
BCP : Bit Clock Polarity
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
#1 : 1
Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
End of enumeration elements list.
MSEL : MCLK Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock selected.
#01 : 01
Master Clock (MCLK) 1 option selected.
#10 : 10
Master Clock (MCLK) 2 option selected.
#11 : 11
Master Clock (MCLK) 3 option selected.
End of enumeration elements list.
BCI : Bit Clock Input
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Internal logic is clocked as if bit clock was externally generated.
End of enumeration elements list.
BCS : Bit Clock Swap
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use the normal bit clock source.
#1 : 1
Swap the bit clock source.
End of enumeration elements list.
SYNC : Synchronous Mode
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
Asynchronous mode.
#01 : 01
Synchronous with transmitter.
#10 : 10
Synchronous with another SAI receiver.
#11 : 11
Synchronous with another SAI transmitter.
End of enumeration elements list.
SAI Receive Configuration 3 Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDFL : Word Flag Configuration
bits : 0 - 3 (4 bit)
access : read-write
RESERVED : no description available
bits : 4 - 15 (12 bit)
access : read-only
RCE : Receive Channel Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive data channel N is disabled.
#1 : 1
Receive data channel N is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only
RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only
SAI Receive Configuration 4 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSD : Frame Sync Direction
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame Sync is generated externally in Slave mode.
#1 : 1
Frame Sync is generated internally in Master mode.
End of enumeration elements list.
FSP : Frame Sync Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync is active high.
#1 : 1
Frame sync is active low.
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-only
FSE : Frame Sync Early
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync asserts with the first bit of the frame.
#1 : 1
Frame sync asserts one bit before the first bit of the frame.
End of enumeration elements list.
MF : MSB First
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
LSB is received first.
#1 : 1
MSB is received first.
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only
SYWD : Sync Width
bits : 8 - 12 (5 bit)
access : read-write
RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only
FRSZ : Frame Size
bits : 16 - 19 (4 bit)
access : read-write
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only
RESERVED : no description available
bits : 26 - 27 (2 bit)
access : read-only
RESERVED : no description available
bits : 28 - 28 (1 bit)
access : read-only
RESERVED : no description available
bits : 28 - 28 (1 bit)
access : read-only
SAI Receive Configuration 5 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only
FBT : First Bit Shifted
bits : 8 - 12 (5 bit)
access : read-write
RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only
W0W : Word 0 Width
bits : 16 - 20 (5 bit)
access : read-write
RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only
RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only
WNW : Word N Width
bits : 24 - 28 (5 bit)
access : read-write
SAI Receive Data Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
SAI Transmit Configuration 3 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDFL : Word Flag Configuration
bits : 0 - 3 (4 bit)
access : read-write
RESERVED : no description available
bits : 4 - 15 (12 bit)
access : read-only
TCE : Transmit Channel Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data channel N is disabled.
#1 : 1
Transmit data channel N is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only
RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only
SAI Receive FIFO Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 3 (4 bit)
access : read-only
RESERVED : no description available
bits : 4 - 14 (11 bit)
access : read-only
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 19 (4 bit)
access : read-only
SAI Receive Mask Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWM : Receive Word Mask
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
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