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PIT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x140 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCR

LDVAL0

CVAL0

TCTRL0

TFLG0

LDVAL1

CVAL1

TCTRL1

TFLG1

LDVAL2

CVAL2

TCTRL2

TFLG2

LDVAL3

CVAL3

TCTRL3

TFLG3


MCR

PIT Module Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRZ MDIS RESERVED RESERVED

FRZ : Freeze
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timers continue to run in Debug mode.

#1 : 1

Timers are stopped in Debug mode.

End of enumeration elements list.

MDIS : Module Disable - (PIT section)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock for standard PIT timers is enabled.

#1 : 1

Clock for standard PIT timers is disabled.

End of enumeration elements list.

RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-only

RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-only


LDVAL0

Timer Load Value Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LDVAL0 LDVAL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSV

TSV : Timer Start Value
bits : 0 - 31 (32 bit)
access : read-write


CVAL0

Current Timer Value Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CVAL0 CVAL0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TVL

TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only


TCTRL0

Timer Control Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCTRL0 TCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TIE CHN RESERVED

TEN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer n is disabled.

#1 : 1

Timer n is enabled.

End of enumeration elements list.

TIE : Timer Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt requests from Timer n are disabled.

#1 : 1

Interrupt will be requested whenever TIF is set.

End of enumeration elements list.

CHN : Chain Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer is not chained.

#1 : 1

Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-only


TFLG0

Timer Flag Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFLG0 TFLG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF RESERVED

TIF : Timer Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timeout has not yet occurred.

#1 : 1

Timeout has occurred.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 31 (31 bit)
access : read-only


LDVAL1

Timer Load Value Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LDVAL1 LDVAL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSV

TSV : Timer Start Value
bits : 0 - 31 (32 bit)
access : read-write


CVAL1

Current Timer Value Register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CVAL1 CVAL1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TVL

TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only


TCTRL1

Timer Control Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCTRL1 TCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TIE CHN RESERVED

TEN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer n is disabled.

#1 : 1

Timer n is enabled.

End of enumeration elements list.

TIE : Timer Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt requests from Timer n are disabled.

#1 : 1

Interrupt will be requested whenever TIF is set.

End of enumeration elements list.

CHN : Chain Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer is not chained.

#1 : 1

Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-only


TFLG1

Timer Flag Register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFLG1 TFLG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF RESERVED

TIF : Timer Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timeout has not yet occurred.

#1 : 1

Timeout has occurred.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 31 (31 bit)
access : read-only


LDVAL2

Timer Load Value Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LDVAL2 LDVAL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSV

TSV : Timer Start Value
bits : 0 - 31 (32 bit)
access : read-write


CVAL2

Current Timer Value Register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CVAL2 CVAL2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TVL

TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only


TCTRL2

Timer Control Register
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCTRL2 TCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TIE CHN RESERVED

TEN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer n is disabled.

#1 : 1

Timer n is enabled.

End of enumeration elements list.

TIE : Timer Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt requests from Timer n are disabled.

#1 : 1

Interrupt will be requested whenever TIF is set.

End of enumeration elements list.

CHN : Chain Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer is not chained.

#1 : 1

Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-only


TFLG2

Timer Flag Register
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFLG2 TFLG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF RESERVED

TIF : Timer Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timeout has not yet occurred.

#1 : 1

Timeout has occurred.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 31 (31 bit)
access : read-only


LDVAL3

Timer Load Value Register
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LDVAL3 LDVAL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSV

TSV : Timer Start Value
bits : 0 - 31 (32 bit)
access : read-write


CVAL3

Current Timer Value Register
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CVAL3 CVAL3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TVL

TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only


TCTRL3

Timer Control Register
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCTRL3 TCTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TIE CHN RESERVED

TEN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer n is disabled.

#1 : 1

Timer n is enabled.

End of enumeration elements list.

TIE : Timer Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt requests from Timer n are disabled.

#1 : 1

Interrupt will be requested whenever TIF is set.

End of enumeration elements list.

CHN : Chain Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer is not chained.

#1 : 1

Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-only


TFLG3

Timer Flag Register
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFLG3 TFLG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF RESERVED

TIF : Timer Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timeout has not yet occurred.

#1 : 1

Timeout has occurred.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 31 (31 bit)
access : read-only



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