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FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x300 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PFAPR

TAGVDW0S0

TAGVDW1S0

TAGVDW2S0

TAGVDW3S0

TAGVDW0S1

TAGVDW1S1

TAGVDW2S1

TAGVDW3S1

PFB0CR

DATAW0S0UM

DATAW0S0MU

TAGVDW0S2

DATAW0S0ML

DATAW0S0LM

TAGVDW1S2

DATAW1S0UM

DATAW1S0MU

TAGVDW2S2

DATAW1S0ML

DATAW1S0LM

TAGVDW3S2

DATAW2S0UM

DATAW2S0MU

DATAW2S0ML

TAGVDW0S3

DATAW2S0LM

TAGVDW1S3

DATAW3S0UM

DATAW3S0MU

DATAW3S0ML

DATAW3S0LM

TAGVDW2S3

TAGVDW3S3

DATAW0S1UM

DATAW0S1MU

DATAW0S1ML

DATAW0S1LM

DATAW1S1UM

DATAW1S1MU

DATAW1S1ML

DATAW1S1LM

DATAW2S1UM

DATAW2S1MU

DATAW2S1ML

DATAW2S1LM

PFB1CR

DATAW0S2UM

DATAW0S2MU

DATAW0S2ML

DATAW3S1UM

DATAW3S1MU

DATAW0S2LM

DATAW3S1ML

DATAW3S1LM

DATAW1S2UM

DATAW1S2MU

DATAW1S2ML

DATAW1S2LM

DATAW2S2UM

DATAW2S2MU

DATAW2S2ML

DATAW0S3UM

DATAW2S2LM

DATAW0S3MU

DATAW0S3ML

DATAW0S3LM

DATAW3S2UM

DATAW3S2MU

DATAW3S2ML

DATAW3S2LM

DATAW1S3UM

DATAW1S3MU

DATAW1S3ML

DATAW1S3LM

DATAW2S3UM

DATAW2S3MU

DATAW2S3ML

DATAW2S3LM

DATAW3S3UM

DATAW3S3MU

DATAW3S3ML

DATAW3S3LM


PFAPR

Flash Access Protection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFAPR PFAPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0AP M1AP M2AP M3AP M4AP M5AP M6AP M7AP M0PFD M1PFD M2PFD M3PFD M4PFD M5PFD M6PFD M7PFD

M0AP : Master 0 Access Protection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M1AP : Master 1 Access Protection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M2AP : Master 2 Access Protection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M3AP : Master 3 Access Protection
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M4AP : Master 4 Access Protection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M5AP : Master 5 Access Protection
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M6AP : Master 6 Access Protection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M7AP : Master 7 Access Protection
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master.

#01 : 01

Only read accesses may be performed by this master.

#10 : 10

Only write accesses may be performed by this master.

#11 : 11

Both read and write accesses may be performed by this master.

End of enumeration elements list.

M0PFD : Master 0 Prefetch Disable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M1PFD : Master 1 Prefetch Disable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M2PFD : Master 2 Prefetch Disable
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M3PFD : Master 3 Prefetch Disable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M4PFD : Master 4 Prefetch Disable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M5PFD : Master 5 Prefetch Disable
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M6PFD : Master 6 Prefetch Disable
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M7PFD : Master 7 Prefetch Disable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.


TAGVDW0S0

Cache Tag Storage
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S0 TAGVDW0S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


TAGVDW1S0

Cache Tag Storage
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S0 TAGVDW1S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


TAGVDW2S0

Cache Tag Storage
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S0 TAGVDW2S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


TAGVDW3S0

Cache Tag Storage
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S0 TAGVDW3S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


TAGVDW0S1

Cache Tag Storage
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S1 TAGVDW0S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


TAGVDW1S1

Cache Tag Storage
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S1 TAGVDW1S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


TAGVDW2S1

Cache Tag Storage
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S1 TAGVDW2S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


TAGVDW3S1

Cache Tag Storage
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S1 TAGVDW3S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


PFB0CR

Flash Bank 0 Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFB0CR PFB0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0SEBE B0IPE B0DPE B0ICE B0DCE CRC B0MW S_B_INV CINV_WAY CLCK_WAY B0RWSC

B0SEBE : Bank 0 Single Entry Buffer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Single entry buffer is disabled.

#1 : 1

Single entry buffer is enabled.

End of enumeration elements list.

B0IPE : Bank 0 Instruction Prefetch Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not prefetch in response to instruction fetches.

#1 : 1

Enable prefetches in response to instruction fetches.

End of enumeration elements list.

B0DPE : Bank 0 Data Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not prefetch in response to data references.

#1 : 1

Enable prefetches in response to data references.

End of enumeration elements list.

B0ICE : Bank 0 Instruction Cache Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not cache instruction fetches.

#1 : 1

Cache instruction fetches.

End of enumeration elements list.

B0DCE : Bank 0 Data Cache Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not cache data references.

#1 : 1

Cache data references.

End of enumeration elements list.

CRC : Cache Replacement Control
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

#000 : 000

LRU replacement algorithm per set across all four ways

#010 : 010

Independent LRU with ways [0-1] for ifetches, [2-3] for data

#011 : 011

Independent LRU with ways [0-2] for ifetches, [3] for data

End of enumeration elements list.

B0MW : Bank 0 Memory Width
bits : 17 - 18 (2 bit)
access : read-only

Enumeration:

#00 : 00

32 bits

#01 : 01

64 bits

#10 : 10

128 bits

End of enumeration elements list.

S_B_INV : Invalidate Prefetch Speculation Buffer
bits : 19 - 19 (1 bit)
access : write-only

Enumeration:

#0 : 0

Speculation buffer and single entry buffer are not affected.

#1 : 1

Invalidate (clear) speculation buffer and single entry buffer.

End of enumeration elements list.

CINV_WAY : Cache Invalidate Way x
bits : 20 - 23 (4 bit)
access : write-only

Enumeration:

#0000 : 0

No cache way invalidation for the corresponding cache

#0001 : 1

Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected

End of enumeration elements list.

CLCK_WAY : Cache Lock Way x
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Cache way is unlocked and may be displaced

#0001 : 1

Cache way is locked and its contents are not displaced

End of enumeration elements list.

B0RWSC : Bank 0 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only


DATAW0S0UM

Cache Data Storage (uppermost word)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S0UM DATAW0S0UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S0MU

Cache Data Storage (mid-upper word)
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S0MU DATAW0S0MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW0S2

Cache Tag Storage
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S2 TAGVDW0S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


DATAW0S0ML

Cache Data Storage (mid-lower word)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S0ML DATAW0S0ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S0LM

Cache Data Storage (lowermost word)
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S0LM DATAW0S0LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW1S2

Cache Tag Storage
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S2 TAGVDW1S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


DATAW1S0UM

Cache Data Storage (uppermost word)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S0UM DATAW1S0UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S0MU

Cache Data Storage (mid-upper word)
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S0MU DATAW1S0MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW2S2

Cache Tag Storage
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S2 TAGVDW2S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


DATAW1S0ML

Cache Data Storage (mid-lower word)
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S0ML DATAW1S0ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S0LM

Cache Data Storage (lowermost word)
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S0LM DATAW1S0LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW3S2

Cache Tag Storage
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S2 TAGVDW3S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


DATAW2S0UM

Cache Data Storage (uppermost word)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S0UM DATAW2S0UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S0MU

Cache Data Storage (mid-upper word)
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S0MU DATAW2S0MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S0ML

Cache Data Storage (mid-lower word)
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S0ML DATAW2S0ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW0S3

Cache Tag Storage
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S3 TAGVDW0S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


DATAW2S0LM

Cache Data Storage (lowermost word)
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S0LM DATAW2S0LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW1S3

Cache Tag Storage
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S3 TAGVDW1S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


DATAW3S0UM

Cache Data Storage (uppermost word)
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S0UM DATAW3S0UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S0MU

Cache Data Storage (mid-upper word)
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S0MU DATAW3S0MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S0ML

Cache Data Storage (mid-lower word)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S0ML DATAW3S0ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S0LM

Cache Data Storage (lowermost word)
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S0LM DATAW3S0LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW2S3

Cache Tag Storage
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S3 TAGVDW2S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


TAGVDW3S3

Cache Tag Storage
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S3 TAGVDW3S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid cache_tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write


DATAW0S1UM

Cache Data Storage (uppermost word)
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S1UM DATAW0S1UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S1MU

Cache Data Storage (mid-upper word)
address_offset : 0x61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S1MU DATAW0S1MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S1ML

Cache Data Storage (mid-lower word)
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S1ML DATAW0S1ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S1LM

Cache Data Storage (lowermost word)
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S1LM DATAW0S1LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S1UM

Cache Data Storage (uppermost word)
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S1UM DATAW1S1UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S1MU

Cache Data Storage (mid-upper word)
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S1MU DATAW1S1MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S1ML

Cache Data Storage (mid-lower word)
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S1ML DATAW1S1ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S1LM

Cache Data Storage (lowermost word)
address_offset : 0x6F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S1LM DATAW1S1LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S1UM

Cache Data Storage (uppermost word)
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S1UM DATAW2S1UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S1MU

Cache Data Storage (mid-upper word)
address_offset : 0x79C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S1MU DATAW2S1MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S1ML

Cache Data Storage (mid-lower word)
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S1ML DATAW2S1ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S1LM

Cache Data Storage (lowermost word)
address_offset : 0x7B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S1LM DATAW2S1LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


PFB1CR

Flash Bank 1 Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFB1CR PFB1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B1SEBE B1IPE B1DPE B1ICE B1DCE B1MW B1RWSC

B1SEBE : Bank 1 Single Entry Buffer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Single entry buffer is disabled.

#1 : 1

Single entry buffer is enabled.

End of enumeration elements list.

B1IPE : Bank 1 Instruction Prefetch Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not prefetch in response to instruction fetches.

#1 : 1

Enable prefetches in response to instruction fetches.

End of enumeration elements list.

B1DPE : Bank 1 Data Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not prefetch in response to data references.

#1 : 1

Enable prefetches in response to data references.

End of enumeration elements list.

B1ICE : Bank 1 Instruction Cache Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not cache instruction fetches.

#1 : 1

Cache instruction fetches.

End of enumeration elements list.

B1DCE : Bank 1 Data Cache Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not cache data references.

#1 : 1

Cache data references.

End of enumeration elements list.

B1MW : Bank 1 Memory Width
bits : 17 - 18 (2 bit)
access : read-only

Enumeration:

#00 : 00

32 bits

#01 : 01

64 bits

#10 : 10

128 bits

End of enumeration elements list.

B1RWSC : Bank 1 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only


DATAW0S2UM

Cache Data Storage (uppermost word)
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S2UM DATAW0S2UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S2MU

Cache Data Storage (mid-upper word)
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S2MU DATAW0S2MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S2ML

Cache Data Storage (mid-lower word)
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S2ML DATAW0S2ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S1UM

Cache Data Storage (uppermost word)
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S1UM DATAW3S1UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S1MU

Cache Data Storage (mid-upper word)
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S1MU DATAW3S1MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S2LM

Cache Data Storage (lowermost word)
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S2LM DATAW0S2LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S1ML

Cache Data Storage (mid-lower word)
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S1ML DATAW3S1ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S1LM

Cache Data Storage (lowermost word)
address_offset : 0x874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S1LM DATAW3S1LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S2UM

Cache Data Storage (uppermost word)
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S2UM DATAW1S2UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S2MU

Cache Data Storage (mid-upper word)
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S2MU DATAW1S2MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S2ML

Cache Data Storage (mid-lower word)
address_offset : 0x950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S2ML DATAW1S2ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S2LM

Cache Data Storage (lowermost word)
address_offset : 0x960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S2LM DATAW1S2LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S2UM

Cache Data Storage (uppermost word)
address_offset : 0xA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S2UM DATAW2S2UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S2MU

Cache Data Storage (mid-upper word)
address_offset : 0xA40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S2MU DATAW2S2MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S2ML

Cache Data Storage (mid-lower word)
address_offset : 0xA50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S2ML DATAW2S2ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S3UM

Cache Data Storage (uppermost word)
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S3UM DATAW0S3UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S2LM

Cache Data Storage (lowermost word)
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S2LM DATAW2S2LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S3MU

Cache Data Storage (mid-upper word)
address_offset : 0xA74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S3MU DATAW0S3MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S3ML

Cache Data Storage (mid-lower word)
address_offset : 0xA88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S3ML DATAW0S3ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S3LM

Cache Data Storage (lowermost word)
address_offset : 0xA9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S3LM DATAW0S3LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S2UM

Cache Data Storage (uppermost word)
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S2UM DATAW3S2UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S2MU

Cache Data Storage (mid-upper word)
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S2MU DATAW3S2MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S2ML

Cache Data Storage (mid-lower word)
address_offset : 0xB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S2ML DATAW3S2ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S2LM

Cache Data Storage (lowermost word)
address_offset : 0xB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S2LM DATAW3S2LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S3UM

Cache Data Storage (uppermost word)
address_offset : 0xBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S3UM DATAW1S3UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S3MU

Cache Data Storage (mid-upper word)
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S3MU DATAW1S3MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S3ML

Cache Data Storage (mid-lower word)
address_offset : 0xBC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S3ML DATAW1S3ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S3LM

Cache Data Storage (lowermost word)
address_offset : 0xBDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S3LM DATAW1S3LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S3UM

Cache Data Storage (uppermost word)
address_offset : 0xCE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S3UM DATAW2S3UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S3MU

Cache Data Storage (mid-upper word)
address_offset : 0xCF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S3MU DATAW2S3MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S3ML

Cache Data Storage (mid-lower word)
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S3ML DATAW2S3ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S3LM

Cache Data Storage (lowermost word)
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S3LM DATAW2S3LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S3UM

Cache Data Storage (uppermost word)
address_offset : 0xE20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S3UM DATAW3S3UM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S3MU

Cache Data Storage (mid-upper word)
address_offset : 0xE34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S3MU DATAW3S3MU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S3ML

Cache Data Storage (mid-lower word)
address_offset : 0xE48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S3ML DATAW3S3ML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S3LM

Cache Data Storage (lowermost word)
address_offset : 0xE5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S3LM DATAW3S3LM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write



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