\n
address_offset : 0x0 Bytes (0x0)
size : 0x70 byte (0x0)
mem_usage : registers
protection : not protected
ADC Status and Control Registers 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
#00001 : 00001
When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
#00010 : 00010
When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
#00011 : 00011
When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
#00100 : 00100
When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
#00101 : 00101
When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
#00110 : 00110
When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
#00111 : 00111
When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
#01000 : 01000
When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
#01001 : 01001
When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
#01010 : 01010
When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
#01011 : 01011
When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
#01100 : 01100
When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
#01101 : 01101
When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
#01110 : 01110
When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
#01111 : 01111
When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
#10000 : 10000
When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
#10001 : 10001
When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
#10010 : 10010
When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
#10011 : 10011
When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
#10100 : 10100
When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
#10101 : 10101
When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
#10110 : 10110
When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
#10111 : 10111
When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
#11010 : 11010
When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
#11011 : 11011
When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
#11101 : 11101
When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11110 : 11110
When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
#11111 : 11111
Module is disabled.
End of enumeration elements list.
DIFF : Differential Mode Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single-ended conversions and input channels are selected.
#1 : 1
Differential conversions and input channels are selected.
End of enumeration elements list.
AIEN : Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion complete interrupt is disabled.
#1 : 1
Conversion complete interrupt is enabled.
End of enumeration elements list.
COCO : Conversion Complete Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion is not completed.
#1 : 1
Conversion is completed.
End of enumeration elements list.
ADC Data Result Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
D : Data result
bits : 0 - 15 (16 bit)
access : read-only
Status and Control Register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFSEL : Voltage Reference Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Default voltage reference pin pair, that is, external pins VREFH and VREFL
#01 : 01
Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
End of enumeration elements list.
DMAEN : DMA Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA is disabled.
#1 : 1
DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
End of enumeration elements list.
ACREN : Compare Function Range Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Range function disabled. Only CV1 is compared.
#1 : 1
Range function enabled. Both CV1 and CV2 are compared.
End of enumeration elements list.
ACFGT : Compare Function Greater Than Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
#1 : 1
Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
End of enumeration elements list.
ACFE : Compare Function Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function disabled.
#1 : 1
Compare function enabled.
End of enumeration elements list.
ADTRG : Conversion Trigger Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger selected.
#1 : 1
Hardware trigger selected.
End of enumeration elements list.
ADACT : Conversion Active
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion not in progress.
#1 : 1
Conversion in progress.
End of enumeration elements list.
Status and Control Register 3
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AVGS : Hardware Average Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
4 samples averaged.
#01 : 01
8 samples averaged.
#10 : 10
16 samples averaged.
#11 : 11
32 samples averaged.
End of enumeration elements list.
AVGE : Hardware Average Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware average function disabled.
#1 : 1
Hardware average function enabled.
End of enumeration elements list.
ADCO : Continuous Conversion Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
#1 : 1
Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
End of enumeration elements list.
CALF : Calibration Failed Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Calibration completed normally.
#1 : 1
Calibration failed. ADC accuracy specifications are not guaranteed.
End of enumeration elements list.
CAL : Calibration
bits : 7 - 7 (1 bit)
access : read-write
ADC Offset Correction Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFS : Offset Error Correction Value
bits : 0 - 15 (16 bit)
access : read-write
ADC Plus-Side Gain Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG : Plus-Side Gain
bits : 0 - 15 (16 bit)
access : read-write
Compare Value Registers
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Compare Value.
bits : 0 - 15 (16 bit)
access : read-write
ADC Minus-Side Gain Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MG : Minus-Side Gain
bits : 0 - 15 (16 bit)
access : read-write
ADC Data Result Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
D : Data result
bits : 0 - 15 (16 bit)
access : read-only
ADC Plus-Side General Calibration Value Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLPD : Calibration Value
bits : 0 - 5 (6 bit)
access : read-write
ADC Plus-Side General Calibration Value Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLPS : Calibration Value
bits : 0 - 5 (6 bit)
access : read-write
ADC Plus-Side General Calibration Value Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLP4 : Calibration Value
bits : 0 - 9 (10 bit)
access : read-write
ADC Status and Control Registers 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
#00001 : 00001
When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
#00010 : 00010
When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
#00011 : 00011
When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
#00100 : 00100
When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
#00101 : 00101
When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
#00110 : 00110
When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
#00111 : 00111
When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
#01000 : 01000
When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
#01001 : 01001
When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
#01010 : 01010
When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
#01011 : 01011
When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
#01100 : 01100
When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
#01101 : 01101
When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
#01110 : 01110
When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
#01111 : 01111
When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
#10000 : 10000
When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
#10001 : 10001
When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
#10010 : 10010
When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
#10011 : 10011
When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
#10100 : 10100
When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
#10101 : 10101
When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
#10110 : 10110
When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
#10111 : 10111
When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
#11010 : 11010
When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
#11011 : 11011
When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
#11101 : 11101
When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11110 : 11110
When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
#11111 : 11111
Module is disabled.
End of enumeration elements list.
DIFF : Differential Mode Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single-ended conversions and input channels are selected.
#1 : 1
Differential conversions and input channels are selected.
End of enumeration elements list.
AIEN : Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion complete interrupt is disabled.
#1 : 1
Conversion complete interrupt is enabled.
End of enumeration elements list.
COCO : Conversion Complete Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion is not completed.
#1 : 1
Conversion is completed.
End of enumeration elements list.
ADC Plus-Side General Calibration Value Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLP3 : Calibration Value
bits : 0 - 8 (9 bit)
access : read-write
ADC Plus-Side General Calibration Value Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLP2 : Calibration Value
bits : 0 - 7 (8 bit)
access : read-write
ADC Plus-Side General Calibration Value Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLP1 : Calibration Value
bits : 0 - 6 (7 bit)
access : read-write
Compare Value Registers
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Compare Value.
bits : 0 - 15 (16 bit)
access : read-write
ADC Plus-Side General Calibration Value Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLP0 : Calibration Value
bits : 0 - 5 (6 bit)
access : read-write
ADC PGA Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PGAG : PGA Gain Setting
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1
#0001 : 0001
2
#0010 : 0010
4
#0011 : 0011
8
#0100 : 0100
16
#0101 : 0101
32
#0110 : 0110
64
End of enumeration elements list.
PGALPb : PGA Low-Power Mode Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PGA runs in Low-Power mode.
#1 : 1
PGA runs in Normal Power mode.
End of enumeration elements list.
PGAEN : PGA Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PGA disabled.
#1 : 1
PGA enabled.
End of enumeration elements list.
ADC Minus-Side General Calibration Value Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLMD : Calibration Value
bits : 0 - 5 (6 bit)
access : read-write
ADC Minus-Side General Calibration Value Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLMS : Calibration Value
bits : 0 - 5 (6 bit)
access : read-write
ADC Minus-Side General Calibration Value Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLM4 : Calibration Value
bits : 0 - 9 (10 bit)
access : read-write
ADC Minus-Side General Calibration Value Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLM3 : Calibration Value
bits : 0 - 8 (9 bit)
access : read-write
ADC Minus-Side General Calibration Value Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLM2 : Calibration Value
bits : 0 - 7 (8 bit)
access : read-write
ADC Minus-Side General Calibration Value Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLM1 : Calibration Value
bits : 0 - 6 (7 bit)
access : read-write
ADC Minus-Side General Calibration Value Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLM0 : Calibration Value
bits : 0 - 5 (6 bit)
access : read-write
ADC Configuration Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADICLK : Input Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus clock
#01 : 01
(Bus clock)/2
#10 : 10
Alternate clock (ALTCLK)
#11 : 11
Asynchronous clock (ADACK)
End of enumeration elements list.
MODE : Conversion mode selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
#01 : 01
When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
#10 : 10
When DIFF=0:It is single-ended 10-bit conversion ; when DIFF=1, it is differential 11-bit conversion with 2's complement output.
#11 : 11
When DIFF=0:It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADLSMP : Sample time configuration
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Short sample time.
#1 : 1
Long sample time.
End of enumeration elements list.
ADIV : Clock Divide Select
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 00
The divide ratio is 1 and the clock rate is input clock.
#01 : 01
The divide ratio is 2 and the clock rate is (input clock)/2.
#10 : 10
The divide ratio is 4 and the clock rate is (input clock)/4.
#11 : 11
The divide ratio is 8 and the clock rate is (input clock)/8.
End of enumeration elements list.
ADLPC : Low-Power Configuration
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal power configuration.
#1 : 1
Low-power configuration. The power is reduced at the expense of maximum clock speed.
End of enumeration elements list.
ADC Configuration Register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADLSTS : Long Sample Time Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
#01 : 01
12 extra ADCK cycles; 16 ADCK cycles total sample time.
#10 : 10
6 extra ADCK cycles; 10 ADCK cycles total sample time.
#11 : 11
2 extra ADCK cycles; 6 ADCK cycles total sample time.
End of enumeration elements list.
ADHSC : High-Speed Configuration
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal conversion sequence selected.
#1 : 1
High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
End of enumeration elements list.
ADACKEN : Asynchronous Clock Output Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
#1 : 1
Asynchronous clock and clock output is enabled regardless of the state of the ADC.
End of enumeration elements list.
MUXSEL : ADC Mux Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADxxa channels are selected.
#1 : 1
ADxxb channels are selected.
End of enumeration elements list.
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