\n
address_offset : 0x0 Bytes (0x0)
size : 0x140 byte (0x0)
mem_usage : registers
protection : not protected
PIT Module Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRZ : Freeze
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timers continue to run in debug mode.
#1 : 1
Timers are stopped in debug mode.
End of enumeration elements list.
MDIS : Module Disable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock for PIT Timers is enabled.
#1 : 1
Clock for PIT Timers is disabled.
End of enumeration elements list.
Timer Load Value Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSV : Timer Start Value Bits
bits : 0 - 31 (32 bit)
access : read-write
Current Timer Value Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only
Timer Control Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEN : Timer Enable Bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer n is disabled.
#1 : 1
Timer n is active.
End of enumeration elements list.
TIE : Timer Interrupt Enable Bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt requests from Timer n are disabled.
#1 : 1
Interrupt will be requested whenever TIF is set.
End of enumeration elements list.
Timer Flag Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out has not yet occurred.
#1 : 1
Time-out has occurred.
End of enumeration elements list.
Timer Load Value Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSV : Timer Start Value Bits
bits : 0 - 31 (32 bit)
access : read-write
Current Timer Value Register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only
Timer Control Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEN : Timer Enable Bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer n is disabled.
#1 : 1
Timer n is active.
End of enumeration elements list.
TIE : Timer Interrupt Enable Bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt requests from Timer n are disabled.
#1 : 1
Interrupt will be requested whenever TIF is set.
End of enumeration elements list.
Timer Flag Register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out has not yet occurred.
#1 : 1
Time-out has occurred.
End of enumeration elements list.
Timer Load Value Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSV : Timer Start Value Bits
bits : 0 - 31 (32 bit)
access : read-write
Current Timer Value Register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only
Timer Control Register
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEN : Timer Enable Bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer n is disabled.
#1 : 1
Timer n is active.
End of enumeration elements list.
TIE : Timer Interrupt Enable Bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt requests from Timer n are disabled.
#1 : 1
Interrupt will be requested whenever TIF is set.
End of enumeration elements list.
Timer Flag Register
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out has not yet occurred.
#1 : 1
Time-out has occurred.
End of enumeration elements list.
Timer Load Value Register
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSV : Timer Start Value Bits
bits : 0 - 31 (32 bit)
access : read-write
Current Timer Value Register
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only
Timer Control Register
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEN : Timer Enable Bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer n is disabled.
#1 : 1
Timer n is active.
End of enumeration elements list.
TIE : Timer Interrupt Enable Bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt requests from Timer n are disabled.
#1 : 1
Interrupt will be requested whenever TIF is set.
End of enumeration elements list.
Timer Flag Register
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out has not yet occurred.
#1 : 1
Time-out has occurred.
End of enumeration elements list.
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