\n

MC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SRSH

SRSL

PMPROT

PMCTRL


SRSH

System Reset Status Register High
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRSH SRSH read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 JTAG LOCKUP SW

JTAG : JTAG generated reset
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by JTAG

#1 : 1

Reset caused by JTAG

End of enumeration elements list.

LOCKUP : Core Lock-up
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by core LOCKUP event

#1 : 1

Reset caused by core LOCKUP event

End of enumeration elements list.

SW : Software
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by software setting of SYSRESETREQ bit

#1 : 1

Reset caused by software setting of SYSRESETREQ bit

End of enumeration elements list.


SRSL

System Reset Status Register Low
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRSL SRSL read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WAKEUP LVD LOC COP PIN POR

WAKEUP : Low-leakage wakeup reset
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by LLWU module wakeup source

#1 : 1

Reset caused by LLWU module wakeup source

End of enumeration elements list.

LVD : Low-voltage detect reset
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by LVD trip or POR

#1 : 1

Reset caused by LVD trip or POR

End of enumeration elements list.

LOC : Loss-of-clock reset
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by a loss of external clock.

#1 : 1

Reset caused by a loss of external clock.

End of enumeration elements list.

COP : Computer Operating Properly (COP) Watchdog
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by COP timeout

#1 : 1

Reset caused by COP timeout

End of enumeration elements list.

PIN : External reset pin
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by external reset pin

#1 : 1

Reset caused by external reset pin

End of enumeration elements list.

POR : Power-on reset
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by POR

#1 : 1

Reset caused by POR

End of enumeration elements list.


PMPROT

Power Mode Protection Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMPROT PMPROT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AVLLS1 AVLLS2 AVLLS3 ALLS AVLP

AVLLS1 : Allow very low leakage stop 1 mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

VLLS1 is not allowed

#1 : 1

VLLS1 is allowed

End of enumeration elements list.

AVLLS2 : Allow very low leakage stop 2 mode
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

VLLS2 is not allowed

#1 : 1

VLLS2 is allowed

End of enumeration elements list.

AVLLS3 : Allow Very Low Leakage Stop 3 Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

VLLS3 is not allowed

#1 : 1

VLLS3 is allowed

End of enumeration elements list.

ALLS : Allow low leakage stop mode
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

LLS is not allowed

#1 : 1

LLS is allowed

End of enumeration elements list.

AVLP : Allow very low power modes
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

VLPR, VLPW, and VLPS are not allowed

#1 : 1

VLPR, VLPW, and VLPS are allowed

End of enumeration elements list.


PMCTRL

Power Mode Control Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMCTRL PMCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LPLLSM RUNM LPWUI

LPLLSM : Low Power, Low Leakage Stop Mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

Normal stop

#010 : 010

Very low power stop (VLPS)

#011 : 011

Low leakage stop (LLS)

#101 : 101

Very low leakage stop 3 (VLLS3)

#110 : 110

Very low leakage stop 2 (VLLS2)

#111 : 111

Very low leakage stop 1 (VLLS1)

End of enumeration elements list.

RUNM : Run Mode Enable
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#00 : 00

Normal run mode

#10 : 10

Very low power run mode

End of enumeration elements list.

LPWUI : Low Power Wake Up on Interrupt
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The voltage regulator remains in stop regulation on an interrupt

#1 : 1

The voltage regulator exits stop regulation on an interrupt

End of enumeration elements list.



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