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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

Registers

A1

F

C1

S

D

C2

FLT

RA

SMB

A2

SLTH

SLTL


A1

I2C Address Register 1
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

A1 A1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AD

AD : Address
bits : 1 - 7 (7 bit)
access : read-write


F

I2C Frequency Divider register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

F F read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ICR MULT

ICR : Clock rate
bits : 0 - 5 (6 bit)
access : read-write

MULT : no description available
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

mul = 1

#01 : 01

mul = 2

#10 : 10

mul = 4

End of enumeration elements list.


C1

I2C Control Register 1
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1 C1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DMAEN WUEN RSTA TXAK TX MST IICIE IICEN

DMAEN : DMA enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

All DMA signalling disabled.

#1 : 1

DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.

End of enumeration elements list.

WUEN : Wakeup enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation. No interrupt generated when address matching in low power mode.

#1 : 1

Enables the wakeup function in low power mode.

End of enumeration elements list.

RSTA : Repeat START
bits : 2 - 2 (1 bit)
access : write-only

TXAK : Transmit acknowledge enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

An acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving byte.

#1 : 1

No acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving data byte.SCL is held low until TXAK is written.

End of enumeration elements list.

TX : Transmit mode select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receive

#1 : 1

Transmit

End of enumeration elements list.

MST : Master mode select
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Slave mode

#1 : 1

Master mode

End of enumeration elements list.

IICIE : I2C interrupt enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

IICEN : I2C enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.


S

I2C Status Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

S S read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RXAK IICIF SRW RAM ARBL BUSY IAAS TCF

RXAK : Receive acknowledge
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Acknowledge signal was received after the completion of one byte of data transmission on the bus

#1 : 1

No acknowledge signal detected

End of enumeration elements list.

IICIF : Interrupt flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt pending

#1 : 1

Interrupt pending

End of enumeration elements list.

SRW : Slave read/write
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Slave receive, master writing to slave

#1 : 1

Slave transmit, master reading from slave

End of enumeration elements list.

RAM : Range address match
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not addressed

#1 : 1

Addressed as a slave

End of enumeration elements list.

ARBL : Arbitration lost
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Standard bus operation.

#1 : 1

Loss of arbitration.

End of enumeration elements list.

BUSY : Bus busy
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Bus is idle

#1 : 1

Bus is busy

End of enumeration elements list.

IAAS : Addressed as a slave
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not addressed

#1 : 1

Addressed as a slave

End of enumeration elements list.

TCF : Transfer complete flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Transfer in progress

#1 : 1

Transfer complete

End of enumeration elements list.


D

I2C Data I/O register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 7 (8 bit)
access : read-write


C2

I2C Control Register 2
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2 C2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AD RMEN SBRC HDRS ADEXT GCAEN

AD : Slave address
bits : 0 - 2 (3 bit)
access : read-write

RMEN : Range address matching enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.

#1 : 1

Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.

End of enumeration elements list.

SBRC : Slave baud rate control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The slave baud rate follows the master baud rate and clock stretching may occur

#1 : 1

Slave baud rate is independent of the master baud rate

End of enumeration elements list.

HDRS : High drive select
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal drive mode

#1 : 1

High drive mode

End of enumeration elements list.

ADEXT : Address extension
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

7-bit address scheme

#1 : 1

10-bit address scheme

End of enumeration elements list.

GCAEN : General call address enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.


FLT

I2C Programmable Input Glitch Filter register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLT FLT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FLT

FLT : I2C programmable filter factor
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

#0 : 0

No filter/bypass

End of enumeration elements list.


RA

I2C Range Address register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RA RA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RAD

RAD : Range slave address
bits : 1 - 7 (7 bit)
access : read-write


SMB

I2C SMBus Control and Status register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMB SMB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SHTF2IE SHTF2 SHTF1 SLTF TCKSEL SIICAEN ALERTEN FACK

SHTF2IE : SHTF2 interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

SHTF2 interrupt is disabled

#1 : 1

SHTF2 interrupt is enabled

End of enumeration elements list.

SHTF2 : SCL high timeout flag 2
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SCL high and SDA low timeout occurs

#1 : 1

SCL high and SDA low timeout occurs

End of enumeration elements list.

SHTF1 : SCL high timeout flag 1
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

No SCL high and SDA high timeout occurs

#1 : 1

SCL high and SDA high timeout occurs

End of enumeration elements list.

SLTF : SCL low timeout flag
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No low timeout occurs

#1 : 1

Low timeout occurs

End of enumeration elements list.

TCKSEL : Timeout counter clock select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timeout counter counts at the frequency of the bus clock / 64

#1 : 1

Timeout counter counts at the frequency of the bus clock

End of enumeration elements list.

SIICAEN : Second I2C address enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C address register 2 matching is disabled

#1 : 1

I2C address register 2 matching is enabled

End of enumeration elements list.

ALERTEN : SMBus alert response address enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

SMBus alert response address matching is disabled

#1 : 1

SMBus alert response address matching is enabled

End of enumeration elements list.

FACK : Fast NACK/ACK enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

An ACK or NACK is sent on the following receiving data byte

#1 : 1

Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.

End of enumeration elements list.


A2

I2C Address Register 2
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

A2 A2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SAD

SAD : SMBus address
bits : 1 - 7 (7 bit)
access : read-write


SLTH

I2C SCL Low Timeout Register High
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLTH SLTH read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SSLT

SSLT : no description available
bits : 0 - 7 (8 bit)
access : read-write


SLTL

I2C SCL Low Timeout Register Low
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLTL SLTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SSLT

SSLT : no description available
bits : 0 - 7 (8 bit)
access : read-write



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