\n
address_offset : 0x0 Bytes (0x0)
size : 0xCC byte (0x0)
mem_usage : registers
protection : not protected
Pin Control Register n
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Global Pin Control Low Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : write-only
GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : write-only
Global Pin Control High Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : write-only
GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : write-only
Interrupt Status Flag Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISF : Interrupt Status Flag
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the passive input filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific/JTAG/NMI).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA request disabled.
#0001 : 0001
DMA request on rising edge.
#0010 : 0010
DMA request on falling edge.
#0011 : 0011
DMA request on either edge.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt that remains asserted, then the flag will set again immediately.
End of enumeration elements list.
Digital Filter Enable Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFE : Digital Filter Enable
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
Digital Filter Clock Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS : Clock Source
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filters are clocked by the bus clock.
#1 : 1
Digital filters are clocked by the 1 kHz LPO clock.
End of enumeration elements list.
Digital Filter Width Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILT : Filter Length
bits : 0 - 4 (5 bit)
access : read-write
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