Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
MCG Control 1 Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IREFSTEN : Internal Reference Stop Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal reference clock is disabled in Stop mode.
#1 : 1
Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
End of enumeration elements list.
IRCLKEN : Internal Reference Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCGIRCLK inactive.
#1 : 1
MCGIRCLK active.
End of enumeration elements list.
IREFS : Internal Reference Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
External reference clock is selected.
#1 : 1
The slow internal reference clock is selected.
End of enumeration elements list.
FRDIV : FLL External Reference Divider
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 000
If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
#001 : 001
If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
#010 : 010
If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
#011 : 011
If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
#100 : 100
If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
#101 : 101
If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
#110 : 110
If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is Reserved .
#111 : 111
If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is Reserved .
End of enumeration elements list.
CLKS : Clock Source Select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit).
#01 : 01
Encoding 1 - Internal reference clock is selected.
#10 : 10
Encoding 2 - External reference clock is selected.
#11 : 11
Encoding 3 - Reserved, defaults to 00.
End of enumeration elements list.
MCG Control 2 Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRCS : Internal Reference Clock Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slow internal reference clock selected.
#1 : 1
Fast internal reference clock selected.
End of enumeration elements list.
LP : Low Power Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FLL (or PLL) is not disabled in bypass modes.
#1 : 1
FLL (or PLL) is disabled in bypass modes (lower power)
End of enumeration elements list.
EREFS : External Reference Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
External reference clock requested.
#1 : 1
Oscillator requested.
End of enumeration elements list.
HGO : High Gain Oscillator Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configure crystal oscillator for low-power operation.
#1 : 1
Configure crystal oscillator for high-gain operation.
End of enumeration elements list.
RANGE : Frequency Range Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Encoding 0 - Low frequency range selected for the crystal oscillator .
#01 : 01
Encoding 1 - High frequency range selected for the crystal oscillator .
End of enumeration elements list.
MCG Control 3 Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCTRIM : Slow Internal Reference Clock Trim Setting
bits : 0 - 7 (8 bit)
access : read-write
MCG Control 4 Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCFTRIM : Slow Internal Reference Clock Fine Trim
bits : 0 - 0 (1 bit)
access : read-write
FCTRIM : Fast Internal Reference Clock Trim Setting
bits : 1 - 4 (4 bit)
access : read-write
DRST_DRS : DCO Range Select
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 00
Encoding 0 - Low range (reset default).
#01 : 01
Encoding 1 - Mid range.
#10 : 10
Encoding 2 - Mid-high range.
#11 : 11
Encoding 3 - High range.
End of enumeration elements list.
DMX32 : DCO Maximum Frequency with 32.768 kHz Reference
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DCO has a default range of 25%.
#1 : 1
DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
End of enumeration elements list.
MCG Control 5 Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRDIV : PLL External Reference Divider
bits : 0 - 4 (5 bit)
access : read-write
PLLSTEN : PLL Stop Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCGPLLCLK is disabled in any of the Stop modes.
#1 : 1
MCGPLLCLK is enabled if system is in Normal Stop mode.
End of enumeration elements list.
PLLCLKEN : PLL Clock Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCGPLLCLK is inactive.
#1 : 1
MCGPLLCLK is active.
End of enumeration elements list.
MCG Control 6 Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDIV : VCO Divider
bits : 0 - 4 (5 bit)
access : read-write
CME : Clock Monitor Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
External clock monitor is disabled.
#1 : 1
Generate a reset request on loss of external clock.
End of enumeration elements list.
PLLS : PLL Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
FLL is selected.
#1 : 1
PLL is selected (PRDIV need to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4 MHz prior to setting the PLLS bit).
End of enumeration elements list.
LOLIE : Loss of Lock Interrrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated on loss of lock.
#1 : 1
Generate an interrupt request on loss of lock.
End of enumeration elements list.
MCG Status Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRCST : Internal Reference Clock Status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Source of internal reference clock is the slow clock (32 kHz IRC).
#1 : 1
Source of internal reference clock is the fast clock (2 MHz IRC).
End of enumeration elements list.
OSCINIT : OSC Initialization
bits : 1 - 1 (1 bit)
access : read-only
CLKST : Clock Mode Status
bits : 2 - 3 (2 bit)
access : read-only
Enumeration:
#00 : 00
Encoding 0 - Output of the FLL is selected (reset default).
#01 : 01
Encoding 1 - Internal reference clock is selected.
#10 : 10
Encoding 2 - External reference clock is selected.
#11 : 11
Encoding 3 - Output of the PLL is selected.
End of enumeration elements list.
IREFST : Internal Reference Status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Source of FLL reference clock is the external reference clock.
#1 : 1
Source of FLL reference clock is the internal reference clock.
End of enumeration elements list.
PLLST : PLL Select Status
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Source of PLLS clock is FLL clock.
#1 : 1
Source of PLLS clock is PLL clock.
End of enumeration elements list.
LOCK : Lock Status
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL is currently unlocked.
#1 : 1
PLL is currently locked.
End of enumeration elements list.
LOLS : Loss of Lock Status
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL has not lost lock since LOLS was last cleared.
#1 : 1
PLL has lost lock since LOLS was last cleared.
End of enumeration elements list.
MCG Auto Trim Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATMF : Automatic Trim machine Fail Flag
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Automatic Trim Machine completed normally.
#1 : 1
Automatic Trim Machine failed.
End of enumeration elements list.
ATMS : Automatic Trim Machine Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
32 kHz Internal Reference Clock selected.
#1 : 1
4 MHz Internal Reference Clock selected.
End of enumeration elements list.
ATME : Automatic Trim Machine Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto Trim Machine disabled.
#1 : 1
Auto Trim Machine enabled.
End of enumeration elements list.
MCG Auto Trim Compare Value High Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATCVH : ATM Compare Value High
bits : 0 - 7 (8 bit)
access : read-write
MCG Auto Trim Compare Value Low Register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATCVL : ATM Compare Value Low
bits : 0 - 7 (8 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.