Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x8 Bytes (0x0)
size : 0xD38 byte (0x0)
mem_usage : registers
protection : not protected
Auxiliary Control Register,
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISMCYCINT : Disables interruption of multi-cycle instructions.
bits : 0 - 0 (1 bit)
access : read-write
DISDEFWBUF : Disables write buffer use during default memory map accesses.
bits : 1 - 1 (1 bit)
access : read-write
DISFOLD : Disables folding of IT instructions.
bits : 2 - 2 (1 bit)
access : read-write
CPUID Base Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Indicates patch release: 0x0 = Patch 0
bits : 0 - 3 (4 bit)
access : read-only
PARTNO : Indicates part number
bits : 4 - 15 (12 bit)
access : read-only
VARIANT : Indicates processor revision: 0x2 = Revision 2
bits : 20 - 23 (4 bit)
access : read-only
IMPLEMENTER : Implementer code
bits : 24 - 31 (8 bit)
access : read-only
Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Active exception number
bits : 0 - 8 (9 bit)
access : read-only
RETTOBASE : no description available
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
there are preempted active exceptions to execute
#1 : 1
there are no active exceptions, or the currently-executing exception is the only active exception
End of enumeration elements list.
VECTPENDING : Exception number of the highest priority pending enabled exception
bits : 12 - 17 (6 bit)
access : read-only
ISRPENDING : no description available
bits : 22 - 22 (1 bit)
access : read-only
ISRPREEMPT : no description available
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
Will not service
#1 : 1
Will service a pending exception
End of enumeration elements list.
PENDSTCLR : no description available
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
#0 : 0
no effect
#1 : 1
removes the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
write: no effect; read: SysTick exception is not pending
#1 : 1
write: changes SysTick exception state to pending; read: SysTick exception is pending
End of enumeration elements list.
PENDSVCLR : no description available
bits : 27 - 27 (1 bit)
access : write-only
Enumeration:
#0 : 0
no effect
#1 : 1
removes the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
write: no effect; read: PendSV exception is not pending
#1 : 1
write: changes PendSV exception state to pending; read: PendSV exception is pending
End of enumeration elements list.
NMIPENDSET : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
write: no effect; read: NMI exception is not pending
#1 : 1
write: changes NMI exception state to pending; read: NMI exception is pending
End of enumeration elements list.
Vector Table Offset Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBLOFF : Vector table base offset
bits : 7 - 31 (25 bit)
access : read-write
Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTRESET : no description available
bits : 0 - 0 (1 bit)
access : write-only
VECTCLRACTIVE : no description available
bits : 1 - 1 (1 bit)
access : write-only
SYSRESETREQ : no description available
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
no system reset request
#1 : 1
asserts a signal to the outer system that requests a reset
End of enumeration elements list.
PRIGROUP : Interrupt priority grouping field. This field determines the split of group priority from subpriority.
bits : 8 - 10 (3 bit)
access : read-write
ENDIANNESS : no description available
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
Little-endian
#1 : 1
Big-endian
End of enumeration elements list.
VECTKEY : Register key
bits : 16 - 31 (16 bit)
access : read-write
System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
o not sleep when returning to Thread mode
#1 : 1
enter sleep, or deep sleep, on return from an ISR
End of enumeration elements list.
SLEEPDEEP : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
sleep
#1 : 1
deep sleep
End of enumeration elements list.
SEVONPEND : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
#1 : 1
enabled events and all interrupts, including disabled interrupts, can wakeup the processor
End of enumeration elements list.
Configuration and Control Register
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONBASETHRDENA : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
processor can enter Thread mode only when no exception is active
#1 : 1
processor can enter Thread mode from any level under the control of an EXC_RETURN value
End of enumeration elements list.
USERSETMPEND : Enables unprivileged software access to the STIR
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
UNALIGN_TRP : Enables unaligned access traps
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
do not trap unaligned halfword and word accesses
#1 : 1
trap unaligned halfword and word accesses
End of enumeration elements list.
DIV_0_TRP : Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
do not trap divide by 0
#1 : 1
trap divide by 0
End of enumeration elements list.
BFHFNMIGN : Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
data bus faults caused by load and store instructions cause a lock-up
#1 : 1
handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions
End of enumeration elements list.
STKALIGN : Indicates stack alignment on exception entry
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
4-byte aligned
#1 : 1
8-byte aligned
End of enumeration elements list.
System Handler Priority Register 1
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of system handler 4, MemManage
bits : 0 - 7 (8 bit)
access : read-write
PRI_5 : Priority of system handler 5, BusFault
bits : 8 - 15 (8 bit)
access : read-write
PRI_6 : Priority of system handler 6, UsageFault
bits : 16 - 23 (8 bit)
access : read-write
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of system handler 11, SVCall
bits : 24 - 31 (8 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of system handler 14, PendSV
bits : 16 - 23 (8 bit)
access : read-write
PRI_15 : Priority of system handler 15, SysTick exception
bits : 24 - 31 (8 bit)
access : read-write
System Handler Control and State Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMFAULTACT : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not active
#1 : 1
exception is active
End of enumeration elements list.
BUSFAULTACT : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not active
#1 : 1
exception is active
End of enumeration elements list.
USGFAULTACT : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not active
#1 : 1
exception is active
End of enumeration elements list.
SVCALLACT : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not active
#1 : 1
exception is active
End of enumeration elements list.
MONITORACT : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not active
#1 : 1
exception is active
End of enumeration elements list.
PENDSVACT : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not active
#1 : 1
exception is active
End of enumeration elements list.
SYSTICKACT : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not active
#1 : 1
exception is active
End of enumeration elements list.
USGFAULTPENDED : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not pending
#1 : 1
exception is pending
End of enumeration elements list.
MEMFAULTPENDED : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not pending
#1 : 1
exception is pending
End of enumeration elements list.
BUSFAULTPENDED : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not pending
#1 : 1
exception is pending
End of enumeration elements list.
SVCALLPENDED : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not pending
#1 : 1
exception is pending
End of enumeration elements list.
MEMFAULTENA : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable the exception
#1 : 1
enable the exception
End of enumeration elements list.
BUSFAULTENA : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable the exception
#1 : 1
enable the exception
End of enumeration elements list.
USGFAULTENA : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable the exception
#1 : 1
enable the exception
End of enumeration elements list.
Configurable Fault Status Registers
address_offset : 0xD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IACCVIOL : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
no instruction access violation fault
#1 : 1
the processor attempted an instruction fetch from a location that does not permit execution
End of enumeration elements list.
DACCVIOL : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
no data access violation fault
#1 : 1
the processor attempted a load or store at a location that does not permit the operation
End of enumeration elements list.
MUNSTKERR : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
no unstacking fault
#1 : 1
unstack for an exception return has caused one or more access violations
End of enumeration elements list.
MSTKERR : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
no stacking fault
#1 : 1
stacking for an exception entry has caused one or more access violations
End of enumeration elements list.
MLSPERR : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No MemManage fault occurred during floating-point lazy state preservation
#1 : 1
A MemManage fault occurred during floating-point lazy state preservation
End of enumeration elements list.
MMARVALID : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
value in MMAR is not a valid fault address
#1 : 1
MMAR holds a valid fault address
End of enumeration elements list.
IBUSERR : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
no instruction bus error
#1 : 1
instruction bus error
End of enumeration elements list.
PRECISERR : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
no precise data bus error
#1 : 1
a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault
End of enumeration elements list.
IMPRECISERR : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
no imprecise data bus error
#1 : 1
a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error
End of enumeration elements list.
UNSTKERR : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
no unstacking fault
#1 : 1
unstack for an exception return has caused one or more BusFaults
End of enumeration elements list.
STKERR : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
no stacking fault
#1 : 1
stacking for an exception entry has caused one or more BusFaults
End of enumeration elements list.
LSPERR : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus fault occurred during floating-point lazy state preservation
#1 : 1
A bus fault occurred during floating-point lazy state preservation
End of enumeration elements list.
BFARVALID : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
value in BFAR is not a valid fault address
#1 : 1
BFAR holds a valid fault address
End of enumeration elements list.
UNDEFINSTR : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
no undefined instruction UsageFault
#1 : 1
the processor has attempted to execute an undefined instruction
End of enumeration elements list.
INVSTATE : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
no invalid state UsageFault
#1 : 1
the processor has attempted to execute an instruction that makes illegal use of the EPSR
End of enumeration elements list.
INVPC : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
no invalid PC load UsageFault
#1 : 1
the processor has attempted an illegal load of EXC_RETURN to the PC
End of enumeration elements list.
NOCP : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
no UsageFault caused by attempting to access a coprocessor
#1 : 1
the processor has attempted to access a coprocessor
End of enumeration elements list.
UNALIGNED : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
no unaligned access fault, or unaligned access trapping not enabled
#1 : 1
the processor has made an unaligned memory access
End of enumeration elements list.
DIVBYZERO : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
no divide by zero fault, or divide by zero trapping not enabled
#1 : 1
the processor has executed an SDIV or UDIV instruction with a divisor of 0
End of enumeration elements list.
HardFault Status register
address_offset : 0xD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTTBL : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
no BusFault on vector table read
#1 : 1
BusFault on vector table read
End of enumeration elements list.
FORCED : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
no forced HardFault
#1 : 1
forced HardFault
End of enumeration elements list.
DEBUGEVT : no description available
bits : 31 - 31 (1 bit)
access : read-write
Debug Fault Status Register
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALTED : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No active halt request debug event
#1 : 1
Halt request debug event active
End of enumeration elements list.
BKPT : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No current breakpoint debug event
#1 : 1
At least one current breakpoint debug event
End of enumeration elements list.
DWTTRAP : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No current debug events generated by the DWT
#1 : 1
At least one current debug event generated by the DWT
End of enumeration elements list.
VCATCH : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Vector catch triggered
#1 : 1
Vector catch triggered
End of enumeration elements list.
EXTERNAL : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EDBGRQ debug event
#1 : 1
EDBGRQ debug event
End of enumeration elements list.
MemManage Address Register
address_offset : 0xD34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of MemManage fault location
bits : 0 - 31 (32 bit)
access : read-write
BusFault Address Register
address_offset : 0xD38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address of the BusFault location
bits : 0 - 31 (32 bit)
access : read-write
Auxiliary Fault Status Register
address_offset : 0xD3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUXFAULT : Latched version of the AUXFAULT inputs
bits : 0 - 31 (32 bit)
access : read-write
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