Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
DMA System Address register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSADDR : DMA System Address
bits : 2 - 31 (30 bit)
access : read-write
Command Response 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRSP0 : Command Response 0
bits : 0 - 31 (32 bit)
access : read-only
Command Response 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRSP1 : Command Response 1
bits : 0 - 31 (32 bit)
access : read-only
Command Response 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRSP2 : Command Response 2
bits : 0 - 31 (32 bit)
access : read-only
Command Response 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDRSP3 : Command Response 3
bits : 0 - 31 (32 bit)
access : read-only
Buffer Data Port register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATCONT : Data Content
bits : 0 - 31 (32 bit)
access : read-write
Present State register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CIHB : Command Inhibit (CMD)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Can issue command using only CMD line.
#1 : 1
Cannot issue command.
End of enumeration elements list.
CDIHB : Command Inhibit (DAT)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Can issue command which uses the DAT line.
#1 : 1
Cannot issue command which uses the DAT line.
End of enumeration elements list.
DLA : Data Line Active
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
DAT line inactive.
#1 : 1
DAT line active.
End of enumeration elements list.
SDSTB : SD Clock Stable
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock is changing frequency and not stable.
#1 : 1
Clock is stable.
End of enumeration elements list.
IPGOFF : Bus Clock Gated Off Internally
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Bus clock is active.
#1 : 1
Bus clock is gated off.
End of enumeration elements list.
HCKOFF : System Clock Gated Off Internally
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
System clock is active.
#1 : 1
System clock is gated off.
End of enumeration elements list.
PEROFF : SDHC clock Gated Off Internally
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
SDHC clock is active.
#1 : 1
SDHC clock is gated off.
End of enumeration elements list.
SDOFF : SD Clock Gated Off Internally
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
SD clock is active.
#1 : 1
SD clock is gated off.
End of enumeration elements list.
WTA : Write Transfer Active
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
No valid data.
#1 : 1
Transferring data.
End of enumeration elements list.
RTA : Read Transfer Active
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
No valid data.
#1 : 1
Transferring data.
End of enumeration elements list.
BWEN : Buffer Write Enable
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
Write disable, the buffer can hold valid data less than the write watermark level.
#1 : 1
Write enable, the buffer can hold valid data greater than the write watermark level.
End of enumeration elements list.
BREN : Buffer Read Enable
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
Read disable, valid data less than the watermark level exist in the buffer.
#1 : 1
Read enable, valid data greater than the watermark level exist in the buffer.
End of enumeration elements list.
CINS : Card Inserted
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Power on reset or no card.
#1 : 1
Card inserted.
End of enumeration elements list.
CLSL : CMD Line Signal Level
bits : 23 - 23 (1 bit)
access : read-only
DLSL : DAT Line Signal Level
bits : 24 - 31 (8 bit)
access : read-only
Protocol Control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCTL : LED Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
LED off.
#1 : 1
LED on.
End of enumeration elements list.
DTW : Data Transfer Width
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 00
1-bit mode
#01 : 01
4-bit mode
#10 : 10
8-bit mode
End of enumeration elements list.
D3CD : DAT3 As Card Detection Pin
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAT3 does not monitor card Insertion.
#1 : 1
DAT3 as card detection pin.
End of enumeration elements list.
EMODE : Endian Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Big endian mode
#01 : 01
Half word big endian mode
#10 : 10
Little endian mode
End of enumeration elements list.
CDTL : Card Detect Test Level
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Card detect test level is 0, no card inserted.
#1 : 1
Card detect test level is 1, card inserted.
End of enumeration elements list.
CDSS : Card Detect Signal Selection
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Card detection level is selected for normal purpose.
#1 : 1
Card detection test level is selected for test purpose.
End of enumeration elements list.
DMAS : DMA Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
No DMA or simple DMA is selected.
#01 : 01
ADMA1 is selected.
#10 : 10
ADMA2 is selected.
End of enumeration elements list.
SABGREQ : Stop At Block Gap Request
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer
#1 : 1
Stop
End of enumeration elements list.
CREQ : Continue Request
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Restart
End of enumeration elements list.
RWCTL : Read Wait Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable read wait control, and stop SD clock at block gap when SABGREQ is set.
#1 : 1
Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set.
End of enumeration elements list.
IABG : Interrupt At Block Gap
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
WECINT : Wakeup Event Enable On Card Interrupt
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
WECINS : Wakeup Event Enable On SD Card Insertion
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
WECRM : Wakeup Event Enable On SD Card Removal
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
System Control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPGEN : IPG Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock will be internally gated off.
#1 : 1
Bus clock will not be automatically gated off.
End of enumeration elements list.
HCKEN : System Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
System clock will be internally gated off.
#1 : 1
System clock will not be automatically gated off.
End of enumeration elements list.
PEREN : Peripheral Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SDHC clock will be internally gated off.
#1 : 1
SDHC clock will not be automatically gated off.
End of enumeration elements list.
SDCLKEN : SD Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
DVS : Divisor
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Divisor by 1.
#0001 : 1
Divisor by 2.
#1110 : 1110
Divisor by 15.
#1111 : 1111
Divisor by 16.
End of enumeration elements list.
SDCLKFS : SDCLK Frequency Select
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
#1 : 1
Base clock divided by 2.
#10 : 10
Base clock divided by 4.
#100 : 100
Base clock divided by 8.
#1000 : 1000
Base clock divided by 16.
#10000 : 10000
Base clock divided by 32.
#100000 : 100000
Base clock divided by 64.
#1000000 : 1000000
Base clock divided by 128.
#10000000 : 10000000
Base clock divided by 256.
End of enumeration elements list.
DTOCV : Data Timeout Counter Value
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
SDCLK x 2 13
#0001 : 0001
SDCLK x 2 14
#1110 : 1110
SDCLK x 2 27
End of enumeration elements list.
RSTA : Software Reset For ALL
bits : 24 - 24 (1 bit)
access : write-only
Enumeration:
#0 : 0
No reset.
#1 : 1
Reset.
End of enumeration elements list.
RSTC : Software Reset For CMD Line
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
#0 : 0
No reset.
#1 : 1
Reset.
End of enumeration elements list.
RSTD : Software Reset For DAT Line
bits : 26 - 26 (1 bit)
access : write-only
Enumeration:
#0 : 0
No reset.
#1 : 1
Reset.
End of enumeration elements list.
INITA : Initialization Active
bits : 27 - 27 (1 bit)
access : read-write
Interrupt Status register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Command Complete
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Command not complete.
#1 : 1
Command complete.
End of enumeration elements list.
TC : Transfer Complete
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer not complete.
#1 : 1
Transfer complete.
End of enumeration elements list.
BGE : Block Gap Event
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No block gap event.
#1 : 1
Transaction stopped at block gap.
End of enumeration elements list.
DINT : DMA Interrupt
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No DMA Interrupt.
#1 : 1
DMA Interrupt is generated.
End of enumeration elements list.
BWR : Buffer Write Ready
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not ready to write buffer.
#1 : 1
Ready to write buffer.
End of enumeration elements list.
BRR : Buffer Read Ready
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not ready to read buffer.
#1 : 1
Ready to read buffer.
End of enumeration elements list.
CINS : Card Insertion
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Card state unstable or removed.
#1 : 1
Card inserted.
End of enumeration elements list.
CRM : Card Removal
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Card state unstable or inserted.
#1 : 1
Card removed.
End of enumeration elements list.
CINT : Card Interrupt
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Card Interrupt.
#1 : 1
Generate Card Interrupt.
End of enumeration elements list.
CTOE : Command Timeout Error
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error.
#1 : 1
Time out.
End of enumeration elements list.
CCE : Command CRC Error
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error.
#1 : 1
CRC Error generated.
End of enumeration elements list.
CEBE : Command End Bit Error
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error.
#1 : 1
End Bit Error generated.
End of enumeration elements list.
CIE : Command Index Error
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error.
#1 : 1
Error.
End of enumeration elements list.
DTOE : Data Timeout Error
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error.
#1 : 1
Time out.
End of enumeration elements list.
DCE : Data CRC Error
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error.
#1 : 1
Error.
End of enumeration elements list.
DEBE : Data End Bit Error
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error.
#1 : 1
Error.
End of enumeration elements list.
AC12E : Auto CMD12 Error
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error.
#1 : 1
Error.
End of enumeration elements list.
DMAE : DMA Error
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error.
#1 : 1
Error.
End of enumeration elements list.
Interrupt Status Enable register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCSEN : Command Complete Status Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
TCSEN : Transfer Complete Status Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
BGESEN : Block Gap Event Status Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
DINTSEN : DMA Interrupt Status Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
BWRSEN : Buffer Write Ready Status Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
BRRSEN : Buffer Read Ready Status Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CINSEN : Card Insertion Status Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CRMSEN : Card Removal Status Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CINTSEN : Card Interrupt Status Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CTOESEN : Command Timeout Error Status Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CCESEN : Command CRC Error Status Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CEBESEN : Command End Bit Error Status Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CIESEN : Command Index Error Status Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
DTOESEN : Data Timeout Error Status Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
DCESEN : Data CRC Error Status Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
DEBESEN : Data End Bit Error Status Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
AC12ESEN : Auto CMD12 Error Status Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
DMAESEN : DMA Error Status Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
Interrupt Signal Enable register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCIEN : Command Complete Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
TCIEN : Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
BGEIEN : Block Gap Event Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
DINTIEN : DMA Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
BWRIEN : Buffer Write Ready Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
BRRIEN : Buffer Read Ready Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CINSIEN : Card Insertion Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CRMIEN : Card Removal Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CINTIEN : Card Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CTOEIEN : Command Timeout Error Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CCEIEN : Command CRC Error Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CEBEIEN : Command End Bit Error Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
CIEIEN : Command Index Error Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
DTOEIEN : Data Timeout Error Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
DCEIEN : Data CRC Error Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
DEBEIEN : Data End Bit Error Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
AC12EIEN : Auto CMD12 Error Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
DMAEIEN : DMA Error Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Masked
#1 : 1
Enabled
End of enumeration elements list.
Auto CMD12 Error Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AC12NE : Auto CMD12 Not Executed
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Executed.
#1 : 1
Not executed.
End of enumeration elements list.
AC12TOE : Auto CMD12 Timeout Error
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error.
#1 : 1
Time out.
End of enumeration elements list.
AC12EBE : Auto CMD12 End Bit Error
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error.
#1 : 1
End bit error generated.
End of enumeration elements list.
AC12CE : Auto CMD12 CRC Error
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No CRC error.
#1 : 1
CRC error met in Auto CMD12 response.
End of enumeration elements list.
AC12IE : Auto CMD12 Index Error
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error.
#1 : 1
Error, the CMD index in response is not CMD12.
End of enumeration elements list.
CNIBAC12E : Command Not Issued By Auto CMD12 Error
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error.
#1 : 1
Not issued.
End of enumeration elements list.
Block Attributes register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKSIZE : Transfer Block Size
bits : 0 - 12 (13 bit)
access : read-write
Enumeration:
#0 : 0
No data transfer.
#1 : 1
1 Byte
#10 : 10
2 Bytes
#11 : 11
3 Bytes
#100 : 100
4 Bytes
#111111111 : 111111111
511 Bytes
#1000000000 : 1000000000
512 Bytes
#100000000000 : 100000000000
2048 Bytes
#1000000000000 : 1000000000000
4096 Bytes
End of enumeration elements list.
BLKCNT : Blocks Count For Current Transfer
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
Stop count.
#1 : 1
1 block
#10 : 10
2 blocks
#1111111111111111 : 1111111111111111
65535 blocks
End of enumeration elements list.
Host Controller Capabilities
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MBL : Max Block Length
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
#000 : 000
512 bytes
#001 : 001
1024 bytes
#010 : 010
2048 bytes
#011 : 011
4096 bytes
End of enumeration elements list.
ADMAS : ADMA Support
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
Advanced DMA not supported.
#1 : 1
Advanced DMA supported.
End of enumeration elements list.
HSS : High Speed Support
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
High speed not supported.
#1 : 1
High speed supported.
End of enumeration elements list.
DMAS : DMA Support
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
DMA not supported.
#1 : 1
DMA supported.
End of enumeration elements list.
SRS : Suspend/Resume Support
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not supported.
#1 : 1
Supported.
End of enumeration elements list.
VS33 : Voltage Support 3.3 V
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
3.3 V not supported.
#1 : 1
3.3 V supported.
End of enumeration elements list.
VS30 : Voltage Support 3.0 V
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
3.0 V not supported.
#1 : 1
3.0 V supported.
End of enumeration elements list.
VS18 : Voltage Support 1.8 V
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
1.8 V not supported.
#1 : 1
1.8 V supported.
End of enumeration elements list.
Watermark Level Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDWML : Read Watermark Level
bits : 0 - 7 (8 bit)
access : read-write
WRWML : Write Watermark Level
bits : 16 - 23 (8 bit)
access : read-write
Force Event register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
AC12NE : Force Event Auto Command 12 Not Executed
bits : 0 - 0 (1 bit)
access : write-only
AC12TOE : Force Event Auto Command 12 Time Out Error
bits : 1 - 1 (1 bit)
access : write-only
AC12CE : Force Event Auto Command 12 CRC Error
bits : 2 - 2 (1 bit)
access : write-only
AC12EBE : Force Event Auto Command 12 End Bit Error
bits : 3 - 3 (1 bit)
access : write-only
AC12IE : Force Event Auto Command 12 Index Error
bits : 4 - 4 (1 bit)
access : write-only
CNIBAC12E : Force Event Command Not Executed By Auto Command 12 Error
bits : 7 - 7 (1 bit)
access : write-only
CTOE : Force Event Command Time Out Error
bits : 16 - 16 (1 bit)
access : write-only
CCE : Force Event Command CRC Error
bits : 17 - 17 (1 bit)
access : write-only
CEBE : Force Event Command End Bit Error
bits : 18 - 18 (1 bit)
access : write-only
CIE : Force Event Command Index Error
bits : 19 - 19 (1 bit)
access : write-only
DTOE : Force Event Data Time Out Error
bits : 20 - 20 (1 bit)
access : write-only
DCE : Force Event Data CRC Error
bits : 21 - 21 (1 bit)
access : write-only
DEBE : Force Event Data End Bit Error
bits : 22 - 22 (1 bit)
access : write-only
AC12E : Force Event Auto Command 12 Error
bits : 24 - 24 (1 bit)
access : write-only
DMAE : Force Event DMA Error
bits : 28 - 28 (1 bit)
access : write-only
CINT : Force Event Card Interrupt
bits : 31 - 31 (1 bit)
access : write-only
ADMA Error Status register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADMAES : ADMA Error State (When ADMA Error Is Occurred.)
bits : 0 - 1 (2 bit)
access : read-only
ADMALME : ADMA Length Mismatch Error
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error.
#1 : 1
Error.
End of enumeration elements list.
ADMADCE : ADMA Descriptor Error
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error.
#1 : 1
Error.
End of enumeration elements list.
ADMA System Addressregister
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADSADDR : ADMA System Address
bits : 2 - 31 (30 bit)
access : read-write
Command Argument register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDARG : Command Argument
bits : 0 - 31 (32 bit)
access : read-write
Transfer Type register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
BCEN : Block Count Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
AC12EN : Auto CMD12 Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
DTDSEL : Data Transfer Direction Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write host to card.
#1 : 1
Read card to host.
End of enumeration elements list.
MSBSEL : Multi/Single Block Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single block.
#1 : 1
Multiple blocks.
End of enumeration elements list.
RSPTYP : Response Type Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
No response.
#01 : 01
Response length 136.
#10 : 10
Response length 48.
#11 : 11
Response length 48, check busy after response.
End of enumeration elements list.
CCCEN : Command CRC Check Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
CICEN : Command Index Check Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
DPSEL : Data Present Select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No data present.
#1 : 1
Data present.
End of enumeration elements list.
CMDTYP : Command Type
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
Normal other commands.
#01 : 01
Suspend CMD52 for writing bus suspend in CCCR.
#10 : 10
Resume CMD52 for writing function select in CCCR.
#11 : 11
Abort CMD12, CMD52 for writing I/O abort in CCCR.
End of enumeration elements list.
CMDINX : Command Index
bits : 24 - 29 (6 bit)
access : read-write
Vendor Specific register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTDMAEN : External DMA Request Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
In any scenario, SDHC does not send out the external DMA request.
#1 : 1
When internal DMA is not active, the external DMA request will be sent out.
End of enumeration elements list.
EXBLKNU : Exact Block Number Block Read Enable For SDIO CMD53
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
None exact block read.
#1 : 1
Exact block read for SDIO CMD53.
End of enumeration elements list.
INTSTVAL : Internal State Value
bits : 16 - 23 (8 bit)
access : read-only
MMC Boot register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTOCVACK : Boot ACK Time Out Counter Value
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
SDCLK x 2^8
#0001 : 0001
SDCLK x 2^9
#0010 : 0010
SDCLK x 2^10
#0011 : 0011
SDCLK x 2^11
#0100 : 0100
SDCLK x 2^12
#0101 : 0101
SDCLK x 2^13
#0110 : 0110
SDCLK x 2^14
#0111 : 0111
SDCLK x 2^15
#1110 : 1110
SDCLK x 2^22
End of enumeration elements list.
BOOTACK : Boot Ack Mode Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ack.
#1 : 1
Ack.
End of enumeration elements list.
BOOTMODE : Boot Mode Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal boot.
#1 : 1
Alternative boot.
End of enumeration elements list.
BOOTEN : Boot Mode Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast boot disable.
#1 : 1
Fast boot enable.
End of enumeration elements list.
AUTOSABGEN : When boot, enable auto stop at block gap function
bits : 7 - 7 (1 bit)
access : read-write
BOOTBLKCNT : Defines the stop at block gap value of automatic mode
bits : 16 - 31 (16 bit)
access : read-write
Host Controller Version
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SVN : Specification Version Number
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
#1 : 1
SD host specification version 2.0, supports test event register and ADMA.
End of enumeration elements list.
VVN : Vendor Version Number
bits : 8 - 15 (8 bit)
access : read-only
Enumeration:
#0 : 0
Freescale SDHC version 1.0
#10000 : 10000
Freescale SDHC version 2.0
#10001 : 10001
Freescale SDHC version 2.1
#10010 : 10010
Freescale SDHC version 2.2
End of enumeration elements list.
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