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MCM

Peripheral Memory Blocks

address_offset : 0x8 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISR

ETBCC

ETBRL

ETBCNT

PID

PLASC

PLAMC

CR


ISR

Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ NMI DHREQ

IRQ : Normal Interrupt Pending
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No pending interrupt

#1 : 1

Due to the ETB counter expiring, a normal interrupt is pending

End of enumeration elements list.

NMI : Non-maskable Interrupt Pending
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No pending NMI

#1 : 1

Due to the ETB counter expiring, an NMI is pending

End of enumeration elements list.

DHREQ : Debug Halt Request Indicator
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

No debug halt request

#1 : 1

Debug halt request initiated

End of enumeration elements list.


ETBCC

ETB Counter Control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETBCC ETBCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTEN RSPT RLRQ ETDIS ITDIS

CNTEN : Counter Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

ETB counter disabled

#1 : 1

ETB counter enabled

End of enumeration elements list.

RSPT : Response Type
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

No response when the ETB count expires

#01 : 01

Generate a normal interrupt when the ETB count expires

#10 : 10

Generate an NMI when the ETB count expires

#11 : 11

Generate a debug halt when the ETB count expires

End of enumeration elements list.

RLRQ : Reload Request
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clears pending debug halt, NMI, or IRQ interrupt requests

End of enumeration elements list.

ETDIS : ETM-To-TPIU Disable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

ETM-to-TPIU trace path enabled

#1 : 1

ETM-to-TPIU trace path disabled

End of enumeration elements list.

ITDIS : ITM-To-TPIU Disable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

ITM-to-TPIU trace path enabled

#1 : 1

ITM-to-TPIU trace path disabled

End of enumeration elements list.


ETBRL

ETB Reload register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETBRL ETBRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELOAD

RELOAD : Byte Count Reload Value
bits : 0 - 10 (11 bit)
access : read-write


ETBCNT

ETB Counter Value register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETBCNT ETBCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNTER

COUNTER : Byte Count Counter Value
bits : 0 - 10 (11 bit)
access : read-only


PID

Process ID register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID PID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : M0_PID And M1_PID For MPU
bits : 0 - 7 (8 bit)
access : read-write


PLASC

Crossbar Switch (AXBS) Slave Configuration
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLASC PLASC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASC

ASC : Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

#0 : 0

A bus slave connection to AXBS input port n is absent

#1 : 1

A bus slave connection to AXBS input port n is present

End of enumeration elements list.


PLAMC

Crossbar Switch (AXBS) Master Configuration
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLAMC PLAMC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMC

AMC : Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

#0 : 0

A bus master connection to AXBS input port n is absent

#1 : 1

A bus master connection to AXBS input port n is present

End of enumeration elements list.


CR

Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAMUAP SRAMUWP SRAMLAP SRAMLWP

SRAMUAP : SRAM_U arbitration priority
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Round robin

#01 : 01

Special round robin (favors SRAM backoor accesses over the processor)

#10 : 10

Fixed priority. Processor has highest, backdoor has lowest

#11 : 11

Fixed priority. Backdoor has highest, processor has lowest

End of enumeration elements list.

SRAMUWP : SRAM_U write protect
bits : 26 - 26 (1 bit)
access : read-write

SRAMLAP : SRAM_L arbitration priority
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 00

Round robin

#01 : 01

Special round robin (favors SRAM backoor accesses over the processor)

#10 : 10

Fixed priority. Processor has highest, backdoor has lowest

#11 : 11

Fixed priority. Backdoor has highest, processor has lowest

End of enumeration elements list.

SRAMLWP : SRAM_L Write Protect
bits : 30 - 30 (1 bit)
access : read-write



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