\n
address_offset : 0x8 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ : Normal interrupt pending
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No pending interrupt
#1 : 1
Due to the ETB counter expiring, a normal interrupt is pending
End of enumeration elements list.
NMI : Non-maskable interrupt pending
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No pending NMI
#1 : 1
Due to the ETB counter expiring, an NMI is pending
End of enumeration elements list.
ETB counter control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN : Counter enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ETB counter disabled
#1 : 1
ETB counter enabled
End of enumeration elements list.
RSPT : Response type
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 00
No response when the ETB count expires
#01 : 01
Generate a normal interrupt when the ETB count expires
#10 : 10
Generate an NMI when the ETB count expires
#11 : 11
Generate a debug halt when the ETB count expires
End of enumeration elements list.
RLRQ : Reload request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clears pending debug halt, NMI, or IRQ interrupt requests
End of enumeration elements list.
ETDIS : ETM-to-TPIU disable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
ETM-to-TPIU trace path enabled
#1 : 1
ETM-to-TPIU trace path disabled
End of enumeration elements list.
ITDIS : ITM-to-TPIU disable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
ITM-to-TPIU trace path enabled
#1 : 1
ITM-to-TPIU trace path disabled
End of enumeration elements list.
ETB reload register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : Byte count reload value
bits : 0 - 10 (11 bit)
access : read-write
ETB counter value register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNTER : Byte count counter value
bits : 0 - 10 (11 bit)
access : read-only
Crossbar switch (AXBS) slave configuration
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ASC : Each bit in the ASC field indicates if there is a corresponding connection to the crossbar switch's slave input port.
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
#0 : 0
A bus slave connection to AXBS input port n is absent
#1 : 1
A bus slave connection to AXBS input port n is present
End of enumeration elements list.
Crossbar switch (AXBS) master configuration
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AMC : Each bit in the AMC field indicates if there is a corresponding connection to the AXBS master input port.
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
#0 : 0
A bus master connection to AXBS input port n is absent
#1 : 1
A bus master connection to AXBS input port n is present
End of enumeration elements list.
SRAM arbitration and protection
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAMUAP : SRAM_U arbitration priority
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Round robin
#01 : 01
Special round robin (favors SRAM backoor accesses over the processor)
#10 : 10
Fixed priority. Processor has highest, backdoor has lowest
#11 : 11
Fixed priority. Backdoor has highest, processor has lowest
End of enumeration elements list.
SRAMUWP : SRAM_U write protect
bits : 26 - 26 (1 bit)
access : read-write
SRAMLAP : SRAM_L arbitration priority
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
Round robin
#01 : 01
Special round robin (favors SRAM backoor accesses over the processor)
#10 : 10
Fixed priority. Processor has highest, backdoor has lowest
#11 : 11
Fixed priority. Backdoor has highest, processor has lowest
End of enumeration elements list.
SRAMLWP : SRAM_L write protect
bits : 30 - 30 (1 bit)
access : read-write
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