\n
address_offset : 0x0 Bytes (0x0)
size : 0xC00 byte (0x0)
mem_usage : registers
protection : not protected
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start
bits : 0 - 0 (1 bit)
SUSP : Suspend
bits : 1 - 1 (1 bit)
ABORT : Abort
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 8 - 8 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 9 - 9 (1 bit)
TWIE : Transfer watermark interrupt enable
bits : 10 - 10 (1 bit)
CAEIE : CLUT access error interrupt enable
bits : 11 - 11 (1 bit)
CTCIE : CLUT transfer complete interrupt enable
bits : 12 - 12 (1 bit)
CEIE : Configuration Error Interrupt Enable
bits : 13 - 13 (1 bit)
MODE : DMA2D mode
bits : 16 - 17 (2 bit)
foreground offset register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LO : Line offset
bits : 0 - 13 (14 bit)
background memory address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
background offset register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LO : Line offset
bits : 0 - 13 (14 bit)
foreground PFC control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM : Color mode
bits : 0 - 3 (4 bit)
CCM : CLUT color mode
bits : 4 - 4 (1 bit)
START : Start
bits : 5 - 5 (1 bit)
CS : CLUT size
bits : 8 - 15 (8 bit)
AM : Alpha mode
bits : 16 - 17 (2 bit)
ALPHA : Alpha value
bits : 24 - 31 (8 bit)
foreground color register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLUE : Blue Value
bits : 0 - 7 (8 bit)
GREEN : Green Value
bits : 8 - 15 (8 bit)
RED : Red Value
bits : 16 - 23 (8 bit)
background PFC control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM : Color mode
bits : 0 - 3 (4 bit)
CCM : CLUT Color mode
bits : 4 - 4 (1 bit)
START : Start
bits : 5 - 5 (1 bit)
CS : CLUT size
bits : 8 - 15 (8 bit)
AM : Alpha mode
bits : 16 - 17 (2 bit)
ALPHA : Alpha value
bits : 24 - 31 (8 bit)
background color register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLUE : Blue Value
bits : 0 - 7 (8 bit)
GREEN : Green Value
bits : 8 - 15 (8 bit)
RED : Red Value
bits : 16 - 23 (8 bit)
foreground CLUT memory address register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory Address
bits : 0 - 31 (32 bit)
background CLUT memory address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
output PFC control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM : Color mode
bits : 0 - 2 (3 bit)
output color register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLUE : Blue Value
bits : 0 - 7 (8 bit)
GREEN : Green Value
bits : 8 - 15 (8 bit)
RED : Red Value
bits : 16 - 23 (8 bit)
APLHA : Alpha Channel Value
bits : 24 - 31 (8 bit)
output memory address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory Address
bits : 0 - 31 (32 bit)
Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : Transfer error interrupt flag
bits : 0 - 0 (1 bit)
TCIF : Transfer complete interrupt flag
bits : 1 - 1 (1 bit)
TWIF : Transfer watermark interrupt flag
bits : 2 - 2 (1 bit)
CAEIF : CLUT access error interrupt flag
bits : 3 - 3 (1 bit)
CTCIF : CLUT transfer complete interrupt flag
bits : 4 - 4 (1 bit)
CEIF : Configuration error interrupt flag
bits : 5 - 5 (1 bit)
output offset register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LO : Line Offset
bits : 0 - 13 (14 bit)
FGCLUT
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLUE : BLUE
bits : 0 - 7 (8 bit)
GREEN : GREEN
bits : 8 - 15 (8 bit)
RED : RED
bits : 16 - 23 (8 bit)
APLHA : APLHA
bits : 24 - 31 (8 bit)
number of line register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NL : Number of lines
bits : 0 - 15 (16 bit)
PL : Pixel per lines
bits : 16 - 29 (14 bit)
line watermark register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LW : Line watermark
bits : 0 - 15 (16 bit)
AHB master timer configuration register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
DT : Dead Time
bits : 8 - 15 (8 bit)
interrupt flag clear register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF : Clear Transfer error interrupt flag
bits : 0 - 0 (1 bit)
CTCIF : Clear transfer complete interrupt flag
bits : 1 - 1 (1 bit)
CTWIF : Clear transfer watermark interrupt flag
bits : 2 - 2 (1 bit)
CAECIF : Clear CLUT access error interrupt flag
bits : 3 - 3 (1 bit)
CCTCIF : Clear CLUT transfer complete interrupt flag
bits : 4 - 4 (1 bit)
CCEIF : Clear configuration error interrupt flag
bits : 5 - 5 (1 bit)
BGCLUT
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLUE : BLUE
bits : 0 - 7 (8 bit)
GREEN : GREEN
bits : 8 - 15 (8 bit)
RED : RED
bits : 16 - 23 (8 bit)
APLHA : APLHA
bits : 24 - 31 (8 bit)
foreground memory address register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
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