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CAU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xB6C byte (0x0)
mem_usage : registers
protection : not protected

Registers

DIRECT0

DIRECT4

DIRECT5

DIRECT6

DIRECT7

DIRECT8

DIRECT9

DIRECT10

DIRECT11

DIRECT12

DIRECT13

DIRECT14

DIRECT15

DIRECT1

DIRECT2

LDR_CASR

LDR_CAA

LDR_CA0

LDR_CA1

LDR_CA2

LDR_CA3

LDR_CA4

LDR_CA5

LDR_CA6

LDR_CA7

LDR_CA8

STR_CASR

STR_CAA

STR_CA0

STR_CA1

STR_CA2

STR_CA3

STR_CA4

STR_CA5

STR_CA6

STR_CA7

STR_CA8

ADR_CASR

ADR_CAA

ADR_CA0

ADR_CA1

ADR_CA2

ADR_CA3

ADR_CA4

ADR_CA5

ADR_CA6

ADR_CA7

ADR_CA8

RADR_CASR

RADR_CAA

RADR_CA0

RADR_CA1

RADR_CA2

RADR_CA3

RADR_CA4

RADR_CA5

RADR_CA6

RADR_CA7

RADR_CA8

XOR_CASR

XOR_CAA

XOR_CA0

XOR_CA1

XOR_CA2

XOR_CA3

XOR_CA4

XOR_CA5

XOR_CA6

XOR_CA7

XOR_CA8

ROTL_CASR

ROTL_CAA

ROTL_CA0

ROTL_CA1

ROTL_CA2

ROTL_CA3

ROTL_CA4

ROTL_CA5

ROTL_CA6

ROTL_CA7

ROTL_CA8

AESC_CASR

AESC_CAA

AESC_CA0

AESC_CA1

AESC_CA2

AESC_CA3

AESC_CA4

AESC_CA5

AESC_CA6

AESC_CA7

AESC_CA8

AESIC_CASR

AESIC_CAA

AESIC_CA0

AESIC_CA1

AESIC_CA2

AESIC_CA3

AESIC_CA4

AESIC_CA5

AESIC_CA6

AESIC_CA7

AESIC_CA8

DIRECT3


DIRECT0

Direct access register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT0 DIRECT0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT0

CAU_DIRECT0 : Direct register 0
bits : 0 - 31 (32 bit)
access : write-only


DIRECT4

Direct access register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT4 DIRECT4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT4

CAU_DIRECT4 : Direct register 4
bits : 0 - 31 (32 bit)
access : write-only


DIRECT5

Direct access register 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT5 DIRECT5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT5

CAU_DIRECT5 : Direct register 5
bits : 0 - 31 (32 bit)
access : write-only


DIRECT6

Direct access register 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT6 DIRECT6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT6

CAU_DIRECT6 : Direct register 6
bits : 0 - 31 (32 bit)
access : write-only


DIRECT7

Direct access register 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT7 DIRECT7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT7

CAU_DIRECT7 : Direct register 7
bits : 0 - 31 (32 bit)
access : write-only


DIRECT8

Direct access register 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT8 DIRECT8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT8

CAU_DIRECT8 : Direct register 8
bits : 0 - 31 (32 bit)
access : write-only


DIRECT9

Direct access register 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT9 DIRECT9 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT9

CAU_DIRECT9 : Direct register 9
bits : 0 - 31 (32 bit)
access : write-only


DIRECT10

Direct access register 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT10 DIRECT10 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT10

CAU_DIRECT10 : Direct register 10
bits : 0 - 31 (32 bit)
access : write-only


DIRECT11

Direct access register 11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT11 DIRECT11 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT11

CAU_DIRECT11 : Direct register 11
bits : 0 - 31 (32 bit)
access : write-only


DIRECT12

Direct access register 12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT12 DIRECT12 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT12

CAU_DIRECT12 : Direct register 12
bits : 0 - 31 (32 bit)
access : write-only


DIRECT13

Direct access register 13
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT13 DIRECT13 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT13

CAU_DIRECT13 : Direct register 13
bits : 0 - 31 (32 bit)
access : write-only


DIRECT14

Direct access register 14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT14 DIRECT14 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT14

CAU_DIRECT14 : Direct register 14
bits : 0 - 31 (32 bit)
access : write-only


DIRECT15

Direct access register 15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT15 DIRECT15 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT15

CAU_DIRECT15 : Direct register 15
bits : 0 - 31 (32 bit)
access : write-only


DIRECT1

Direct access register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT1 DIRECT1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT1

CAU_DIRECT1 : Direct register 1
bits : 0 - 31 (32 bit)
access : write-only


DIRECT2

Direct access register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT2 DIRECT2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT2

CAU_DIRECT2 : Direct register 2
bits : 0 - 31 (32 bit)
access : write-only


LDR_CASR

Status register - Load Register command
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LDR_CASR LDR_CASR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC DPE VER

IC : no description available
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

No illegal commands issued

#1 : 1

Illegal command issued

End of enumeration elements list.

DPE : no description available
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

#0 : 0

No error detected

#1 : 1

DES key parity error detected

End of enumeration elements list.

VER : CAU version
bits : 28 - 31 (4 bit)
access : write-only

Enumeration:

#0001 : 0001

Initial CAU version

#0010 : 0010

Second version, added support for SHA-256 algorithm.(This is the value on this device)

End of enumeration elements list.


LDR_CAA

Accumulator register - Load Register command
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LDR_CAA LDR_CAA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC

ACC : ACC
bits : 0 - 31 (32 bit)
access : write-only


LDR_CA0

General Purpose Register 0 - Load Register command
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LDR_CA0 LDR_CA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA0

CA0 : CA0
bits : 0 - 31 (32 bit)
access : write-only


LDR_CA1

General Purpose Register 1 - Load Register command
address_offset : 0x84C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LDR_CA1 LDR_CA1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA1

CA1 : CA1
bits : 0 - 31 (32 bit)
access : write-only


LDR_CA2

General Purpose Register 2 - Load Register command
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LDR_CA2 LDR_CA2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA2

CA2 : CA2
bits : 0 - 31 (32 bit)
access : write-only


LDR_CA3

General Purpose Register 3 - Load Register command
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LDR_CA3 LDR_CA3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA3

CA3 : CA3
bits : 0 - 31 (32 bit)
access : write-only


LDR_CA4

General Purpose Register 4 - Load Register command
address_offset : 0x858 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LDR_CA4 LDR_CA4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA4

CA4 : CA4
bits : 0 - 31 (32 bit)
access : write-only


LDR_CA5

General Purpose Register 5 - Load Register command
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LDR_CA5 LDR_CA5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA5

CA5 : CA5
bits : 0 - 31 (32 bit)
access : write-only


LDR_CA6

General Purpose Register 6 - Load Register command
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LDR_CA6 LDR_CA6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA6

CA6 : CA6
bits : 0 - 31 (32 bit)
access : write-only


LDR_CA7

General Purpose Register 7 - Load Register command
address_offset : 0x864 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LDR_CA7 LDR_CA7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA7

CA7 : CA7
bits : 0 - 31 (32 bit)
access : write-only


LDR_CA8

General Purpose Register 8 - Load Register command
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LDR_CA8 LDR_CA8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA8

CA8 : CA8
bits : 0 - 31 (32 bit)
access : write-only


STR_CASR

Status register - Store Register command
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR_CASR STR_CASR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC DPE VER

IC : no description available
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

No illegal commands issued

#1 : 1

Illegal command issued

End of enumeration elements list.

DPE : no description available
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

No error detected

#1 : 1

DES key parity error detected

End of enumeration elements list.

VER : CAU version
bits : 28 - 31 (4 bit)
access : read-only

Enumeration:

#0001 : 0001

Initial CAU version

#0010 : 0010

Second version, added support for SHA-256 algorithm.(This is the value on this device)

End of enumeration elements list.


STR_CAA

Accumulator register - Store Register command
address_offset : 0x884 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR_CAA STR_CAA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC

ACC : ACC
bits : 0 - 31 (32 bit)
access : read-only


STR_CA0

General Purpose Register 0 - Store Register command
address_offset : 0x888 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR_CA0 STR_CA0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA0

CA0 : CA0
bits : 0 - 31 (32 bit)
access : read-only


STR_CA1

General Purpose Register 1 - Store Register command
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR_CA1 STR_CA1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA1

CA1 : CA1
bits : 0 - 31 (32 bit)
access : read-only


STR_CA2

General Purpose Register 2 - Store Register command
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR_CA2 STR_CA2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA2

CA2 : CA2
bits : 0 - 31 (32 bit)
access : read-only


STR_CA3

General Purpose Register 3 - Store Register command
address_offset : 0x894 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR_CA3 STR_CA3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA3

CA3 : CA3
bits : 0 - 31 (32 bit)
access : read-only


STR_CA4

General Purpose Register 4 - Store Register command
address_offset : 0x898 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR_CA4 STR_CA4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA4

CA4 : CA4
bits : 0 - 31 (32 bit)
access : read-only


STR_CA5

General Purpose Register 5 - Store Register command
address_offset : 0x89C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR_CA5 STR_CA5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA5

CA5 : CA5
bits : 0 - 31 (32 bit)
access : read-only


STR_CA6

General Purpose Register 6 - Store Register command
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR_CA6 STR_CA6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA6

CA6 : CA6
bits : 0 - 31 (32 bit)
access : read-only


STR_CA7

General Purpose Register 7 - Store Register command
address_offset : 0x8A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR_CA7 STR_CA7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA7

CA7 : CA7
bits : 0 - 31 (32 bit)
access : read-only


STR_CA8

General Purpose Register 8 - Store Register command
address_offset : 0x8A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STR_CA8 STR_CA8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA8

CA8 : CA8
bits : 0 - 31 (32 bit)
access : read-only


ADR_CASR

Status register - Add Register command
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADR_CASR ADR_CASR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC DPE VER

IC : no description available
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

No illegal commands issued

#1 : 1

Illegal command issued

End of enumeration elements list.

DPE : no description available
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

#0 : 0

No error detected

#1 : 1

DES key parity error detected

End of enumeration elements list.

VER : CAU version
bits : 28 - 31 (4 bit)
access : write-only

Enumeration:

#0001 : 0001

Initial CAU version

#0010 : 0010

Second version, added support for SHA-256 algorithm.(This is the value on this device)

End of enumeration elements list.


ADR_CAA

Accumulator register - Add to register command
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADR_CAA ADR_CAA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC

ACC : ACC
bits : 0 - 31 (32 bit)
access : write-only


ADR_CA0

General Purpose Register 0 - Add to register command
address_offset : 0x8C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADR_CA0 ADR_CA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA0

CA0 : CA0
bits : 0 - 31 (32 bit)
access : write-only


ADR_CA1

General Purpose Register 1 - Add to register command
address_offset : 0x8CC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADR_CA1 ADR_CA1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA1

CA1 : CA1
bits : 0 - 31 (32 bit)
access : write-only


ADR_CA2

General Purpose Register 2 - Add to register command
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADR_CA2 ADR_CA2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA2

CA2 : CA2
bits : 0 - 31 (32 bit)
access : write-only


ADR_CA3

General Purpose Register 3 - Add to register command
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADR_CA3 ADR_CA3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA3

CA3 : CA3
bits : 0 - 31 (32 bit)
access : write-only


ADR_CA4

General Purpose Register 4 - Add to register command
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADR_CA4 ADR_CA4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA4

CA4 : CA4
bits : 0 - 31 (32 bit)
access : write-only


ADR_CA5

General Purpose Register 5 - Add to register command
address_offset : 0x8DC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADR_CA5 ADR_CA5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA5

CA5 : CA5
bits : 0 - 31 (32 bit)
access : write-only


ADR_CA6

General Purpose Register 6 - Add to register command
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADR_CA6 ADR_CA6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA6

CA6 : CA6
bits : 0 - 31 (32 bit)
access : write-only


ADR_CA7

General Purpose Register 7 - Add to register command
address_offset : 0x8E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADR_CA7 ADR_CA7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA7

CA7 : CA7
bits : 0 - 31 (32 bit)
access : write-only


ADR_CA8

General Purpose Register 8 - Add to register command
address_offset : 0x8E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADR_CA8 ADR_CA8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA8

CA8 : CA8
bits : 0 - 31 (32 bit)
access : write-only


RADR_CASR

Status register - Reverse and Add to Register command
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RADR_CASR RADR_CASR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC DPE VER

IC : no description available
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

No illegal commands issued

#1 : 1

Illegal command issued

End of enumeration elements list.

DPE : no description available
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

#0 : 0

No error detected

#1 : 1

DES key parity error detected

End of enumeration elements list.

VER : CAU version
bits : 28 - 31 (4 bit)
access : write-only

Enumeration:

#0001 : 0001

Initial CAU version

#0010 : 0010

Second version, added support for SHA-256 algorithm.(This is the value on this device)

End of enumeration elements list.


RADR_CAA

Accumulator register - Reverse and Add to Register command
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RADR_CAA RADR_CAA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC

ACC : ACC
bits : 0 - 31 (32 bit)
access : write-only


RADR_CA0

General Purpose Register 0 - Reverse and Add to Register command
address_offset : 0x908 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RADR_CA0 RADR_CA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA0

CA0 : CA0
bits : 0 - 31 (32 bit)
access : write-only


RADR_CA1

General Purpose Register 1 - Reverse and Add to Register command
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RADR_CA1 RADR_CA1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA1

CA1 : CA1
bits : 0 - 31 (32 bit)
access : write-only


RADR_CA2

General Purpose Register 2 - Reverse and Add to Register command
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RADR_CA2 RADR_CA2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA2

CA2 : CA2
bits : 0 - 31 (32 bit)
access : write-only


RADR_CA3

General Purpose Register 3 - Reverse and Add to Register command
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RADR_CA3 RADR_CA3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA3

CA3 : CA3
bits : 0 - 31 (32 bit)
access : write-only


RADR_CA4

General Purpose Register 4 - Reverse and Add to Register command
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RADR_CA4 RADR_CA4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA4

CA4 : CA4
bits : 0 - 31 (32 bit)
access : write-only


RADR_CA5

General Purpose Register 5 - Reverse and Add to Register command
address_offset : 0x91C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RADR_CA5 RADR_CA5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA5

CA5 : CA5
bits : 0 - 31 (32 bit)
access : write-only


RADR_CA6

General Purpose Register 6 - Reverse and Add to Register command
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RADR_CA6 RADR_CA6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA6

CA6 : CA6
bits : 0 - 31 (32 bit)
access : write-only


RADR_CA7

General Purpose Register 7 - Reverse and Add to Register command
address_offset : 0x924 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RADR_CA7 RADR_CA7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA7

CA7 : CA7
bits : 0 - 31 (32 bit)
access : write-only


RADR_CA8

General Purpose Register 8 - Reverse and Add to Register command
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RADR_CA8 RADR_CA8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA8

CA8 : CA8
bits : 0 - 31 (32 bit)
access : write-only


XOR_CASR

Status register - Exclusive Or command
address_offset : 0x980 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

XOR_CASR XOR_CASR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC DPE VER

IC : no description available
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

No illegal commands issued

#1 : 1

Illegal command issued

End of enumeration elements list.

DPE : no description available
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

#0 : 0

No error detected

#1 : 1

DES key parity error detected

End of enumeration elements list.

VER : CAU version
bits : 28 - 31 (4 bit)
access : write-only

Enumeration:

#0001 : 0001

Initial CAU version

#0010 : 0010

Second version, added support for SHA-256 algorithm.(This is the value on this device)

End of enumeration elements list.


XOR_CAA

Accumulator register - Exclusive Or command
address_offset : 0x984 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

XOR_CAA XOR_CAA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC

ACC : ACC
bits : 0 - 31 (32 bit)
access : write-only


XOR_CA0

General Purpose Register 0 - Exclusive Or command
address_offset : 0x988 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

XOR_CA0 XOR_CA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA0

CA0 : CA0
bits : 0 - 31 (32 bit)
access : write-only


XOR_CA1

General Purpose Register 1 - Exclusive Or command
address_offset : 0x98C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

XOR_CA1 XOR_CA1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA1

CA1 : CA1
bits : 0 - 31 (32 bit)
access : write-only


XOR_CA2

General Purpose Register 2 - Exclusive Or command
address_offset : 0x990 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

XOR_CA2 XOR_CA2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA2

CA2 : CA2
bits : 0 - 31 (32 bit)
access : write-only


XOR_CA3

General Purpose Register 3 - Exclusive Or command
address_offset : 0x994 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

XOR_CA3 XOR_CA3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA3

CA3 : CA3
bits : 0 - 31 (32 bit)
access : write-only


XOR_CA4

General Purpose Register 4 - Exclusive Or command
address_offset : 0x998 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

XOR_CA4 XOR_CA4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA4

CA4 : CA4
bits : 0 - 31 (32 bit)
access : write-only


XOR_CA5

General Purpose Register 5 - Exclusive Or command
address_offset : 0x99C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

XOR_CA5 XOR_CA5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA5

CA5 : CA5
bits : 0 - 31 (32 bit)
access : write-only


XOR_CA6

General Purpose Register 6 - Exclusive Or command
address_offset : 0x9A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

XOR_CA6 XOR_CA6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA6

CA6 : CA6
bits : 0 - 31 (32 bit)
access : write-only


XOR_CA7

General Purpose Register 7 - Exclusive Or command
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

XOR_CA7 XOR_CA7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA7

CA7 : CA7
bits : 0 - 31 (32 bit)
access : write-only


XOR_CA8

General Purpose Register 8 - Exclusive Or command
address_offset : 0x9A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

XOR_CA8 XOR_CA8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA8

CA8 : CA8
bits : 0 - 31 (32 bit)
access : write-only


ROTL_CASR

Status register - Rotate Left command
address_offset : 0x9C0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ROTL_CASR ROTL_CASR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC DPE VER

IC : no description available
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

No illegal commands issued

#1 : 1

Illegal command issued

End of enumeration elements list.

DPE : no description available
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

#0 : 0

No error detected

#1 : 1

DES key parity error detected

End of enumeration elements list.

VER : CAU version
bits : 28 - 31 (4 bit)
access : write-only

Enumeration:

#0001 : 0001

Initial CAU version

#0010 : 0010

Second version, added support for SHA-256 algorithm.(This is the value on this device)

End of enumeration elements list.


ROTL_CAA

Accumulator register - Rotate Left command
address_offset : 0x9C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ROTL_CAA ROTL_CAA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC

ACC : ACC
bits : 0 - 31 (32 bit)
access : write-only


ROTL_CA0

General Purpose Register 0 - Rotate Left command
address_offset : 0x9C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ROTL_CA0 ROTL_CA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA0

CA0 : CA0
bits : 0 - 31 (32 bit)
access : write-only


ROTL_CA1

General Purpose Register 1 - Rotate Left command
address_offset : 0x9CC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ROTL_CA1 ROTL_CA1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA1

CA1 : CA1
bits : 0 - 31 (32 bit)
access : write-only


ROTL_CA2

General Purpose Register 2 - Rotate Left command
address_offset : 0x9D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ROTL_CA2 ROTL_CA2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA2

CA2 : CA2
bits : 0 - 31 (32 bit)
access : write-only


ROTL_CA3

General Purpose Register 3 - Rotate Left command
address_offset : 0x9D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ROTL_CA3 ROTL_CA3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA3

CA3 : CA3
bits : 0 - 31 (32 bit)
access : write-only


ROTL_CA4

General Purpose Register 4 - Rotate Left command
address_offset : 0x9D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ROTL_CA4 ROTL_CA4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA4

CA4 : CA4
bits : 0 - 31 (32 bit)
access : write-only


ROTL_CA5

General Purpose Register 5 - Rotate Left command
address_offset : 0x9DC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ROTL_CA5 ROTL_CA5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA5

CA5 : CA5
bits : 0 - 31 (32 bit)
access : write-only


ROTL_CA6

General Purpose Register 6 - Rotate Left command
address_offset : 0x9E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ROTL_CA6 ROTL_CA6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA6

CA6 : CA6
bits : 0 - 31 (32 bit)
access : write-only


ROTL_CA7

General Purpose Register 7 - Rotate Left command
address_offset : 0x9E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ROTL_CA7 ROTL_CA7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA7

CA7 : CA7
bits : 0 - 31 (32 bit)
access : write-only


ROTL_CA8

General Purpose Register 8 - Rotate Left command
address_offset : 0x9E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ROTL_CA8 ROTL_CA8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA8

CA8 : CA8
bits : 0 - 31 (32 bit)
access : write-only


AESC_CASR

Status register - AES Column Operation command
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESC_CASR AESC_CASR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC DPE VER

IC : no description available
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

No illegal commands issued

#1 : 1

Illegal command issued

End of enumeration elements list.

DPE : no description available
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

#0 : 0

No error detected

#1 : 1

DES key parity error detected

End of enumeration elements list.

VER : CAU version
bits : 28 - 31 (4 bit)
access : write-only

Enumeration:

#0001 : 0001

Initial CAU version

#0010 : 0010

Second version, added support for SHA-256 algorithm.(This is the value on this device)

End of enumeration elements list.


AESC_CAA

Accumulator register - AES Column Operation command
address_offset : 0xB04 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESC_CAA AESC_CAA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC

ACC : ACC
bits : 0 - 31 (32 bit)
access : write-only


AESC_CA0

General Purpose Register 0 - AES Column Operation command
address_offset : 0xB08 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESC_CA0 AESC_CA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA0

CA0 : CA0
bits : 0 - 31 (32 bit)
access : write-only


AESC_CA1

General Purpose Register 1 - AES Column Operation command
address_offset : 0xB0C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESC_CA1 AESC_CA1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA1

CA1 : CA1
bits : 0 - 31 (32 bit)
access : write-only


AESC_CA2

General Purpose Register 2 - AES Column Operation command
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESC_CA2 AESC_CA2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA2

CA2 : CA2
bits : 0 - 31 (32 bit)
access : write-only


AESC_CA3

General Purpose Register 3 - AES Column Operation command
address_offset : 0xB14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESC_CA3 AESC_CA3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA3

CA3 : CA3
bits : 0 - 31 (32 bit)
access : write-only


AESC_CA4

General Purpose Register 4 - AES Column Operation command
address_offset : 0xB18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESC_CA4 AESC_CA4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA4

CA4 : CA4
bits : 0 - 31 (32 bit)
access : write-only


AESC_CA5

General Purpose Register 5 - AES Column Operation command
address_offset : 0xB1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESC_CA5 AESC_CA5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA5

CA5 : CA5
bits : 0 - 31 (32 bit)
access : write-only


AESC_CA6

General Purpose Register 6 - AES Column Operation command
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESC_CA6 AESC_CA6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA6

CA6 : CA6
bits : 0 - 31 (32 bit)
access : write-only


AESC_CA7

General Purpose Register 7 - AES Column Operation command
address_offset : 0xB24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESC_CA7 AESC_CA7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA7

CA7 : CA7
bits : 0 - 31 (32 bit)
access : write-only


AESC_CA8

General Purpose Register 8 - AES Column Operation command
address_offset : 0xB28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESC_CA8 AESC_CA8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA8

CA8 : CA8
bits : 0 - 31 (32 bit)
access : write-only


AESIC_CASR

Status register - AES Inverse Column Operation command
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESIC_CASR AESIC_CASR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC DPE VER

IC : no description available
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

No illegal commands issued

#1 : 1

Illegal command issued

End of enumeration elements list.

DPE : no description available
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

#0 : 0

No error detected

#1 : 1

DES key parity error detected

End of enumeration elements list.

VER : CAU version
bits : 28 - 31 (4 bit)
access : write-only

Enumeration:

#0001 : 0001

Initial CAU version

#0010 : 0010

Second version, added support for SHA-256 algorithm.(This is the value on this device)

End of enumeration elements list.


AESIC_CAA

Accumulator register - AES Inverse Column Operation command
address_offset : 0xB44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESIC_CAA AESIC_CAA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC

ACC : ACC
bits : 0 - 31 (32 bit)
access : write-only


AESIC_CA0

General Purpose Register 0 - AES Inverse Column Operation command
address_offset : 0xB48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESIC_CA0 AESIC_CA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA0

CA0 : CA0
bits : 0 - 31 (32 bit)
access : write-only


AESIC_CA1

General Purpose Register 1 - AES Inverse Column Operation command
address_offset : 0xB4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESIC_CA1 AESIC_CA1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA1

CA1 : CA1
bits : 0 - 31 (32 bit)
access : write-only


AESIC_CA2

General Purpose Register 2 - AES Inverse Column Operation command
address_offset : 0xB50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESIC_CA2 AESIC_CA2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA2

CA2 : CA2
bits : 0 - 31 (32 bit)
access : write-only


AESIC_CA3

General Purpose Register 3 - AES Inverse Column Operation command
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESIC_CA3 AESIC_CA3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA3

CA3 : CA3
bits : 0 - 31 (32 bit)
access : write-only


AESIC_CA4

General Purpose Register 4 - AES Inverse Column Operation command
address_offset : 0xB58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESIC_CA4 AESIC_CA4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA4

CA4 : CA4
bits : 0 - 31 (32 bit)
access : write-only


AESIC_CA5

General Purpose Register 5 - AES Inverse Column Operation command
address_offset : 0xB5C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESIC_CA5 AESIC_CA5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA5

CA5 : CA5
bits : 0 - 31 (32 bit)
access : write-only


AESIC_CA6

General Purpose Register 6 - AES Inverse Column Operation command
address_offset : 0xB60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESIC_CA6 AESIC_CA6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA6

CA6 : CA6
bits : 0 - 31 (32 bit)
access : write-only


AESIC_CA7

General Purpose Register 7 - AES Inverse Column Operation command
address_offset : 0xB64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESIC_CA7 AESIC_CA7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA7

CA7 : CA7
bits : 0 - 31 (32 bit)
access : write-only


AESIC_CA8

General Purpose Register 8 - AES Inverse Column Operation command
address_offset : 0xB68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESIC_CA8 AESIC_CA8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CA8

CA8 : CA8
bits : 0 - 31 (32 bit)
access : write-only


DIRECT3

Direct access register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIRECT3 DIRECT3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_DIRECT3

CAU_DIRECT3 : Direct register 3
bits : 0 - 31 (32 bit)
access : write-only



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