Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected
Chip select address register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base address
bits : 16 - 31 (16 bit)
access : read-write
Chip select control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-write enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes.
#1 : 1
Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-read enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.
#1 : 1
Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-enable mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only.
#1 : 1
The FB_BE n signals are asserted for read and write accesses
End of enumeration elements list.
PS : Port size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port size. Valid data sampled and driven on FB_D[31:0]
#01 : 01
8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1
#10 : 10
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
#11 : 11
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
End of enumeration elements list.
AA : Auto-acknowledge enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No internal FB_TA is asserted. Cycle is terminated externally
#1 : 1
Internal transfer acknowledge is asserted as specified by WS
End of enumeration elements list.
BLS : Byte-lane shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not shifted. Data is left-justfied on FB_AD.
#1 : 1
Shifted. Data is right justified on FB_AD.
End of enumeration elements list.
WS : Wait states
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write address hold or deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn)
#01 : 01
Hold address and attributes two cycles after FB_CSn negates on writes.
#10 : 10
Hold address and attributes three cycles after FB_CSn negates on writes.
#11 : 11
Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0)
End of enumeration elements list.
RDAH : Read address hold or deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
If AA is cleared, 1 cycle. If AA is set, 0 cycles.
#01 : 01
If AA is cleared, 2 cycles. If AA is set, 1 cycle.
#10 : 10
If AA is cleared, 3 cycles. If AA is set, 2 cycles.
#11 : 11
If AA is cleared, 4 cycles. If AA is set, 3 cycles.
End of enumeration elements list.
ASET : Address setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn)
#01 : 01
Assert FB_CSn on second rising clock edge after address is asserted.
#10 : 10
Assert FB_CSn on third rising clock edge after address is asserted.
#11 : 11
Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)
End of enumeration elements list.
EXTS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
FB_TS /FB_ALE asserts for one bus clock cycle
#1 : 1
FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts
End of enumeration elements list.
SWSEN : Secondary wait state enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers
#1 : 1
The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations
End of enumeration elements list.
SWS : Secondary wait states
bits : 26 - 31 (6 bit)
access : read-write
Chip select mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip select invalid
#1 : 1
Chip select valid
End of enumeration elements list.
WP : Write protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Read and write accesses are allowed
#1 : 1
Only read accesses are allowed
End of enumeration elements list.
BAM : Base address mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding address bit is used in chip-select decode
#1 : 1
Corresponding address bit is a don't care in chip-select decode.
End of enumeration elements list.
Chip select address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base address
bits : 16 - 31 (16 bit)
access : read-write
Chip select control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-write enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes.
#1 : 1
Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-read enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.
#1 : 1
Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-enable mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only.
#1 : 1
The FB_BE n signals are asserted for read and write accesses
End of enumeration elements list.
PS : Port size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port size. Valid data sampled and driven on FB_D[31:0]
#01 : 01
8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1
#10 : 10
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
#11 : 11
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
End of enumeration elements list.
AA : Auto-acknowledge enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No internal FB_TA is asserted. Cycle is terminated externally
#1 : 1
Internal transfer acknowledge is asserted as specified by WS
End of enumeration elements list.
BLS : Byte-lane shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not shifted. Data is left-justfied on FB_AD.
#1 : 1
Shifted. Data is right justified on FB_AD.
End of enumeration elements list.
WS : Wait states
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write address hold or deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn)
#01 : 01
Hold address and attributes two cycles after FB_CSn negates on writes.
#10 : 10
Hold address and attributes three cycles after FB_CSn negates on writes.
#11 : 11
Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0)
End of enumeration elements list.
RDAH : Read address hold or deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
If AA is cleared, 1 cycle. If AA is set, 0 cycles.
#01 : 01
If AA is cleared, 2 cycles. If AA is set, 1 cycle.
#10 : 10
If AA is cleared, 3 cycles. If AA is set, 2 cycles.
#11 : 11
If AA is cleared, 4 cycles. If AA is set, 3 cycles.
End of enumeration elements list.
ASET : Address setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn)
#01 : 01
Assert FB_CSn on second rising clock edge after address is asserted.
#10 : 10
Assert FB_CSn on third rising clock edge after address is asserted.
#11 : 11
Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)
End of enumeration elements list.
EXTS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
FB_TS /FB_ALE asserts for one bus clock cycle
#1 : 1
FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts
End of enumeration elements list.
SWSEN : Secondary wait state enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers
#1 : 1
The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations
End of enumeration elements list.
SWS : Secondary wait states
bits : 26 - 31 (6 bit)
access : read-write
Chip select mask register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip select invalid
#1 : 1
Chip select valid
End of enumeration elements list.
WP : Write protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Read and write accesses are allowed
#1 : 1
Only read accesses are allowed
End of enumeration elements list.
BAM : Base address mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding address bit is used in chip-select decode
#1 : 1
Corresponding address bit is a don't care in chip-select decode.
End of enumeration elements list.
Chip select control register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-write enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes.
#1 : 1
Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-read enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.
#1 : 1
Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-enable mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only.
#1 : 1
The FB_BE n signals are asserted for read and write accesses
End of enumeration elements list.
PS : Port size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port size. Valid data sampled and driven on FB_D[31:0]
#01 : 01
8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1
#10 : 10
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
#11 : 11
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
End of enumeration elements list.
AA : Auto-acknowledge enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No internal FB_TA is asserted. Cycle is terminated externally
#1 : 1
Internal transfer acknowledge is asserted as specified by WS
End of enumeration elements list.
BLS : Byte-lane shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not shifted. Data is left-justfied on FB_AD.
#1 : 1
Shifted. Data is right justified on FB_AD.
End of enumeration elements list.
WS : Wait states
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write address hold or deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn)
#01 : 01
Hold address and attributes two cycles after FB_CSn negates on writes.
#10 : 10
Hold address and attributes three cycles after FB_CSn negates on writes.
#11 : 11
Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0)
End of enumeration elements list.
RDAH : Read address hold or deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
If AA is cleared, 1 cycle. If AA is set, 0 cycles.
#01 : 01
If AA is cleared, 2 cycles. If AA is set, 1 cycle.
#10 : 10
If AA is cleared, 3 cycles. If AA is set, 2 cycles.
#11 : 11
If AA is cleared, 4 cycles. If AA is set, 3 cycles.
End of enumeration elements list.
ASET : Address setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn)
#01 : 01
Assert FB_CSn on second rising clock edge after address is asserted.
#10 : 10
Assert FB_CSn on third rising clock edge after address is asserted.
#11 : 11
Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)
End of enumeration elements list.
EXTS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
FB_TS /FB_ALE asserts for one bus clock cycle
#1 : 1
FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts
End of enumeration elements list.
SWSEN : Secondary wait state enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers
#1 : 1
The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations
End of enumeration elements list.
SWS : Secondary wait states
bits : 26 - 31 (6 bit)
access : read-write
Chip select address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base address
bits : 16 - 31 (16 bit)
access : read-write
Chip select mask register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip select invalid
#1 : 1
Chip select valid
End of enumeration elements list.
WP : Write protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Read and write accesses are allowed
#1 : 1
Only read accesses are allowed
End of enumeration elements list.
BAM : Base address mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding address bit is used in chip-select decode
#1 : 1
Corresponding address bit is a don't care in chip-select decode.
End of enumeration elements list.
Chip select port multiplexing control register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GROUP5 : FlexBus signal group 5 multiplex control
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
FB_TA
#0001 : 0001
FB_CS3. You must also set CSCRn[AA].
#0010 : 0010
FB_BE_7_0. You must also set CSCRn[AA].
End of enumeration elements list.
GROUP4 : FlexBus signal group 4 multiplex control
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
FB_TBST
#0001 : 0001
FB_CS2
#0010 : 0010
FB_BE_15_8
End of enumeration elements list.
GROUP3 : FlexBus signal group 3 multiplex control
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
FB_CS5
#0001 : 0001
FB_TSIZ1
#0010 : 0010
FB_BE_23_16
End of enumeration elements list.
GROUP2 : FlexBus signal group 2 multiplex control
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
FB_CS4
#0001 : 0001
FB_TSIZ0
#0010 : 0010
FB_BE_31_24
End of enumeration elements list.
GROUP1 : FlexBus signal group 1 multiplex control
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
FB_ALE
#0001 : 0001
FB_CS1
#0010 : 0010
FB_TS
End of enumeration elements list.
Chip select control register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-write enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes.
#1 : 1
Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-read enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.
#1 : 1
Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-enable mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only.
#1 : 1
The FB_BE n signals are asserted for read and write accesses
End of enumeration elements list.
PS : Port size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port size. Valid data sampled and driven on FB_D[31:0]
#01 : 01
8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1
#10 : 10
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
#11 : 11
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
End of enumeration elements list.
AA : Auto-acknowledge enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No internal FB_TA is asserted. Cycle is terminated externally
#1 : 1
Internal transfer acknowledge is asserted as specified by WS
End of enumeration elements list.
BLS : Byte-lane shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not shifted. Data is left-justfied on FB_AD.
#1 : 1
Shifted. Data is right justified on FB_AD.
End of enumeration elements list.
WS : Wait states
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write address hold or deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn)
#01 : 01
Hold address and attributes two cycles after FB_CSn negates on writes.
#10 : 10
Hold address and attributes three cycles after FB_CSn negates on writes.
#11 : 11
Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0)
End of enumeration elements list.
RDAH : Read address hold or deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
If AA is cleared, 1 cycle. If AA is set, 0 cycles.
#01 : 01
If AA is cleared, 2 cycles. If AA is set, 1 cycle.
#10 : 10
If AA is cleared, 3 cycles. If AA is set, 2 cycles.
#11 : 11
If AA is cleared, 4 cycles. If AA is set, 3 cycles.
End of enumeration elements list.
ASET : Address setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn)
#01 : 01
Assert FB_CSn on second rising clock edge after address is asserted.
#10 : 10
Assert FB_CSn on third rising clock edge after address is asserted.
#11 : 11
Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)
End of enumeration elements list.
EXTS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
FB_TS /FB_ALE asserts for one bus clock cycle
#1 : 1
FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts
End of enumeration elements list.
SWSEN : Secondary wait state enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers
#1 : 1
The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations
End of enumeration elements list.
SWS : Secondary wait states
bits : 26 - 31 (6 bit)
access : read-write
Chip select address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base address
bits : 16 - 31 (16 bit)
access : read-write
Chip select mask register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip select invalid
#1 : 1
Chip select valid
End of enumeration elements list.
WP : Write protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Read and write accesses are allowed
#1 : 1
Only read accesses are allowed
End of enumeration elements list.
BAM : Base address mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding address bit is used in chip-select decode
#1 : 1
Corresponding address bit is a don't care in chip-select decode.
End of enumeration elements list.
Chip select mask register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip select invalid
#1 : 1
Chip select valid
End of enumeration elements list.
WP : Write protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Read and write accesses are allowed
#1 : 1
Only read accesses are allowed
End of enumeration elements list.
BAM : Base address mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding address bit is used in chip-select decode
#1 : 1
Corresponding address bit is a don't care in chip-select decode.
End of enumeration elements list.
Chip select control register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-write enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes.
#1 : 1
Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-read enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.
#1 : 1
Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-enable mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only.
#1 : 1
The FB_BE n signals are asserted for read and write accesses
End of enumeration elements list.
PS : Port size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port size. Valid data sampled and driven on FB_D[31:0]
#01 : 01
8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1
#10 : 10
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
#11 : 11
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
End of enumeration elements list.
AA : Auto-acknowledge enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No internal FB_TA is asserted. Cycle is terminated externally
#1 : 1
Internal transfer acknowledge is asserted as specified by WS
End of enumeration elements list.
BLS : Byte-lane shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not shifted. Data is left-justfied on FB_AD.
#1 : 1
Shifted. Data is right justified on FB_AD.
End of enumeration elements list.
WS : Wait states
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write address hold or deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn)
#01 : 01
Hold address and attributes two cycles after FB_CSn negates on writes.
#10 : 10
Hold address and attributes three cycles after FB_CSn negates on writes.
#11 : 11
Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0)
End of enumeration elements list.
RDAH : Read address hold or deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
If AA is cleared, 1 cycle. If AA is set, 0 cycles.
#01 : 01
If AA is cleared, 2 cycles. If AA is set, 1 cycle.
#10 : 10
If AA is cleared, 3 cycles. If AA is set, 2 cycles.
#11 : 11
If AA is cleared, 4 cycles. If AA is set, 3 cycles.
End of enumeration elements list.
ASET : Address setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn)
#01 : 01
Assert FB_CSn on second rising clock edge after address is asserted.
#10 : 10
Assert FB_CSn on third rising clock edge after address is asserted.
#11 : 11
Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)
End of enumeration elements list.
EXTS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
FB_TS /FB_ALE asserts for one bus clock cycle
#1 : 1
FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts
End of enumeration elements list.
SWSEN : Secondary wait state enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers
#1 : 1
The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations
End of enumeration elements list.
SWS : Secondary wait states
bits : 26 - 31 (6 bit)
access : read-write
Chip select address register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base address
bits : 16 - 31 (16 bit)
access : read-write
Chip select address register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base address
bits : 16 - 31 (16 bit)
access : read-write
Chip select mask register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip select invalid
#1 : 1
Chip select valid
End of enumeration elements list.
WP : Write protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Read and write accesses are allowed
#1 : 1
Only read accesses are allowed
End of enumeration elements list.
BAM : Base address mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding address bit is used in chip-select decode
#1 : 1
Corresponding address bit is a don't care in chip-select decode.
End of enumeration elements list.
Chip select control register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-write enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes.
#1 : 1
Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-read enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.
#1 : 1
Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-enable mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only.
#1 : 1
The FB_BE n signals are asserted for read and write accesses
End of enumeration elements list.
PS : Port size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port size. Valid data sampled and driven on FB_D[31:0]
#01 : 01
8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1
#10 : 10
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
#11 : 11
16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1
End of enumeration elements list.
AA : Auto-acknowledge enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No internal FB_TA is asserted. Cycle is terminated externally
#1 : 1
Internal transfer acknowledge is asserted as specified by WS
End of enumeration elements list.
BLS : Byte-lane shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not shifted. Data is left-justfied on FB_AD.
#1 : 1
Shifted. Data is right justified on FB_AD.
End of enumeration elements list.
WS : Wait states
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write address hold or deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn)
#01 : 01
Hold address and attributes two cycles after FB_CSn negates on writes.
#10 : 10
Hold address and attributes three cycles after FB_CSn negates on writes.
#11 : 11
Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0)
End of enumeration elements list.
RDAH : Read address hold or deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
If AA is cleared, 1 cycle. If AA is set, 0 cycles.
#01 : 01
If AA is cleared, 2 cycles. If AA is set, 1 cycle.
#10 : 10
If AA is cleared, 3 cycles. If AA is set, 2 cycles.
#11 : 11
If AA is cleared, 4 cycles. If AA is set, 3 cycles.
End of enumeration elements list.
ASET : Address setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn)
#01 : 01
Assert FB_CSn on second rising clock edge after address is asserted.
#10 : 10
Assert FB_CSn on third rising clock edge after address is asserted.
#11 : 11
Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)
End of enumeration elements list.
EXTS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
FB_TS /FB_ALE asserts for one bus clock cycle
#1 : 1
FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts
End of enumeration elements list.
SWSEN : Secondary wait state enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers
#1 : 1
The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations
End of enumeration elements list.
SWS : Secondary wait states
bits : 26 - 31 (6 bit)
access : read-write
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